CN115800923A - RC oscillator and electronic equipment - Google Patents
RC oscillator and electronic equipment Download PDFInfo
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- CN115800923A CN115800923A CN202211481256.XA CN202211481256A CN115800923A CN 115800923 A CN115800923 A CN 115800923A CN 202211481256 A CN202211481256 A CN 202211481256A CN 115800923 A CN115800923 A CN 115800923A
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Abstract
The application relates to the field of oscillators, and discloses an RC oscillator and electronic equipment, wherein the RC oscillator comprises a bias circuit, a comparison circuit and an oscillation circuit; the bias circuit is used for copying the accessed reference current into two paths of bias current through the two stages of current mirror units and outputting the bias current; the oscillating circuit is used for charging and discharging corresponding capacitors in the oscillating circuit according to the two paths of bias currents so as to turn over high and low levels; the comparison circuit is used for generating a periodic clock oscillation signal according to the first path of bias current and the high-low level overturning result. According to the embodiment of the application, the two stages of current mirror units are arranged, so that the coupling interference of oscillation frequency to current can be effectively shielded, and the frequency precision of a clock oscillation signal output by the RC oscillator is improved; and the sizes of the resistor and the capacitor required in the RC oscillator are correspondingly reduced by adjusting the ratio of two paths of bias currents which are duplicated and output by the two stages of current mirror units, so that the area of a chip is effectively reduced.
Description
Technical Field
The application relates to the technical field of oscillators, in particular to an RC oscillator and electronic equipment.
Background
With the rapid development of the semiconductor integrated circuit technology level, oscillators are widely used in chips such as analog-to-digital converters (ADCs), charge pumps, and low dropout regulators (LDO regulators) as an important basic module in integrated circuit design. The oscillator provides a clock reference frequency for the chip, and can be used for switching operation when the charge pump boosts the voltage and setting a driving period for the digital control logic part.
At present, the conventional RC oscillator has a simple structure, but the oscillation frequency of the output of the RC oscillator has a large influence factor with the power supply voltage, the temperature and the like. Particularly, the temperature has a large influence on the internal current of the RC oscillator, so that the oscillation frequency of the RC oscillator is greatly influenced; therefore, the bias circuit is often specially designed to reduce the influence of the current on the oscillation frequency, but when the corresponding bias circuit is added, the chip area and the circuit power consumption are greatly increased.
Furthermore, how to design an oscillator so that the output oscillation frequency is not affected by the external current and the chip area is effectively reduced is an urgent problem to be solved.
Disclosure of Invention
In view of the above, to solve the problems of the prior art, the present application provides an RC oscillator and an electronic device.
In a first aspect, the present application provides an RC oscillator comprising a bias circuit, a comparison circuit and an oscillation circuit;
the bias circuit is used for copying the accessed reference current into two bias current outputs through the two stages of current mirror units;
the oscillating circuit is used for charging and discharging corresponding capacitors in the oscillating circuit according to the two paths of bias currents so as to turn high and low levels;
the comparison circuit is used for generating a periodic clock oscillation signal according to the first path of bias current and the high-low level overturning result.
In an alternative embodiment, the bias circuit includes a first stage current mirror unit and a second stage current mirror unit;
the first-stage current mirror unit comprises first to fourth switching tubes, and is used for accessing a reference current and copying the reference current to the second-stage current mirror unit;
the second-stage current mirror unit comprises fifth to tenth switching tubes and is used for copying the reference current into two paths of bias current to be output.
In an optional embodiment, the first end and the second end of the first switching tube and the first end of the second switching tube in the first-stage current mirror unit are both connected to the reference current;
the third end of the first switching tube is respectively connected with the first end and the second end of the third switching tube and the first end of the fourth switching tube;
the third end of the third switching tube is connected with the second end of the fourth switching tube, and the third end of the third switching tube is connected with the second end of the fourth switching tube and is grounded;
and the third end of the fourth switching tube is connected with the second end of the second switching tube, and the third end of the second switching tube is connected with the second-stage current mirror unit.
In an optional embodiment, a first end of a fifth switching tube, a first end of a sixth switching tube and a first end of a seventh switching tube in the second-stage current mirror unit are all connected to a power supply voltage source;
the second end of the fifth switching tube, the second end of the sixth switching tube and the second end of the seventh switching tube are connected in sequence;
the second end and the third end of the fifth switching tube are respectively connected with the first end of an eighth switching tube, and the second end and the third end of the eighth switching tube, the first end of the ninth switching tube and the first end of the tenth switching tube are connected with the first-stage current mirror unit;
a second end of the tenth switching tube is connected with a third end of the seventh switching tube, and the third end of the tenth switching tube is used for outputting a first path of bias current;
the second end of the ninth switching tube is connected with the third end of the sixth switching tube, and the third end of the ninth switching tube is used for outputting a second path of bias current.
In an alternative embodiment, the oscillation circuit comprises a first oscillation branch, a second oscillation branch and a third oscillation branch;
the first oscillation branch and the third oscillation branch have the same structure;
one end of each of the first oscillation branch, the second oscillation branch and the third oscillation branch is connected with two paths of bias currents; the other ends of the first oscillation branch, the second oscillation branch and the third oscillation branch are all grounded.
In an alternative embodiment, the first oscillation branch comprises an eleventh switch tube, a twelfth switch tube and a first capacitor;
the second oscillation branch comprises a second capacitor, a third capacitor and a resistor;
the second oscillation branch comprises a thirteenth switching tube, a fourteenth switching tube and a fourth capacitor.
In an optional embodiment, a first end of the eleventh switch tube is used for connecting two paths of the bias current;
a second end of the eleventh switching tube is configured to output a first phase control signal, and a third end of the eleventh switching tube is connected to a first end of the twelfth switching tube and one end of the first capacitor, respectively;
and the second end of the twelfth switching tube is used for outputting a second phase control signal, and the third end of the twelfth switching tube and the other end of the first capacitor are both grounded.
In an optional embodiment, the second capacitor, the third capacitor and a first parallel end of the resistor are used for connecting two paths of the bias current;
and the second parallel ends of the second capacitor, the third capacitor and the resistor are grounded.
In an optional embodiment, the comparison circuit comprises a fifteenth switching tube, a sixteenth switching tube, an amplifier, a schmitt trigger and a plurality of inverters connected in series;
the first end of the fifteenth switching tube and the first end of the sixteenth switching tube are both used for accessing the same path of bias current; the second end of the fifteenth switching tube and the second end of the sixteenth switching tube are both connected with the input end of the amplifier;
the output end of the amplifier is connected with the input end of the Schmitt trigger, and the output end of the Schmitt trigger is connected with the input ends of the plurality of inverters which are connected in series.
In a second aspect, an embodiment of the present application provides an electronic device, which includes the RC oscillator as described above.
The embodiment of the application has the following beneficial effects:
the RC oscillator provided by the embodiment of the application comprises a bias circuit, a comparison circuit and an oscillation circuit; the bias circuit is used for copying the accessed reference current into two paths of bias current through the two stages of current mirror units and outputting the bias current; the oscillating circuit is used for charging and discharging corresponding capacitors in the oscillating circuit according to the two paths of bias currents so as to turn over high and low levels; the comparison circuit is used for generating a periodic clock oscillation signal according to the first path of bias current and the high-low level overturning result. According to the RC oscillator provided by the embodiment of the application, on the first hand, by arranging the structure of the two stages of current mirror units, the coupling interference of the oscillation frequency to the current can be effectively shielded, and the influence of the external current on the oscillation frequency is avoided, so that when the RC oscillator is applied to a chip, the frequency precision of a clock signal output by the RC oscillator can be effectively improved; in a second aspect, the RC oscillator provided in the embodiment of the present application can correspondingly reduce the size of the required resistor and capacitor by adjusting the ratio of the two paths of bias currents duplicated and output by the two stages of current mirror units, so as to effectively reduce the chip area.
Drawings
To more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of the present application. Like components are numbered similarly in the various figures.
FIG. 1 shows a schematic circuit diagram of a conventional RC oscillator;
FIG. 2 is a schematic diagram of a first structure of an RC oscillator in the embodiment of the present application;
FIG. 3 is a diagram illustrating a second structure of an RC oscillator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a third structure of an RC oscillator in the embodiment of the present application;
fig. 5 shows a timing diagram of high-low level inversion in the embodiment of the present application.
Description of the main element symbols: 100-a bias circuit; 110-a first stage current mirror unit; 120-a second stage current mirror unit; 200-a comparison circuit; 300-an oscillating circuit; 310-a first oscillating branch; 320-a second oscillating branch; 330-third oscillation branch.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numerals, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the presence of or adding to one or more other features, numerals, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as terms defined in a commonly used dictionary) will be construed to have the same meaning as the contextual meaning in the related art and will not be construed to have an idealized or overly formal meaning unless expressly so defined in various embodiments of the present application.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a conventional RC oscillator, in which a level inversion is performed according to a comparison result between a voltage value corresponding to a charged and discharged capacitor in a circuit and a fixed voltage value at a certain position in the circuit, so as to generate a clock oscillation signal based on the level inversion.
As shown in fig. 1, KP and KN are two clock signals with opposite phases, and if the voltage value of the VIP terminal is a fixed voltage value (VIP = I5 × R2) at the initial time after power-on, the voltage value of the VIN terminal is lower than that of the VIP terminal; meanwhile, KP is a low level signal, KN is a high level signal, and the capacitor C5 is charged by the current I4 to store energy.
When the voltage value of VIN end was higher than the voltage value of VIP end, the high-low level upset, KP was high level signal, KN was low level signal this moment, and the voltage value of VIN end is: VIN = I4 × R2, the capacitor C7 is charged by I5 current.
When the voltage value of the polar plate on the capacitor C7 is higher than the voltage value (I4 × R2) of the VIN terminal, that is, the voltage value of the VIP terminal is higher than the voltage value of the VIN terminal again, the high level and the low level are inverted; at this time, signal oscillation of one period is completed, and the rest is repeated in the following oscillation period.
Wherein the oscillation period (f) is:
since the conventional RC oscillator has the same current value as the currents I4 and I5, the oscillation frequency (frequency) of the finally generated clock oscillation signal is related only to the capacitance value and the resistance value, that is, the oscillation frequency is independent of the current in the conventional RC oscillator. The oscillation frequency error of the clock oscillation signal generated finally is only related to the mismatch of the operational amplifier and the delay time of the logic gate in the oscillation circuit of the conventional RC oscillator.
Therefore, if the conventional RC oscillator is adopted to form a low-frequency, low-power consumption clock, since the current values of I4 and I5 are equal, the oscillation frequency of the clock oscillation signal is only related to the resistance and the capacitance; furthermore, when the oscillation frequency is required to be small, a large resistor and a large capacitor are required, and the large resistor and the large capacitor increase the chip area of the RC oscillator, so that the chip area is required to meet the requirement.
Based on this, the embodiment of the present application provides an RC oscillator, which ensures that the oscillation frequency of the output of the RC oscillator is not changed by reducing the values of a capacitor and a resistor in a circuit by using a current ratio, thereby greatly reducing the chip area of the RC oscillator of a low-frequency clock.
Example 1
Referring to fig. 2, fig. 3, and fig. 4, an embodiment of the present invention provides an RC oscillator, which includes a bias circuit 100, a comparison circuit 200, and an oscillation circuit 300; the bias circuit 100 is configured to copy the connected reference current (e.g., IREF1 shown in fig. 4) into two bias current outputs through two stages of current mirror units; the oscillating circuit 300 is configured to charge and discharge a corresponding capacitor in the oscillating circuit according to the two paths of bias currents to perform high-low level inversion; the comparator circuit 200 is configured to generate a periodic clock oscillation signal according to the first bias current (e.g., I2 in fig. 4) and a result of the high-low level inversion.
In the present embodiment, the bias circuit 100 includes a first-stage current mirror unit 110 and a second-stage current mirror unit 120. Exemplarily, the first stage current mirror unit 110 includes first to fourth switching tubes, and the first stage current mirror unit 110 is configured to switch in a reference current (IREF 1 shown in fig. 4) and copy the reference current to the second stage current mirror unit 120; the second stage current mirror unit 120 includes fifth to tenth switching tubes, and the second stage current mirror unit 120 is configured to copy the reference current into two bias current outputs.
In this embodiment, the first end and the second end of the first switch tube and the first end of the second switch tube in the first-stage current mirror unit 110 are both connected to a reference current; the third end of the first switching tube is respectively connected with the first end and the second end of the third switching tube and the first end of the fourth switching tube; the third end of the third switching tube is connected with the second end of the fourth switching tube, and the third end of the third switching tube and the second end of the fourth switching tube are both grounded; the third end of the fourth switching tube is connected to the second end of the second switching tube, and the third end of the second switching tube is connected to the second-stage current mirror unit 120.
In this embodiment, the first to fourth switching tubes may be NMOS tubes, and further, the first to fourth switching tubes are the first to fourth NMOS tubes, respectively, and the drain and the gate of the first NMOS tube (NM 1) and the gate of the second NMOS tube (NM 2) in the first-stage current mirror unit 110 are both connected to the reference current; the source electrode of the first NMOS tube (NM 1) is respectively connected with the drain electrode and the grid electrode of the third NMOS tube (NM 3) and the grid electrode of the fourth NMOS tube (NM 4); the source electrode of the third NMOS tube (NM 3) is connected with the source electrode of the fourth NMOS tube (NM 4); the source electrode of the third NMOS tube (NM 3) and the source electrode of the fourth NMOS tube (NM 4) are grounded; the drain of the fourth NMOS transistor (NM 4) is connected to the source of the second NMOS transistor (NM 2), and the drain of the second NMOS transistor (NM 2) is connected to the second-stage current mirror unit 120.
A first end of a fifth switching tube, a first end of a sixth switching tube and a first end of a seventh switching tube in the second-stage current mirror unit 120 are all connected to a power supply voltage source; the second end of the fifth switching tube, the second end of the sixth switching tube and the second end of the seventh switching tube are sequentially connected; the second end and the third end of the fifth switching tube are respectively connected with the first end of the eighth switching tube, and the second end and the third end of the eighth switching tube, the first end of the ninth switching tube and the first end of the tenth switching tube are all connected with the third end of the second switching tube in the first-stage current mirror unit 110; the second end of the ninth switching tube is connected with the third end of the sixth switching tube, and the third end of the ninth switching tube is used for outputting a second path of bias current (I1); the second end of the tenth switching tube is connected with the third end of the seventh switching tube, and the third end of the tenth switching tube is used for outputting the first path of bias current (I2).
In this embodiment, the fifth to eighth switching tubes may be PMOS tubes, and the fifth to eighth switching tubes are corresponding to the first to fourth PMOS tubes, respectively; the drain electrode of a first PMOS transistor (PM 1), the drain electrode of a second PMOS transistor (PM 2), and the drain electrode of a third PMOS transistor (PM 3) in the second-stage current mirror unit 120 are all connected to a power supply voltage source; the grid electrode of the first PMOS tube (PM 1), the grid electrode of the second PMOS tube (PM 2) and the grid electrode of the third PMOS tube (PM 3) are sequentially connected; the source electrode and the grid electrode of the first PMOS tube (PM 1) are both connected with the drain electrode of the fourth PMOS tube; the grid and the source of the fourth PMOS transistor (PM 4), the grid of the fifth PMOS transistor (PM 5) and the grid of the sixth PMOS transistor (PM 6) are all connected to the drain of the second NMOS transistor (NM 2) in the first-stage current mirror unit 110; the drain electrode of the fifth PMOS tube (PM 5) is connected with the source electrode of the sixth PMOS tube (PM 6), and the source electrode of the fifth PMOS tube (PM 5) is used for outputting the second path of bias current; the drain electrode of the sixth PMOS tube (PM 6) is connected with the source electrode of the third PMOS tube (PM 3), and the source electrode of the sixth PMOS tube (PM 6) is used for outputting the first path of bias current.
The oscillating circuit 300 comprises a first oscillating branch 310, a second oscillating branch 320 and a third oscillating branch 330; the first oscillation branch 310 and the third oscillation branch 330 have the same structure; two paths of bias currents are connected to one end of the first oscillation branch 310, one end of the second oscillation branch 320 and one end of the third oscillation branch 330; the other ends of the first oscillation branch 310, the second oscillation branch 320 and the third oscillation branch 330 are all grounded.
Exemplarily, the first oscillation branch 310 includes an eleventh switch tube, a twelfth switch tube, and a first capacitor C1; the second oscillation branch 320 comprises a second capacitor C2, a third capacitor C3 and a resistor R1; the third oscillating branch 330 includes a thirteenth switching tube, a fourteenth switching tube and a fourth capacitor C4.
The first end of the eleventh switch tube and the first end of the thirteenth switch tube are both used for connecting two paths of bias current, the second end of the eleventh switch tube is used for outputting a first phase control signal, the third end of the eleventh switch tube is respectively connected with the first end of the twelfth switch tube and one end of the first capacitor C1, the second end of the twelfth switch tube is used for outputting a second phase control signal, and the third end of the twelfth switch tube and the other end of the first capacitor C1 are both grounded.
The second capacitor C2, the resistor R1 and the third capacitor C3 are connected in parallel, first parallel ends of the second capacitor C2, the resistor R1 and the third capacitor C3 are used for being connected with two paths of bias current, and second parallel ends of the second capacitor C2, the resistor R1 and the third capacitor C3 are grounded.
The first end of the thirteenth switching tube is used for connecting two paths of bias current, the second end of the thirteenth switching tube is used for outputting a second phase control signal, the third end of the thirteenth switching tube is respectively connected with the first end of the fourteenth switching tube and one end of the fourth capacitor C4, the second end of the fourteenth switching tube is used for outputting a first phase control signal, and the third end of the fourteenth switching tube and the other end of the fourth capacitor C4 are grounded.
Exemplarily, the eleventh to fourteenth switching tubes may all be NMOS tubes, and further, the eleventh to fourteenth switching tubes are respectively corresponding to the fifth to eighth NMOS tubes.
Specifically, the drain of the fifth NMOS transistor (NM 5) and the drain of the seventh NMOS transistor (NM 7) are both used for accessing two paths of bias currents, the gate of the fifth NMOS transistor (NM 5) is used for outputting a first phase control signal, the source of the fifth NMOS transistor (NM 5) is connected to the drain of the sixth NMOS transistor (NM 6) and one end of the first capacitor C1, the gate of the sixth NMOS transistor (NM 6) is used for outputting a second phase control signal, and the source of the sixth NMOS transistor (NM 6) and the other end of the first capacitor C1 are both grounded.
The drain electrode of the seventh NMOS tube (NM 7) is used for accessing two paths of bias current, the grid electrode of the seventh NMOS tube (NM 7) is used for outputting a second phase control signal, the source electrode of the seventh NMOS tube (NM 7) is respectively connected with the drain electrode of the eighth NMOS tube (NM 8) and one end of the fourth capacitor C4, the grid electrode of the eighth NMOS tube (NM 8) is used for outputting a first phase control signal, and the source electrode of the eighth NMOS tube (NM 8) and the other end of the fourth capacitor C4 are both grounded.
The first phase control signal is a PHN control signal, and the second phase control signal is a PHP control signal. The PHN control signal and the PHP control signal are in opposite phases.
Exemplarily, the comparison circuit 200 includes a fifteenth switch, a sixteenth switch, an amplifier COMP, a schmitt trigger SMIT, and a plurality of inverters INV connected in series. The specific number of the inverters INV is not limited herein, and a plurality of inverters INV are connected in series.
The first end of the fifteenth switching tube and the first end of the sixteenth switching tube are both used for accessing the same bias current; the second end of the fifteenth switching tube and the second end of the sixteenth switching tube are both connected with the input end of an amplifier COMP; the output end of the amplifier COMP is connected with the input end of a Schmitt trigger SMIT, and the output end of the Schmitt trigger SMIT is connected with the input ends of the plurality of inverters INV which are connected in series. The third end of the fifteenth switching tube is used for inputting the second phase control signal, and the third end of the sixteenth switching tube is used for inputting the first phase control signal.
In an embodiment, the fifteenth switching tube and the sixteenth switching tube both use NMOS tubes, and further, the fifteenth switching tube and the sixteenth switching tube correspond to a ninth NMOS tube and a tenth NMOS tube.
The grid electrode of the ninth NMOS tube (NM 9) is used for inputting a PHP control signal, the source electrode of the ninth NMOS tube (NM 9) is used for accessing the second path of bias current, and the drain electrode of the ninth NMOS tube (NM 9) is connected with the first input end of the amplifier COMP; the grid electrode of the tenth NMOS tube (NM 10) is used for inputting a PHN control signal, the drain electrode of the tenth NMOS tube (NM 10) is used for accessing the second path of bias current, and the source electrode of the tenth NMOS tube (NM 10) is connected with the second input end of the amplifier COMP.
In one embodiment, as shown in fig. 3, the present embodiment is described by taking three Inverters (INV) as an example, where an input terminal of the first inverter is connected to an output terminal of the schmitt trigger SMIT, an output terminal of the first inverter outputs the PHP control signal to an input terminal of the second inverter, an output terminal of the second inverter outputs the PHN control signal to an input terminal of the third inverter, and an output terminal of the third inverter outputs the periodic clock oscillation signal (CLK).
In this embodiment, an input reference current is copied to the oscillation circuit through the two-stage current mirror unit to charge the corresponding capacitor (the first capacitor C1 or the fourth capacitor C4) and the resistor (the resistor R1). The fixed voltage value, i.e., the voltage value across the resistor R1, is (I2 × R1). When the PHN control signal and the PHP control signal are input, the PHN control signal indicates that the switching tube is turned on, and the PHP control signal indicates that the switching tube is turned off, so as to provide the second path of bias current (I1) to charge the first capacitor C1, and the fourth capacitor C4 is discharged through the fourteenth switching tube (NM 8).
When the voltage value of the end of the first capacitor C1 is higher than the voltage values of the two ends of the resistor R1, the high and low levels are turned over, the input PHN control signal indicates that the switch tube is turned off, and the PHP control signal indicates that the switch tube is turned on; at this time, the first capacitor C1 is discharged through the twelfth switching tube (NM 6), and the first path of bias current (I2) is provided to charge the fourth capacitor C4.
When the charging voltage value of the fourth capacitor C4 is higher than the voltage value at the two ends of the resistor R1, that is, the voltage value at the VIN end is higher than the voltage value at the VIP end, the high and low levels are inverted again, that is, after two high and low level inversions are completed, the oscillation of one period is completed, and so on in the subsequent oscillation period.
As shown in fig. 5, fig. 5 is a timing diagram of high-low level inversion, and the voltage across the resistor R1 is obtained as follows:
V R1 ＝I2*R1；
wherein, V R1 The voltage value across the resistor R1 is shown, and I2 is the bias current when the resistor R1 is charged.
The voltage value across the first capacitor C1 or the fourth capacitor C4 is:
V C ＝I1*T1；
wherein, V C The voltage value of the two ends of the first capacitor C1 or the fourth capacitor C4 is shown, and T1 represents the charging time when the first capacitor C1 or the fourth capacitor C4 is charged.
The condition of high and low level turnover is V R1 And V C If the voltages at the two ends are equal, the following can be derived:
C1*V R1 ＝I1*T1；
further, the oscillation cycle or oscillation frequency (f) of the clock signal output from the comparator circuit 200 is:
according to the above calculation formula of the oscillation period, it can be understood that the magnitude of the oscillation period or the oscillation frequency is related to the ratio, the resistance value and the capacitance value of the two bias currents.
For example, if the second path of bias current I2 has an error factor, it is assumed as α, because the first path of bias current I1 and I2 are copied from the same current mirror unit, and if the current value of I1 is β times the current value of I2, the error factor is β × α times, and the error factor α can be removed, so as to obtain an RC oscillator whose oscillation period is independent of the current value. Under the condition that the oscillation frequency accuracy of the RC oscillator in the embodiment is the same as that of the conventional RC oscillator shown in fig. 1, the values of the resistor and the capacitor can be correspondingly reduced by adjusting the ratio between the two paths of bias currents I1 and I2, so that a larger resistor and a larger capacitor are not required, and the chip area of the RC oscillator is effectively reduced.
According to the RC oscillator provided by the embodiment of the application, on the first hand, by arranging the structure of the two stages of current mirror units, the coupling interference of the oscillation frequency to the current can be effectively shielded, and the influence of the external current on the oscillation frequency is avoided, so that when the RC oscillator is applied to a chip, the frequency precision of a clock signal output by the RC oscillator can be effectively improved; in a second aspect, the RC oscillator provided in the embodiment of the present application can correspondingly reduce the sizes of the required resistor and capacitor by adjusting the ratio of the two paths of bias currents duplicated and output by the two stages of current mirror units, so as to effectively reduce the chip area; in a third aspect, when a hardware test is performed on the RC oscillator, since the RC oscillator provided in the embodiments of the present application is an RC oscillator with a low-area circuit structure, a capacitance value is small, and when a frequency is adjusted during a hardware test, the resistance value can be finely adjusted by roughly adjusting the capacitance value to improve the accuracy of the oscillation frequency, so that an influence of the hardware test on each circuit in the RC oscillator can be prevented.
An embodiment of the present application further provides an electronic device, where the electronic device includes the RC oscillator of the above embodiment, and any optional item of the RC oscillator of the above embodiment may be applicable to the electronic device of this embodiment, which is not described herein again. The electronic device includes, but is not limited to, a communication device, an am radio, an audio generator, a frequency synthesizer, a central processing unit, a communication station, a quartz watch, and the like.
In all examples shown and described herein, any particular value should be construed as exemplary only and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application.
Claims (10)
1. An RC oscillator is characterized by comprising a bias circuit, a comparison circuit and an oscillation circuit;
the bias circuit is used for copying the accessed reference current into two bias current outputs through the two stages of current mirror units;
the oscillation circuit is used for charging and discharging corresponding capacitors in the oscillation circuit according to the two paths of bias currents so as to turn high and low levels;
the comparison circuit is used for generating a periodic clock oscillation signal according to the first path of bias current and the high-low level overturning result.
2. The RC oscillator of claim 1, wherein the bias circuit comprises a first stage current mirror unit and a second stage current mirror unit;
the first-stage current mirror unit comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, and is used for accessing a reference current and copying the reference current to the second-stage current mirror unit;
the second-stage current mirror unit comprises fifth to tenth switching tubes and is used for copying the reference current into two paths of bias current to be output.
3. The RC oscillator according to claim 2, wherein the first and second ends of the first and second switching tubes in the first stage current mirror unit are connected to the reference current;
the third end of the first switching tube is respectively connected with the first end and the second end of the third switching tube and the first end of the fourth switching tube;
the third end of the third switching tube is connected with the second end of the fourth switching tube, and the third end of the third switching tube is connected with the second end of the fourth switching tube and is grounded;
and the third end of the fourth switching tube is connected with the second end of the second switching tube, and the third end of the second switching tube is connected with the second-stage current mirror unit.
4. The RC oscillator according to claim 2, wherein the first end of the fifth switching tube, the first end of the sixth switching tube and the first end of the seventh switching tube in the second stage current mirror unit are all connected to a supply voltage source;
the second end of the fifth switching tube, the second end of the sixth switching tube and the second end of the seventh switching tube are sequentially connected;
the second end and the third end of the fifth switching tube are respectively connected with the first end of an eighth switching tube, and the second end and the third end of the eighth switching tube, the first end of the ninth switching tube and the first end of the tenth switching tube are connected with the first-stage current mirror unit;
the second end of the ninth switching tube is connected with the third end of the sixth switching tube, and the third end of the ninth switching tube is used for outputting a second path of bias current;
the second end of the tenth switching tube is connected to the third end of the seventh switching tube, and the third end of the tenth switching tube is used for outputting the first path of bias current.
5. The RC oscillator of claim 1, wherein the oscillating circuit comprises a first oscillating branch, a second oscillating branch and a third oscillating branch;
the first oscillation branch and the third oscillation branch have the same structure;
one end of each of the first oscillation branch, the second oscillation branch and the third oscillation branch is connected with two paths of bias current; the other ends of the first oscillation branch, the second oscillation branch and the third oscillation branch are all grounded.
6. The RC oscillator of claim 5, wherein the first oscillation branch comprises an eleventh switch tube, a twelfth switch tube and a first capacitor;
the second oscillation branch comprises a second capacitor, a third capacitor and a resistor;
the second oscillation branch comprises a thirteenth switching tube, a fourteenth switching tube and a fourth capacitor.
7. The RC oscillator of claim 6, wherein a first terminal of the eleventh switch is configured to connect two paths of the bias current;
a second end of the eleventh switching tube is configured to output a first phase control signal, and a third end of the eleventh switching tube is connected to a first end of the twelfth switching tube and one end of the first capacitor, respectively;
and the second end of the twelfth switching tube is used for outputting a second phase control signal, and the third end of the twelfth switching tube and the other end of the first capacitor are both grounded.
8. The RC oscillator of claim 6, wherein the first parallel terminals of the second capacitor, the third capacitor and the resistor are used for connecting two paths of the bias current;
and the second parallel ends of the second capacitor, the third capacitor and the resistor are grounded.
9. The RC oscillator of claim 1, wherein the comparison circuit comprises a fifteenth switching tube, a sixteenth switching tube, an amplifier, a schmitt trigger and a plurality of inverters connected in series;
the first end of the fifteenth switching tube and the first end of the sixteenth switching tube are both used for accessing the same bias current; the second end of the fifteenth switching tube and the second end of the sixteenth switching tube are both connected with the input end of the amplifier;
the output end of the amplifier is connected with the input end of the Schmitt trigger, and the output end of the Schmitt trigger is connected with the input ends of the plurality of inverters which are connected in series.
10. An electronic device comprising the RC oscillator of any of claims 1-9.
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| CN202211481256.XA CN115800923A (en) | 2022-11-24 | 2022-11-24 | RC oscillator and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117394689A (en) * | 2023-10-24 | 2024-01-12 | 上海帝迪集成电路设计有限公司 | Power supply unit with self-adaptive wide working voltage range and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117394689A (en) * | 2023-10-24 | 2024-01-12 | 上海帝迪集成电路设计有限公司 | Power supply unit with self-adaptive wide working voltage range and control method thereof |
| CN117394689B (en) * | 2023-10-24 | 2024-03-08 | 上海帝迪集成电路设计有限公司 | Power supply unit with self-adaptive wide working voltage range and control method thereof |
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