CN101465631A - Delay circuit - Google Patents
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- CN101465631A CN101465631A CN 200710162170 CN200710162170A CN101465631A CN 101465631 A CN101465631 A CN 101465631A CN 200710162170 CN200710162170 CN 200710162170 CN 200710162170 A CN200710162170 A CN 200710162170A CN 101465631 A CN101465631 A CN 101465631A
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Abstract
Disclosed is a delay circuit capable of providing high-stability delay time for digital signal processing, which comprises a pre-stage charge-discharge circuit, a signal processing circuit and an output circuit. the pre-stage charge-discharge circuit executes charge-discharge program according to a logic input signal and generates a voltage signal; the signal processing circuit executes signal processing to generate a first delay signal and a second delay signal according to the voltage signal; the output circuit executes the logic signal processing of the first delay signal and the second delay signal to generate a logic output signal which is later than the logic input signal to a delay time; the delay time is unrelated to power supply voltage, so even if the power supply voltage is unstable, the delay circuit can execute the signal delay processing of the logic input signal without the influence of power supply voltage, and generate a stable logic output signal.
Description
Technical field
The invention relates to a kind of delay circuit, refer to especially a kind ofly not influenced by mains voltage variations and can provide high stable time of delay in the delay circuit of Digital Signal Processing.
Background technology
In many circuit, for example time-pulse signal generator (clockgenerator) or radio frequency transmission receiver (RF transceiver), accuracy requirement for signal phase is quite high, when these signal phases produce deviations, can produce considerable influence to whole system.As in leggy time-pulse signal generator (multi-phase clockgenerator), the accuracy of the phase difference between each output signal is also quite important, when phase error increases, the clock pulse shake (jitter) of output clock signal also can increase, this is for the system of the accurate clock signal of needs, may cause the late-class circuit grave error, for example sampling point mistake of analog-to-digital converter, or bit error rate (biterror rate) rises.Therefore, when design needs the circuit of high phase accuracy, all can its layout path of handled, yet when supplying voltage generation drift phenomenon, the known delay circuit engineering can't provide phase delay accurately usually, and just need utilize extra mechanism that correction is done in phase deviation this moment.
Known delay circuit technology mainly is to utilize the effect that discharges and recharges of electric capacity to come the signal that next stage is delivered in tendency to develop is postponed to handle, and please refer to Fig. 1, and Fig. 1 is the circuit diagram that shows a known delay circuit 100.Delay circuit 100 comprises a prime charge-discharge circuit 105 and an inverter 190.Prime charge-discharge circuit 105 comprises one first current source 110, one second current source 112, one first control switch 120, one second control switch 122, reaches an electric capacity 130.Inverter 190 comprises a P passage burning half-court effect transistor (PMOSFET) 180 and a N passage burning half-court effect transistor (NMOSFET) 182.Delay circuit 100 is coupled between one first supply voltage Vdd and the one second supply voltage Vss, and first control switch 120 and second control switch 122 are to be controlled by a logic input signal Sin.According to the on off state of first control switch 120 and second control switch 122, first current source 110 and second current source 112 can be carried out charging and discharge operation to capacitor 130, in order to produce voltage signal Vc.Inverter 190 is carried out the signal inversion of the voltage signal Vc of electric capacity 130 and is handled, to produce the backward logic input signal Sin logic output signal Sout of one time of delay.
But when the first supply voltage Vdd or second supplies the supply voltage drift of voltage Vss, the transition voltage that inputs to output of inverter 190 with change, the voltage range that corresponds to time of delay that electric capacity 130 is discharged and recharged changes, be directed at and also change the time of delay that inputs to output, in other words, when the supply voltage instability regularly, time of delay also with instability.
Please refer to Fig. 2, Fig. 2 is the circuit diagram that shows another known delay circuit 200.Delay circuit 200 comprises a prime charge-discharge circuit 205 and a comparison circuit 290.Prime charge-discharge circuit 205 is in order to producing voltage signal Vc according to logic input signal Sin, its internal circuit configuration with above-mentioned prime charge-discharge circuit 105 is identical, so repeat no more.Comparison circuit 290 comprises one first divider resistance 291, one second divider resistance 292, reaches a comparator 295.First divider resistance 291 and one second divider resistance 292 are coupled between the first supply voltage Vdd and the second supply voltage Vss, in order to a comparison reference voltage Vr to be provided.Comparator 295 is carried out the signal comparison process of voltage signal Vc and comparison reference voltage Vr, in order to produce logic output signal Sout.
Summary of the invention
The objective of the invention is to, a kind of delay circuit is provided, it can not supplied the influence of voltage drift.In addition, in the circuit layout design, need not expend suitable divider resistance element area, help the reduction of circuit closeness and production cost.
According to embodiments of the invention, it discloses a kind of delay circuit, comprises a prime charge-discharge circuit, a signal processing circuit, reaches an output circuit.The prime charge-discharge circuit comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and the prime charge-discharge circuit is to produce voltage signal in order to carry out the program that discharges and recharges according to logic input signal.Signal processing circuit is coupled in the output of prime charge-discharge circuit to receive voltage signal, in order to produce one first inhibit signal and one second inhibit signal according to voltage signal, signal processing circuit comprises one first current source, a first transistor, one second current source, reaches a transistor seconds.First current source comprises one first end in order to receive one first supply voltage, reaches one second end.The first transistor comprises one first end in order to receive one second supply voltage, one second end is coupled in second end of first current source, and the output that a control end is coupled in the prime charge-discharge circuit to be to receive voltage signal, and wherein second end of the first transistor is in order to export first inhibit signal.Second current source comprises one first end in order to receive the second supply voltage, reaches one second end.Transistor seconds comprises one first end in order to receive the first supply voltage, one second end is coupled in second end of second current source, and the output that a control end is coupled in the prime charge-discharge circuit to be to receive voltage signal, and wherein second end of transistor seconds is in order to export second inhibit signal.Output circuit comprises second end that a first input end is coupled in the first transistor, in order to receive first inhibit signal, one second input is coupled in second end of transistor seconds, in order to receive second inhibit signal, one the 3rd input is in order to the receive logic input signal, and an output is in order to exporting a logic output signal, output circuit according to first inhibit signal, second inhibit signal, and logic input signal produce logic output signal.
According to embodiments of the invention, it discloses a kind of delay circuit in addition, comprises a prime charge-discharge circuit, a signal processing circuit, reaches an output circuit.The prime charge-discharge circuit comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and the prime charge-discharge circuit is to produce voltage signal in order to carry out the program that discharges and recharges according to logic input signal.Signal processing circuit is coupled in the output of prime charge-discharge circuit to receive voltage signal, in order to produce one first inhibit signal and one second inhibit signal according to voltage signal, signal processing circuit comprises one first current source, a first transistor, one second current source, reaches a transistor seconds.First current source comprises one first end in order to receive one first supply voltage, reaches one second end.The first transistor comprises one first end in order to receive one second supply voltage, one second end is coupled in second end of first current source, and the output that a control end is coupled in the prime charge-discharge circuit to be to receive voltage signal, and wherein second end of the first transistor is in order to export first inhibit signal.Second current source comprises one first end in order to receive the second supply voltage, reaches one second end.Transistor seconds comprises one first end in order to receive the first supply voltage, one second end is coupled in second end of second current source, and the output that a control end is coupled in the prime charge-discharge circuit to be to receive voltage signal, and wherein second end of transistor seconds is in order to export second inhibit signal.Output circuit comprises second end that a first input end is coupled in the first transistor, in order to receive first inhibit signal, one second input is coupled in second end of transistor seconds, in order to receive second inhibit signal, reach an output in order to export a logic output signal, output circuit produces logic output signal according to first inhibit signal and second inhibit signal.
Description of drawings
For making the present invention more apparent and understandable, hereinafter, elaborate especially exemplified by the embodiment conjunction with figs. according to delay circuit of the present invention, but the scope that the embodiment that is provided is not contained in order to restriction the present invention, wherein:
Fig. 1 shows the circuit diagram of a known delay circuit.
Fig. 2 shows the circuit diagram of another known delay circuit.
Fig. 3 shows the circuit diagram according to the delay circuit of first embodiment of the invention.
The sequential chart of the work coherent signal of the delay circuit of Fig. 4 displayed map 3.
Fig. 5 shows the circuit diagram according to the delay circuit of second embodiment of the invention.
Fig. 6 shows the circuit diagram according to the delay circuit of third embodiment of the invention.
Fig. 7 shows the circuit diagram according to the delay circuit of fourth embodiment of the invention.
Embodiment
Please refer to Fig. 3, Fig. 3 is the circuit diagram that shows according to the delay circuit 300 of first embodiment of the invention.Delay circuit 300 comprises a prime charge-discharge circuit 305, a signal processing circuit 350, reaches an output circuit 380.Signal processing circuit 350 comprises one first current source 370, a first transistor 360, one second current source 372, reaches a transistor seconds 362.Prime charge-discharge circuit 305 comprises one the 3rd current source 310, one first control switch 320, one the 4th current source 312, one second control switch 322, reaches an electric capacity 330.Output circuit 380 comprises one first NOR gate (NOR gate), 381,1 second NOR gate 383, one the 3rd NOR gate 385, reaches a four nor gate 388.
The 3rd current source 310 comprises one first end and one second end, and wherein first end is in order to receive one first supply voltage Vdd, and second end is in order to supply an electric current I 3.First control switch 320 comprises one first end, one second end, reaches a control end, wherein first end is coupled in second end of the 3rd current source 310, in order to received current I3, control end is in order to receive a logic input signal Sin, second end is in order to output current I3, and first control switch 320 is in order to control the couple state of its first end and second end according to logic input signal Sin.The 4th current source 312 comprises one first end and one second end, and wherein first end is in order to receive one second supply voltage Vss, and second end can be an earthed voltage in order to supply an electric current I 4, the second supply voltage Vss.Second control switch 322 comprises one first end, one second end, reaches a control end, wherein first end is coupled in second end of the 4th current source 312, in order to received current I4, control end is in order to receive logic input signal Si n, second end is in order to output current I4, and second control switch 322 is in order to control the couple state of its first end and second end according to logic input signal Sin.First control switch 320 and second control switch 322 can be electronic type relay (Electronic Relay), burning half-court effect transistor (MOSTransistor) or two-carrier transistor (Bipolar Transistor).
Electric capacity 330 comprises one first end and one second end, and wherein first end is coupled in second end of first control switch 320, and in order to export a voltage signal Vc, second end is in order to receive the second supply voltage Vss.When logic input signal Sin is low level voltage, 320 conductings of first control switch and second control switch 322 end, so electric capacity 330 can be carried out charging procedure by the electric current I 3 that the 3rd current source 310 is provided, make voltage signal Vc rise to the first supply voltage Vdd.When logic input signal Sin is high levle voltage, first control switch 320 ends and 322 conductings of second control switch, so electric capacity 330 can be carried out discharge procedures by the electric current I 4 that the 4th current source 312 is provided, make voltage signal Vc drop to the second supply voltage Vss.
First current source 370 comprises one first end and one second end, and wherein first end is in order to receive the first supply voltage Vdd, and second end is in order to supply an electric current I 1.The first transistor 360 comprises one first end, one second end, an and control end, wherein first end is in order to receive the second supply voltage Vss, second end is coupled in second end of first current source 370, control end is coupled in first end of electric capacity 330, in order to receive voltage signal Vc, second end of the first transistor 360 is in order to exporting one first inhibit signal Sd1, and the first transistor 360 is to be a N passage burning half-court effect transistor (NMOS Field Effect Transistor) or a N passage junction field effect transistor (N-channel Junction FieldEffect Transistor).
Second current source 372 comprises one first end and one second end, and wherein first end is in order to receive the second supply voltage Vss, and second end is in order to supply an electric current I 2.Transistor seconds 362 comprises one first end, one second end, an and control end, wherein first end is in order to receive the first supply voltage Vdd, second end is coupled in second end of second current source 372, control end is coupled in first end of electric capacity 330, in order to receive voltage signal Vc, second end of transistor seconds 362 is in order to exporting one second inhibit signal Sd2, and transistor seconds 362 is to be a P passage burning half-court effect transistor (PMOS Field Effect Transistor) or a P passage junction field effect transistor (P-channel Junction FieldEffect Transistor).
First NOR gate 381 comprises a first input end, one second input, reaches an output, wherein first input end is in order to receive logic input signal Si n, second input is coupled in second end of transistor seconds 362, in order to receive the second inhibit signal Sd2, output is in order to output actuating logic input signal Si n and the logical inverse of the second inhibit signal Sd2 or one first signal that processing produced.Second NOR gate 383 comprises a first input end, one second input, reaches an output, wherein first input end is coupled in second end of transistor seconds 362, in order to receive the second inhibit signal Sd2, second input is coupled in second end of the first transistor 360, in order to receive the first inhibit signal Sd1, output is carried out the first inhibit signal Sd1 and the logical inverse of the second inhibit signal Sd2 or the secondary signal that processing produced in order to output.The 3rd NOR gate 385 comprises a first input end, one second input, reaches an output, wherein first input end is in order to receive logic input signal Si n, second input is coupled in second end of the first transistor 360, in order to receive the first inhibit signal Sd1, output is in order to output actuating logic input signal Si n and the logical inverse of the first inhibit signal Sd1 or one the 3rd signal that processing produced.
Four nor gate 388 comprises a first input end, one second input, one the 3rd input, reaches an output, wherein first input end is coupled in the output of first NOR gate 381, in order to receive first signal, second input is coupled in the output of second NOR gate 383, in order to receive secondary signal, the 3rd input is coupled in the output of the 3rd NOR gate 385, in order to receive the 3rd signal, output is carried out first signal, secondary signal, the logical inverse that reaches the 3rd signal or the logic output signal Sout that processing produced in order to output.
Please refer to Fig. 4, Fig. 4 is the sequential chart of work coherent signal of the delay circuit 300 of displayed map 3, and transverse axis is a time shaft.Work coherent signal shown in Figure 4 from top to bottom is logic input signal Sin, voltage signal Vc, the first inhibit signal Sd1, the second inhibit signal Sd2 in regular turn, reach logic output signal Sout.Logic input signal Sin transfers high levle voltage in time T 1 to from low level voltage, first control switch 320 is transferred to by conducting and ending, second control switch 322 transfers conducting to by ending, electric capacity 330 is carried out discharge procedures by the electric current I 4 that the 4th current source 312 is provided, and the voltage of voltage signal Vc is successively decreased from the first supply voltage Vdd.When time T 2, the voltage grading of voltage signal Vc is to equaling one second transition voltage Vt2, and the voltage difference between the control end of transistor seconds 362 and first end, equal to correspond to one second critical voltage Vth2 of transistor seconds 362, make transistor seconds 362 transfer conducting to, so the second inhibit signal Sd2 just transfers high levle voltage to from low level voltage by ending.When time T 3, the voltage grading of voltage signal Vc is to equaling one first transition voltage Vt1, and the voltage difference between the control end of the first transistor 361 and first end, equal to correspond to one first critical voltage Vth1 of the first transistor 361, the first transistor 361 is transferred to by conducting end, so the first inhibit signal Sd1 just transfers high levle voltage to from low level voltage.
Logic input signal Sin transfers low level voltage in time T 4 to from high levle voltage, first control switch 320 transfers conducting to by ending, second control switch 322 is transferred to by conducting and ending, electric capacity 330 is carried out charging procedure by the electric current I 3 that the 3rd current source 310 is provided, and the voltage of voltage signal Vc is increased progressively from the second supply voltage Vss.When time T 5, the voltage delivery of voltage signal Vc increases to and equals the first transition voltage Vt1, and the voltage difference between the control end of the first transistor 361 and first end equals the first critical voltage Vth1, make the first transistor 361 transfer conducting to, so the first inhibit signal Sd1 just transfers low level voltage to from high levle voltage by ending.When time T 6, the voltage delivery of voltage signal Vc increases to and equals the second transition voltage Vt2, and the voltage difference of the control end of transistor seconds 362 and first end equals the second critical voltage Vth2, transistor seconds 362 is transferred to by conducting end, so the second inhibit signal Sd2 just transfers low level voltage to from high levle voltage.
The first inhibit signal Sd1, the second inhibit signal Sd2, and logic input signal Sin handle through the logical signal of output circuit 380, and produce logic output signal Sout shown in the 4th figure.The pulse wave leading edge of logic output signal Sout is with the pulse wave leading edge of the backward logic input signal Sin of one liter of edge time of delay (rising edgedelay time) DT1, and the pulse wave trailing edge of logic output signal Sout falls the pulse wave trailing edge that edge time of delay (falling edge delay time) DT2 falls behind logic input signal Sin with one.Rise edge DT1 time of delay and fall edge DT2 time of delay and can produce according to following formula (1) and (2) calculating.
Wherein, parameters C is the capacitance of electric capacity 330, and parameter I c3 is the current value of electric current I 3, and parameter I c4 is the current value of electric current I 4.Reach (2) as can be known according to above-listed formula (1), rising edge DT1 time of delay is by current value I c4, the second critical voltage Vth2, and capacitance C determines, and fall edge DT2 time of delay is by current value I c3, the first critical voltage Vth1, and capacitance C determines, therefore, all parameters of formula (1) and (2) are not influenced by the first supply voltage Vdd and the second supply voltage Vss all, in other words, when the first supply voltage Vdd or the second supply voltage Vss have the voltage drift phenomenon to take place, rise edge DT1 time of delay and fall edge DT2 time of delay all unaffected, delay circuit 300 still can produce stable logic output signal Sout according to logic input signal Sin.
Please refer to Fig. 5, Fig. 5 is the circuit diagram that shows according to the delay circuit 500 of second embodiment of the invention.Delay circuit 500 comprises a prime charge-discharge circuit 505, a signal processing circuit 550, reaches an output circuit 580.Signal processing circuit 550 comprises one first current source 570, a first transistor 560, one second current source 572, reaches a transistor seconds 562.Prime charge-discharge circuit 505 comprises one the 3rd current source 510, one first control switch 520, one the 4th current source 512, one second control switch 522, reaches an electric capacity 530.Output circuit 580 comprise one first or door (ORgate) 581, one second or door 583, the 3rd or door 585, and one with door (an AND gate) 588.
The internal circuit configuration of prime charge-discharge circuit 505 is identical with prime charge-discharge circuit 305, connects so repeat no more the circuit of its related elements.First current source 570 comprises one first end and one second end, and wherein first end is in order to receive the first supply voltage Vdd, and second end is in order to supply an electric current I 1.The first transistor 560 comprises one first end, one second end, reaches a control end, wherein first end is in order to receive the second supply voltage Vss, second end is coupled in second end of first current source 570, control end is coupled in electric capacity 530, in order to receive a voltage signal Vc, second end of the first transistor 560 is in order to exporting one first inhibit signal Sd1, and the first transistor 560 is to be a NPN two-carrier transistor (NPNbipolar transistor).
Second current source 572 comprises one first end and one second end, and wherein first end is in order to receive the second supply voltage Vss, and second end is in order to supply an electric current I 2.Transistor seconds 562 comprises one first end, one second end, reaches a control end, wherein first end is in order to receive the first supply voltage Vdd, second end is coupled in second end of second current source 572, control end is coupled in electric capacity 530, in order to receive voltage signal Vc, second end of transistor seconds 562 is in order to exporting one second inhibit signal Sd2, and transistor seconds 562 is to be a PNP two-carrier transistor (PNPbipolar transistor).
First or door 581 comprise a first input end, one second input, an and output, wherein first input end is in order to receive a logic input signal Sin, second input is coupled in second end of transistor seconds 562, in order to receive the second inhibit signal Sd2, output is handled one first signal that is produced in order to the logic OR of the output actuating logic input signal Si n and the second inhibit signal Sd2.Second or door 583 comprise a first input end, one second input, an and output, wherein first input end is coupled in second end of transistor seconds 562, in order to receive the second inhibit signal Sd2, second input is coupled in second end of the first transistor 560, in order to receive the first inhibit signal Sd1, the logic OR that output is carried out the first inhibit signal Sd1 and the second inhibit signal Sd2 in order to output is handled a secondary signal that is produced.The 3rd or door 585 comprise a first input end, one second input, an and output, wherein first input end is in order to receive logic input signal Si n, second input is coupled in second end of the first transistor 560, in order to receive the first inhibit signal Sd1, output is handled one the 3rd signal that is produced in order to the logic OR of the output actuating logic input signal Si n and the first inhibit signal Sd1.
Comprise a first input end, one second input, one the 3rd input, reach an output with door 588, wherein first input end is coupled in first or door 581 output, in order to receive first signal, second input is coupled in second or door 583 output, in order to receive secondary signal, the 3rd input is coupled in the 3rd or door 585 output, in order to receive the 3rd signal, output is carried out first signal, secondary signal, the logic that reaches the 3rd signal and the logic output signal Sout that processing produced in order to output.
Correspond to logic input signal Sin, voltage signal Vc, the first inhibit signal Sd1, the second inhibit signal Sd2, and the working timing figure of logic output signal Sout of delay circuit 500, be the working timing figure that is same as the coherent signal of the delay circuit 300 shown in the 4th figure, so repeat no more its operation principle.
Please refer to Fig. 6, Fig. 6 is the circuit diagram that shows according to the delay circuit 600 of third embodiment of the invention.Delay circuit 600 comprises a prime charge-discharge circuit 605, a signal processing circuit 650, reaches an output circuit 680.Signal processing circuit 650 comprises one first current source 670, a first transistor 660, one second current source 672, reaches a transistor seconds 662.Prime charge-discharge circuit 605 comprises one the 3rd current source 610, one first control switch 620, one the 4th current source 612, one second control switch 622, reaches an electric capacity 630.Output circuit 680 comprises an inverter (inverter) 681, one first NAND gate (NAND gate) 683,1 second NAND gate 685, one and door 687, and one or door 689.
The internal circuit configuration of prime charge-discharge circuit 605 and signal processing circuit 650 is same as the internal circuit configuration of prime charge-discharge circuit 305 and signal processing circuit 350, connects so repeat no more the circuit of its related elements.Inverter 681 comprises an input and an output, and wherein input is coupled in the first transistor 660, and in order to receive one first inhibit signal Sd1, the logical inversion that output is carried out the first inhibit signal Sd1 in order to output is handled one first signal that is produced.First NAND gate 683 comprises a first input end, one second input, reaches an output, and wherein first input end is coupled in the output of inverter 681, in order to receive first signal.Second NAND gate 685 comprises a first input end, one second input, reaches an output, wherein first input end is coupled in transistor seconds 662, in order to receive one second inhibit signal Sd2, second input is coupled in the output of first NAND gate 683, and output is coupled in second input of first NAND gate 683.First NAND gate 683 and second NAND gate 685 are combined as a RS flip-flop (RS Flip-Flop), in order to producing a secondary signal according to the second inhibit signal Sd2 and first signal, and from the output output secondary signal of second NAND gate 685.Comprise a first input end, one second input with door 687, reach an output, wherein first input end is coupled in transistor seconds 662, in order to receive the second inhibit signal Sd2, second input is coupled in the output of second NAND gate 685, in order to receive secondary signal, output is carried out the second inhibit signal Sd2 and the logic of secondary signal and one the 3rd signal that processing produced in order to output.Or door 689 comprises a first input end, one second input, reaches an output, wherein first input end is coupled in and door 687 output, in order to receive the 3rd signal, second input is coupled in the first transistor 660, in order to receive the first inhibit signal Sd1, the logic OR that output is carried out the first inhibit signal Sd1 and the 3rd signal in order to output is handled a logic output signal Sout who is produced.
Note that 680 of output circuits according to the first inhibit signal Sd1 and the second inhibit signal Sd2 to produce logic output signal Sout, do not need input logic input signal Si n to output circuit 680.Correspond to logic input signal Sin, voltage signal Vc, the first inhibit signal Sd1, the second inhibit signal Sd2, and the working timing figure of logic output signal Sout of delay circuit 600, still be same as the working timing figure of the coherent signal of delay circuit shown in Figure 4 300, so repeat no more its operation principle.
Please refer to Fig. 7, Fig. 7 is the circuit diagram that shows according to the delay circuit 700 of fourth embodiment of the invention.Delay circuit 700 comprises a prime charge-discharge circuit 705, a signal processing circuit 750, reaches an output circuit 780.Signal processing circuit 750 comprises one first current source 770, a first transistor 760, one second current source 772, reaches a transistor seconds 762.Prime charge-discharge circuit 705 comprises one the 3rd current source 710, one first control switch 720, one the 4th current source 712, one second control switch 722, reaches an electric capacity 730.Output circuit 780 comprises an inverter 781, one first NAND gate 783, one second NAND gate 785, one and door 787, one or door 789, and a plurality of buffers (buffer) 791-794.
The internal circuit configuration of prime charge-discharge circuit 705 and signal processing circuit 750 is same as the internal circuit configuration of prime charge-discharge circuit 505 and signal processing circuit 550, connects so repeat no more the circuit of its related elements.Buffer 791 be coupled in transistor seconds 762 and and an input of door 787 between, buffer 792-794 be coupled in the first transistor 760 and or a door input of 789 between, all the other internal circuit configurations of output circuit 780 are to be same as output circuit 680, so repeat no more.Correspond to logic input signal Sin, voltage signal Vc, the first inhibit signal Sd1, the second inhibit signal Sd2, and the working timing figure of logic output signal Sout of delay circuit 700, still be same as the working timing figure of the coherent signal of delay circuit shown in Figure 4 300, so repeat no more its operation principle.
From the above, according to delay circuit of the present invention be according to transistorized critical voltage, capacity cell capacitance, and the current value of current source with decision signal delay time, do not supplied voltage drift signal delay time to influence, so when the timing of supply voltage instability, still can produce stable logic output signal according to delay circuit of the present invention, make logic output signal can not be directed at the clock pulse jitter phenomenon because of the supply spread of voltage according to logic input signal.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. a delay circuit is characterized in that, comprises:
One prime charge-discharge circuit, it comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and this prime charge-discharge circuit is to produce this voltage signal in order to carry out the program of discharging and recharging according to this logic input signal;
One signal processing circuit, this output that is coupled in this prime charge-discharge circuit is to receive this voltage signal, and in order to produce one first inhibit signal and one second inhibit signal according to this voltage signal, this signal processing circuit comprises:
One first current source, it comprises one first end in order to receive one first supply voltage, reaches one second end;
One the first transistor, it comprises one first end in order to receive one second supply voltage, one second end is coupled in this second end of this first current source, and a control end is coupled in this output of this prime charge-discharge circuit, in order to receive this voltage signal, wherein this of this first transistor second end is in order to export this first inhibit signal;
One second current source, it comprises one first end in order to receive this second supply voltage, reaches one second end; And
One transistor seconds, it comprises one first end in order to receive this first supply voltage, one second end is coupled in this second end of this second current source, and a control end is coupled in this output of this prime charge-discharge circuit, in order to receive this voltage signal, wherein this of this transistor seconds second end is in order to export this second inhibit signal; And
One output circuit, it comprises this second end that a first input end is coupled in this first transistor, in order to receive this first inhibit signal, one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, one the 3rd input is in order to receiving this logic input signal, and an output is in order to export a logic output signal, wherein this output circuit according to this first inhibit signal, this second inhibit signal, and this logic input signal produce this logic output signal.
2. delay circuit as claimed in claim 1 is characterized in that, wherein this prime charge-discharge circuit comprises:
One the 3rd current source, it comprises one first end in order to receive this first supply voltage, reaches one second end;
One first control switch, it comprises this second end that one first end is coupled in the 3rd current source, and a control end reaches one second end in order to receive this logic input signal;
One the 4th current source, it comprises one first end in order to receive this second supply voltage, reaches one second end;
One second control switch, it comprises this second end that one first end is coupled in the 4th current source, and a control end reaches this second end that one second end is coupled in this first control switch in order to receive this logic input signal; And
One electric capacity, it comprises this second end that one first end is coupled in this first control switch, in order to export this voltage signal, reaches one second end in order to receive this second supply voltage.
3. delay circuit as claimed in claim 1 is characterized in that, wherein this output circuit comprises:
One first NOR gate, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, reaches an output;
One second NOR gate, it comprises this second end that a first input end is coupled in this transistor seconds, and in order to receive this second inhibit signal, one second input is coupled in this second end of this first transistor, in order to receive this first inhibit signal, reaches an output;
One the 3rd NOR gate, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this first transistor, in order to receive this first inhibit signal, reaches an output; And
One four nor gate, it comprises this output that a first input end is coupled in this first NOR gate, one second input is coupled in this output of this second NOR gate, and one the 3rd input is coupled in this output of the 3rd NOR gate, and an output is in order to export this logic output signal.
4. delay circuit as claimed in claim 1 is characterized in that, wherein this output circuit comprises:
One first or door, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this transistor seconds, in order to receiving this second inhibit signal, and an output;
One second or door, it comprises this second end that a first input end is coupled in this transistor seconds, and in order to receive this second inhibit signal, one second input is coupled in this second end of this first transistor, in order to receiving this first inhibit signal, and an output;
One the 3rd or door, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this first transistor, in order to receiving this first inhibit signal, and an output; And
One with the door, its comprise a first input end be coupled in this first or the door this output, one second input be coupled in this second or this output of door, one the 3rd input is coupled in the 3rd or this output of door, and an output is in order to export this logic output signal.
5. a delay circuit is characterized in that, comprises:
One prime charge-discharge circuit, it comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and this prime charge-discharge circuit is to produce this voltage signal in order to carry out the program of discharging and recharging according to this logic input signal;
One signal processing circuit, this output that is coupled in this prime charge-discharge circuit is to receive this voltage signal, and in order to produce one first inhibit signal and one second inhibit signal according to this voltage signal, this signal processing circuit comprises:
One first current source, it comprises one first end in order to receive one first supply voltage, reaches one second end;
One the first transistor, it comprises one first end in order to receive one second supply voltage, one second end is coupled in this second end of this first current source, and a control end is coupled in this output of this prime charge-discharge circuit, to receive this voltage signal, wherein this of this first transistor second end is in order to export this first inhibit signal;
One second current source, it comprises one first end in order to receive this second supply voltage, reaches one second end; And
One transistor seconds, it comprises one first end in order to receive this first supply voltage, one second end is coupled in this second end of this second current source, and a control end is coupled in this output of this prime charge-discharge circuit, to receive this voltage signal, wherein this of this transistor seconds second end is in order to export this second inhibit signal; And
One output circuit, it comprises this second end that a first input end is coupled in this first transistor, in order to receive this first inhibit signal, one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, reach an output in order to export a logic output signal, wherein this output circuit produces this logic output signal according to this first inhibit signal and this second inhibit signal.
6. delay circuit as claimed in claim 5 is characterized in that, wherein this prime charge-discharge circuit comprises:
One the 3rd current source, it comprises one first end in order to receive this first supply voltage, reaches one second end;
One first control switch, it comprises this second end that one first end is coupled in the 3rd current source, and a control end reaches one second end in order to receive this logic input signal;
One the 4th current source, it comprises one first end in order to receive this second supply voltage, reaches one second end;
One second control switch, it comprises this second end that one first end is coupled in the 4th current source, and a control end reaches this second end that one second end is coupled in this first control switch in order to receive this logic input signal; And
One electric capacity, it comprises this second end that one first end is coupled in this first control switch, in order to export this voltage signal, reaches one second end, in order to receive this second supply voltage.
7. delay circuit as claimed in claim 5 is characterized in that, wherein this output circuit comprises:
One inverter, it comprises this second end that an input is coupled in this first transistor receiving this first inhibit signal, and an output;
One first NAND gate, it comprises a first input end, one second input, reaches an output, and this first input end is coupled in this output of this inverter;
One second NAND gate, it comprises a first input end and is coupled in this second end of this transistor seconds to receive this second inhibit signal, one second input is coupled in this output of this first NAND gate, and an output is coupled in this second input of this first NAND gate;
One with door, it contains this second end that a first input end is coupled in this transistor seconds to receive this second inhibit signal, one second input is coupled in this output of this second NAND gate, and an output; And
One or door, it comprises a first input end and is coupled in this and this output of door, and this second end that one second input is coupled in this first transistor is receiving this first inhibit signal, and an output is in order to export this logic output signal.
8. delay circuit as claimed in claim 7 is characterized in that, wherein this output circuit comprises in addition:
At least one buffer, be coupled in this first transistor this second end and should or the door this second input between.
9. delay circuit as claimed in claim 7 is characterized in that, wherein this output circuit comprises in addition:
At least one buffer, be coupled in this transistor seconds this second end and should and this first input end of door between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710162170 CN101465631A (en) | 2007-12-21 | 2007-12-21 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710162170 CN101465631A (en) | 2007-12-21 | 2007-12-21 | Delay circuit |
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| Publication Number | Publication Date |
|---|---|
| CN101465631A true CN101465631A (en) | 2009-06-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710162170 Pending CN101465631A (en) | 2007-12-21 | 2007-12-21 | Delay circuit |
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| Country | Link |
|---|---|
| CN (1) | CN101465631A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832912A (en) * | 2012-08-03 | 2012-12-19 | 沃谱瑞科技(北京)有限责任公司 | Pulse signal unilateral edge time delay circuit |
| CN103368536A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Signal delay circuit based on MOS (metal oxide semiconductor) transistors |
| CN117544140A (en) * | 2024-01-09 | 2024-02-09 | 杭州米芯微电子有限公司 | Delay circuit and chip stable along with power supply voltage change |
-
2007
- 2007-12-21 CN CN 200710162170 patent/CN101465631A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832912A (en) * | 2012-08-03 | 2012-12-19 | 沃谱瑞科技(北京)有限责任公司 | Pulse signal unilateral edge time delay circuit |
| CN102832912B (en) * | 2012-08-03 | 2015-03-25 | 无锡中科沃谱瑞科技有限责任公司 | Pulse signal unilateral edge time delay circuit |
| CN103368536A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Signal delay circuit based on MOS (metal oxide semiconductor) transistors |
| CN103368536B (en) * | 2013-07-24 | 2016-01-13 | 苏州加古尔微电子科技有限公司 | Based on the signal delay circuit of metal-oxide-semiconductor |
| CN117544140A (en) * | 2024-01-09 | 2024-02-09 | 杭州米芯微电子有限公司 | Delay circuit and chip stable along with power supply voltage change |
| CN117544140B (en) * | 2024-01-09 | 2024-04-12 | 杭州米芯微电子有限公司 | Along with the change of power supply voltage Stable time delay circuit and chip |
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Open date: 20090624 |