CN105515549A - Single trigger circuit - Google Patents

Single trigger circuit Download PDF

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Publication number
CN105515549A
CN105515549A CN 201410506251 CN201410506251A CN105515549A CN 105515549 A CN105515549 A CN 105515549A CN 201410506251 CN201410506251 CN 201410506251 CN 201410506251 A CN201410506251 A CN 201410506251A CN 105515549 A CN105515549 A CN 105515549A
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clock
delay
signal
voltage
module
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CN 201410506251
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Chinese (zh)
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李秋平
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原景科技股份有限公司
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Abstract

The invention relates to a single trigger circuit comprising a constant voltage generating module, a clock skew module, and a logic operation module. The constant voltage generating module can operate according to a system voltage to generate a constant voltage, which is smaller than the system voltage, and is not changed along with the system voltage. The clock skew module comprises a delay circuit and a first phase inverter. The delay circuit is used to receive and delay a clock signal, and is used to generate a first delay clock signal. The first phase inverter is electrically connected with the delay circuit, can operate according to the constant voltage, and has a fixed switching point, and is used to receive the first delay clock signal to generate a second delay clock signal, and in addition, the period of the second delay clock signal is the same as the period of the clock signal, and the preset time is delayed. The logic calculation module can be used to receive the clock signal and the second delay clock signal for the logic calculation, and then a single trigger signal can be generated.

Description

单触发电路 One-shot circuit

技术领域 FIELD

[0001] 本发明涉及一种电路技术,且特别是涉及一种单触发电路。 [0001] The present invention relates to a circuit technique, and more particularly to a one-shot circuit.

背景技术 Background technique

[0002] 在实用电路上有许多的应用,是需要响应输入信号预设的状态改变(例如响应输入信号的电压上升)来产生短波宽的脉冲信号,以对其它电路进行驱动或触发。 [0002] There are many practical applications in the circuit, in response to a state change is required preset input signal (e.g., rising signal in response to the input voltage) to generate a short pulse width, to the driving circuits or other trigger. 特别对电子计算机电路来说,常需要响应时序信号的特定状况产生或改变,例如对应周期性的时序信号的波形上升缘,来产生具有相对短的波宽的单触发脉冲信号。 Especially for computer circuits, often need to respond to specific conditions or changing the timing signals generated, for example, a periodic timing signal corresponding to the waveform of the rising edge of the pulse width to generate a one-shot pulse signal having a relatively short. 在逻辑电路及电子计算机中,如何在即便单触发电路的供应电压变动的情形下,产生波宽不随之变动的精准单触发脉冲信号,是非常重要的。 In the logic circuit and computer, and how the supply voltage even in the case of one-shot circuit fluctuation generated wave width does not result in changes in the precise one-shot pulse signal, is very important.

[0003] 因此,如何设计一个新的单触发电路,以解决上述的问题,是业界亟待解决的问题。 [0003] Therefore, how to design a new one-shot circuit, in order to solve the above problems, the industry's problems to be solved.

发明内容 SUMMARY

[0004] 因此,本发明提供一种单触发(one-shot)电路,包含:定电压产生模块、时钟偏移模块以及逻辑运算模块。 [0004] Accordingly, the present invention provides a one-shot (one-shot) circuit, comprising: a constant voltage generating module, a clock module and a logical shift operation module. 定电压产生模块根据系统电压运作,以产生小于系统电压且不随系统电压改变的定电压。 Constant voltage generating system according to the voltage application module to generate a voltage not less than the system voltage change over a given system voltage. 时钟偏移模块包含:延迟电路以及至少一个第一反相器。 Clock offset module comprises: a first delay circuit and at least one inverter. 延迟电路用以接收并延迟时钟信号,以产生第一延迟时钟信号。 And a delay circuit for receiving the delayed clock signal to generate a first delayed clock signal. 第一反相器电性连接于延迟电路,根据固定电压运作而具有固定的转态点,用以接收第一延迟时钟信号并产生与时钟信号具有相同周期但延迟预设时间的第二延迟时钟信号。 A first inverter circuit electrically connected to the delay, according to a fixed operating voltage transient having a fixed point, for receiving the first delayed clock signal and generates a clock signal having the same period but a second predetermined time delay delayed clock signal. 逻辑运算模块接收时钟信号以及第二延迟时钟信号进行逻辑运算,以产生单触发信号。 Logical operation means for receiving a second clock signal and delayed clock signal by a logic operation to generate a one-shot signal.

[0005] 依据本发明一实施例,其中定电压产生模块包含:电流源、定压负载以及晶体管。 [0005] According to an embodiment of the present invention, wherein the constant voltage generating module comprises: a current source, the constant pressure and the load transistor. 电流源具有电流源输出端。 A current source having a current source output terminal. 定压负载电性连接于电流源输出端,以使电流源输出端的输出端电压固定于预设电平。 Constant pressure load is electrically connected to the output terminal of the current source, so that the output terminal of the current source output terminal is fixed to a predetermined voltage level. 晶体管的栅极电性连接于电流源输出端,以根据输出端电压导通并于晶体管的源/漏极产生固定电压。 The gate of the transistor is connected to a current source output terminal, the output terminal voltage according to the conduction of the transistor and the source / drain fixed voltage is generated.

[0006] 依据本发明另一实施例,其中定压负载包含多个串联的二极管。 [0006] According to another embodiment of the present invention, wherein the constant pressure load includes a plurality of diodes connected in series.

[0007] 依据本发明又一实施例,其中固定电压为二极管的总跨压与晶体管的临界电压之差。 [0007] According to yet another embodiment of the present invention, wherein the fixed voltage across the diode of the total pressure difference between the threshold voltage of the transistor.

[0008] 依据本发明再一实施例,其中延迟电路包含互相电性连接的第二反相器以及电容,其中第二反相器包含充电路径以及放电路径,根据时钟信号对电容进行充放电,以产生第一延迟时钟信号。 [0008] According to the present invention, another embodiment in which the delay circuit comprises a second inverter and a capacitor electrically connected to each other, wherein the second inverter comprises a charging path and a discharging path, charging and discharging the capacitor according to the clock signal, to generate a first delayed clock signal. 其中第二反相器的放电路径的放电速度高于充电路径的充电速度。 Wherein the discharge path of the second discharge rate is higher than the charging speed inverter charging path.

[0009] 依据本发明还具有的一实施例,其中时钟偏移模块还包含电平提升电路,以提升第二延迟时钟信号的电压电平,以使第二延迟时钟信号的电压电平与时钟信号相同。 [0009] According to the present invention has a further embodiment wherein the clock module further comprises an offset level-up circuit to boost the voltage level of the second delayed clock signal, so that the voltage level and the second clock signal is delayed clock the same signal.

[0010] 依据本发明再具有的一实施例,其中逻辑运算模块包含:第一逻辑运算模块以及第二逻辑运算模块。 [0010] According to the present invention has a further embodiment wherein the logic operation module comprises: a first logic operation and second logic operation module module. 第一逻辑运算模块接收时钟信号以及第二延迟时钟信号进行第一逻辑运算以产生每周期包含二脉冲的逻辑运算输出信号,其中逻辑运算输出信号在时钟信号以及第二延迟时钟信号为相反逻辑状态时对应二脉冲输出第一状态,并在时钟信号以及第二延迟时钟信号为相同逻辑状态时输出第二状态。 First logic operation module receives a second clock signal and delayed clock signal to generate a first logic operation logic operation output signal comprises two pulses per period, wherein the output signal of the logic operation to the opposite logic state of the clock signal and the second delayed clock signal when two pulse output corresponding to a first state and a second state when the same output logic state of the clock signal and the second delayed clock signal. 第二逻辑运算模块接收时钟信号以及逻辑运算输出信号进行第二逻辑运算以产生每周期包含二脉冲其中之一的单触发信号。 Second logic calculation block receives the clock signal and the output signal of a second logical operation to produce a single logic operation the trigger signal comprises a one-week period in which the pulse.

[0011] 依据本发明一实施例,其中第一逻辑运算模块包含异或门(Exclusive-OR gate)以及非门,第二逻辑运算模块包含或门。 [0011] According to an embodiment of the present invention, wherein the module comprises a first logic operation XOR gates (Exclusive-OR gate), and NAND gate, the second logic operation module comprises an OR gate.

[0012] 依据本发明另一实施例,其中第一逻辑运算模块包含异或门,第二逻辑运算模块包含与门。 [0012] According to another embodiment of the present invention, wherein the module comprises a first logic operation XOR gate, the second logic gate comprises a computing module.

[0013] 依据本发明又一实施例,其中单触发信号于每周期包含单一高态脉冲。 [0013] According to yet another embodiment of the present invention, which comprises a single-shot signal in the high state pulse per period.

[0014] 依据本发明再一实施例,其中单触发信号于每周期包含单一低态脉冲。 [0014] According to the present invention, another embodiment in which the signal comprises a single-shot pulse to the low state per period.

[0015] 应用本发明的优点在于借助单触发电路中的定电压产生模块产生固定电压,并供应至时钟偏移模块的第一反相器进行转态,以避免在延迟电路延迟时钟时造成过长的上升缘(rising edge)及下降缘(falling edge)时,容易受系统电压影响造成时序变动的缺点,因而可产生精准而不受系统电压影响的延迟时钟信号,并与时钟信号进行逻辑运算后产生精准的单触发信号,而轻易地达到上述的目的。 [0015] The advantages of the application of the present invention is that by means of the one-shot constant voltage generating module generates a fixed voltage circuit, and supplied to the first inverter clock offset module is transient, in order to avoid excessive delay in clock delay circuit long rising edge (rising edge) and a falling edge (falling edge), the system susceptible to voltage fluctuations impact disadvantage timing, thus accurately generating a voltage system without influence of the delayed clock signal, and performs a logic operation with a clock signal after the one-shot signal generating accurate, and easily to achieve the above objects.

附图说明 BRIEF DESCRIPTION

[0016] 图1为本发明一实施例中,一种单触发电路的电路图; [0016] FIG 1 one embodiment of the present invention, a circuit diagram of a one-shot circuit;

[0017] 图2为本发明一实施例中,延迟电路更详细的电路图; [0017] FIG. 2 embodiment, the delay circuit is a circuit diagram of a more detailed embodiment of the present invention;

[0018] 图3为本发明一实施例中,时钟信号、第一延迟时钟信号以及第二延迟时钟信号的波形图; [0018] FIG. 3 embodiment, the clock signal, the first delayed clock signal and a delayed clock signal waveform diagram of a second embodiment of the present invention;

[0019] 图4为本发明一实施例中,逻辑运算模块的方块图; [0019] In Figure 4, a block diagram of a logic operation module of the present embodiment of the invention;

[0020] 图5为本发明一实施例中,时钟信号、第二延迟时钟信号、逻辑运算输出信号以及单触发信号的波形图; [0020] FIG. 5 embodiment, the clock signal, the second delayed clock signal, the output signal of the logic operation and a single trigger a signal waveform diagram embodiment of the present invention;

[0021] 图6为本发明一实施例中,逻辑运算模块的方块图;以及 [0021] In Figure 6, a block diagram of a logic operation module of the present embodiment of the invention; and

[0022] 图7为本发明一实施例中,时钟信号、第二延迟时钟信号、逻辑运算输出信号以及单触发信号的波形图。 [0022] FIG. 7 embodiment, the clock signal, the second delayed clock signal, the output signal of the logic operation and a single trigger a signal waveform diagram embodiment of the present invention.

[0023] 附图符号说明 [0023] BRIEF DESCRIPTION OF REFERENCE NUMERALS

[0024] 1:单触发电路 10:定电压产生模块 [0024] 1: the one-shot circuit 10: constant voltage generating module

[0025] 100:电流源 101: 二极管 [0025] 100: current source 101: Diode

[0026] 102:定压负载 104:晶体管 [0026] 102: Constant pressure load 104: transistor

[0027] 12:时钟偏移模块 120:延迟电路 [0027] 12: 120 clock offset modules: a delay circuit

[0028] 121:第二反相器 122:第一反相器 [0028] 121: second inverter 122: first inverter

[0029] 123:电容 124:电平提升电路 [0029] 123: capacitor 124: level-up circuit

[0030] 14:逻辑运算模块 140:第一逻辑运算模块 [0030] 14: logic operation module 140: first logic operation module

[0031] 142:第二逻辑运算模块20:P型晶体管 [0031] 142: second logic calculation block 20: P-type transistor

[0032] 22:N型晶体管 40:异或门 [0032] 22: N-type transistor 40: XOR gate

[0033] 42:非门 44:或门 [0033] 42: NOT gate 44: gate or

[0034] 60:异或门 62:与门 [0034] 60: 62 XOR gates: AND gate

具体实施方式 detailed description

[0035] 请参照图1。 [0035] Referring to FIG. 图1为本发明一实施例中,一种单触发(one-shot)电路I的电路图。 In one embodiment of FIG. 1, a circuit diagram of a single-trigger (one-shot) circuit I of the present invention. 单触发电路I包含:定电压产生模块10、时钟偏移模块12以及逻辑运算模块14。 I-shot circuit comprises: a constant voltage generating module 10, the clock offset calculation module 12, and a logic module 14.

[0036] 定电压产生模块10中包含的各个元件是根据系统电压VDD运作。 [0036] The constant voltage generating modules of each element 10 is included in the system according to the operating voltage VDD. 在不同实施例中,系统电压VDD可为例如3.3伏特、5伏特或其它更高的电压值,但不限于此。 In various embodiments, the system voltage VDD may, for example, 3.3 volts, 5 volts or higher voltage value of the other, but is not limited thereto.

[0037] 定电压产生模块10包含:电流源100、定压负载102以及晶体管104。 [0037] The constant voltage generating module 10 comprises: a current source 100, 102 and a constant-pressure load transistor 104.

[0038] 电流源100具有电流源输出端O。 [0038] The current source 100 has a current source output terminal O. 定压负载102电性连接于电流源输出端0,以使电流源输出端O的输出端电压Vg固定于一个预设电平。 Constant pressure load 102 is electrically connected to the current source output terminal 0, so that the output terminal of the current source voltage Vg of the output terminal O is fixed to a preset level. 在一实施例中,定压负载102包含数个串联的二极管101。 In one embodiment, the constant-pressure load 102 comprising a plurality of diodes 101 in series. 因此,输出端电压Vg的电压电平相当于串联的二极管101的总跨压。 Therefore, the total voltage across the voltage level of the output terminal of the voltage Vg corresponding to the series diode 101. 举例来说,如果单一个二极管101在导通时的跨压为0.7伏特,且定压负载102如图1所示包含三个二极管101,则输出端电压Vg的电压电平将等于2.1伏特。 For example, if the voltage across a single diode 101 is turned on at 0.7 volts, and the constant pressure load includes three diodes 101 102 shown in FIG. 1, the output voltage level of the terminal voltage Vg is equal to 2.1 volts.

[0039] 需注意的是,上述的二极管101数目仅为一范例,在其它实施例中可视需求进行调整。 [0039] It should be noted that the number of diode 101 is one example of the above, the visual needs adjustments in other embodiments. 并且,定压负载102也可能以其它具有类似使电压固定机制的负载元件形成,不限于二极管。 Further, the constant-pressure load 102 may also be formed in other similar load element having the voltage fixing mechanism is not limited to a diode.

[0040] 在本实施例中,晶体管104为N型晶体管。 [0040] In the present embodiment, the transistor 104 is an N-type transistor. 晶体管104的栅极G电性连接于电流源100的电流源输出端0,并根据输出端电压Vg导通,并于晶体管104的源极S产生固定电压VDDL。 The gate G of the transistor 104 is connected to the current source output terminal 0 of the current source 100, and in accordance with the output terminal voltage Vg is turned on, and the source electrode S of the transistor 104 generates fixed voltage VDDL. 其中,固定电压VDDL小于系统电压VSS且不随系统电压VSS变动。 Wherein the fixed voltage VDDL variation not less than the system with the system voltage VSS voltage VSS.

[0041] 在一实施例中,固定电压VDDL的电压电平相当于输出端电压Vg的电压值和晶体管104的临界电压之差。 [0041] In one embodiment, the voltage level of VDDL fixed voltage difference between the threshold voltage corresponds to the voltage value of the output terminal voltage Vg of the transistor 104.

[0042] 以上述输出端电压Vg为三个二极管101的总跨压为例,若晶体管104的临界电压为0.5伏特,则固定电压VDDL的电压电平将为2.1-0.5 = 1.6伏特。 [0042] In the above-described output terminal voltage Vg of the total voltage across the three diodes 101 as an example, if the threshold voltage of the transistor 104 is 0.5 volts, the voltage level of the fixed voltage VDDL will be 2.1-0.5 = 1.6 volts.

[0043] 需注意的是,上述的N型晶体管仅为一范例,在其它实施例中,在适当调整后,也可以P型晶体管实现产生固定电压VDDL的目的,不为本实施例叙述所限。 [0043] It is noted that the above-described N-type transistor is merely an example, in other embodiments, after the appropriate adjustments may be P-type transistors to achieve the purpose of generating a fixed voltage VDDL, are not limited by the present embodiment is described in Example . 更进一步地,用以产生固定电压VDDL的电路也不限于图1所示的电路。 Still further circuit for generating a fixed voltage VDDL is not limited to the circuit shown in FIG. 换句话说,固定电压VDDL可由其它电路或方法来产生。 In other words, the fixed voltage VDDL or by other methods for generating circuits.

[0044] 时钟偏移模块12包含:延迟电路120以及第一反相器122。 [0044] The clock offset module 12 comprises: a first delay circuit 120 and inverter 122.

[0045] 请参照图2。 [0045] Referring to FIG. 图2为本发明一实施例中,延迟电路120更详细的电路图。 2 embodiment, the more detailed circuit diagram of the delay circuit 120 an embodiment of the present invention.

[0046] 延迟电路120接收并延迟时钟信号CLK,以产生第一延迟时钟信号CLKDl。 [0046] The delay circuit 120 receives and delays the clock signal CLK, the delayed clock signal to generate a first CLKDl. 在本实施例中,延迟电路120包含互相电性连接的第二反相器121以及电容123。 In the present embodiment, the delay circuit 120 comprises a second inverter each electrically connected to the capacitor 121 and 123.

[0047] 在本实施例中,第二反相器121包含由P型晶体管20形成的充电路径以及由N型晶体管22形成的放电路径。 [0047] In the present embodiment, the second inverter 121 includes a charge path formed by the P-type transistor 20 and the discharging path formed by the N-type transistor 22. 其中,P型晶体管20及N型晶体管22的漏极Dp及Dn互相电性连接,并进一步电性连接于电容123。 Wherein, P-type transistor 20 and an N-type transistor drain Dp and Dn are electrically connected to 22, and further electrically connected to the capacitor 123.

[0048] P型晶体管20及N型晶体管22的栅极Gp及Gn则接收时钟信号CLK。 [0048] P-type transistor and a gate electrode Gp 20 N-type transistor 22 and the Gn receives a clock signal CLK. 在本实施例中,P型晶体管20的源极Sp是电性连接于电流源100,以自电流源100接收电流II。 In the present embodiment, the source electrode of the P-type transistor Sp 20 is electrically connected to a current source 100 to receive the current from the current source 100 II.

[0049] 因此,当时钟信号CLK为低态时,P型晶体管20将导通并形成充电路径而借助电流Il对电容123充电。 [0049] Accordingly, when the clock signal CLK to low state, P-type transistor 20 will conduct and a charging path formed by the capacitor 123 charging current Il. 而N型晶体管22的源极Sn则电性连接于接地端GND。 The source of the N-type transistor 22 Sn is electrically connected to the ground terminal GND. 因此,当时钟信号CLK为高态时,N型晶体管22将导通并形成放电路径而借助流经N型晶体管22的电流12对电容123放电。 Accordingly, when the clock signal CLK to a high state, the N-type transistor 22 is turned on and the discharge path formed by current I2 flowing through the N-type transistor discharging the capacitor 12322.

[0050] 因此,在经由第二反相器121的充电路径及放电路径对电容123的充放电后,将产生第一延迟时钟信号CLKDl。 [0050] Accordingly, after charging and discharging the capacitor 123 through the charging path and a discharging path of the second inverter 121 will produce a first delayed clock signal CLKDl.

[0051] 第一反相器122互相电性串联,并电性连接于延迟电路120,以根据固定电压VDDL运作。 [0051] The first inverter 122 is electrically connected in series to each other, and electrically connected to a delay circuit 120, to operate according to a fixed voltage VDDL. 第一反相器122将接收延迟电路120产生的第一延迟时钟信号CLKDl,并产生第二延迟时钟信号CLKD2。 A first inverter delay circuit 122 receives the first delayed clock signal 120 generated CLKDl, and generating a second delayed clock signal CLKD2. 第一反相器122的运作以及第二延迟时钟信号CLKD2的产生将于以下的段落进行进一步的讨论。 Operating a first inverter 122 and the second delayed clock signal generating CLKD2 following paragraphs will be discussed further.

[0052] 请参照图3。 [0052] Referring to FIG. 图3为本发明一实施例中,时钟信号CLK、第一延迟时钟信号CLKDl以及第二延迟时钟信号CLKD2的波形图。 3 embodiment, the clock signal CLK, the delayed clock signal CLKDl first and second delayed clock signal waveform diagram CLKD2 to an embodiment of the present invention.

[0053] 在一实施例中,延迟电路120是接收电压电平范围介于接地电位及系统电压VDD的时钟信号CLK。 [0053] In one embodiment, the delay circuit 120 is a voltage level range between the reception clock signal CLK and a system ground potential voltage VDD. 延迟电路120可借助适当的设计,使第二反相器121中,放电路径对电容123的放电速度高于充电路径对电容123的充电速度。 The delay circuit 120 may be by means of appropriate design, so that the second inverter 121, a discharge path for discharging the capacitor 123 is higher than the speed of the charging rate of the capacitor charging path 123. 因此,每周期的波形中,第一延迟时钟信号CLKDl的上升缘的斜率将高于下降缘的斜率。 Accordingly, the waveform of the week, the slope of the first rising edge of the delayed clock signal CLKDl will be higher than the slope of the falling edge.

[0054] 由于第一反相器122依照固定不变的固定电压VDDL运作,因此其转态点也可维持稳定的值,而不会受系统电压VDD的变化而改变。 [0054] Since the first inverter 122 VDDL operating in accordance with a fixed voltage fixed, so the transient point values ​​can be maintained stable without change by the change of the system voltage VDD. 在一实施例中,转态点的电压电平为m)L/20 In one embodiment, the voltage level of the points is transited m) L / 20

[0055] 并且,第一反相器122可借助类似图2中第二反相器121的结构实现。 [0055] Further, the first inverter 122 may be implemented by means of the structure 121 in the second inverter 2 is similar to FIG. 然而,第一反相器122的充放电速度将相当快速,以使具有相当快的转态速度,而使第二延迟时钟信号CLKD2的上升缘及下降缘实质上均为垂直,即与原始的时钟信号CLK相同。 However, the charge and discharge rate a first inverter 122 will be quite fast, so as to have a relatively fast transition speed, the second delayed clock signal rising edge and a falling edge of CLKD2 are substantially perpendicular, i.e., the original the same clock signal CLK. 需注意的是,上述「实质上垂直」的叙述,指上升缘及下降缘并非一定为90度,而可具有一可容许范围内的误差,例如90度的-5%及+5%的范围间。 It is noted that, the above description "substantially perpendicular", referring to the rising edge and a falling edge is not necessarily 90 °, but may have an error within an allowable range, for example, a range of -5% and 90 + 5% between.

[0056] 因此,第二延迟时钟信号CLKD2的周期将相当于时钟信号CLK的周期,但在时序上将相对时钟信号CLK延迟一段预设时间Tl。 [0056] Thus, the second delayed clock signal CLKD2 cycle period corresponding to the clock signal CLK, but the relative timing on the clock signal CLK for a predetermined delay time Tl. 更进一步地,在本实施例中,第二延迟时钟信号CLKD2的电压电平相当于固定电压VDDL。 Still further, in the present embodiment, the second delayed clock signal CLKD2 voltage level corresponding to the fixed voltage VDDL. 实际所延迟的预设时间Tl,将取决于第二反相器121的充放电能力,以及第一反相器122的数目。 Actual delay preset time Tl, will depend on the number of charge-discharge capacity of the second inverter 121, and a first inverter 122. 在图3中,为便于说明,所绘示的第二延迟时钟信号CLKD2绘出受到第二反相器121的充放电能力影响造成的延迟,而忽略第一反相器122的影响。 In Figure 3, for convenience of explanation, depicted CLKD2 second delayed clock signal is depicted by the charging and discharging capacity of the second inverter 121, the influence caused by the delay and ignore the influence of the first inverter 122.

[0057] 需注意的是,图1中所绘示的第一反相器122数目仅为一范例,在其它实施例中可视需求进行调整。 [0057] It should be noted that the number of the first inverter 122 depicted in FIG. 1 is one example, adjustments in other embodiments the visual needs.

[0058] 在一实施例中,图1中的时钟偏移模块12可进一步包含电平提升电路124,以提升第二延迟时钟信号CLKD2的电压电平,以产生第二延迟时钟信号CLKD2'。 [0058] In one embodiment, a clock skew in FIG module 12 may further include a level-up circuit 124, a second delayed clock signal to enhance voltage level CLKD2 to generate a second delayed clock signal CLKD2 '. 其中,第二延迟时钟信号CLKD2'的电压电平被提升而与时钟信号CLK相同。 Wherein the second delayed clock signal CLKD2 'voltage level is raised and the same clock signal CLK. 在不同实施例中,电平提升电路124可以不同的电路设计实现,任何本领域技术人员在不脱离本发明内容的精神和范围内,可做各种的更动与润饰。 In various embodiments, the level-up circuit 124 can be implemented in different circuit design, anyone skilled in the art without departing from the spirit and scope of the spirit of the invention, that various alterations and modifications.

[0059] 逻辑运算模块14将接收时钟信号CLK以及第二延迟时钟信号CLKD2'进行逻辑运算,以产生单触发信号CLKS。 [0059] The logic operation module 14 receives the clock signal CLK delayed clock signal and a second CLKD2 'conducts logic operation to generate a one-shot signal CLKS.

[0060] 请同时参照图4及图5。 [0060] Referring to FIGS. 4 and 5. 图4为本发明一实施例中,逻辑运算模块14的方块图。 Figure 4 embodiment, the logic operation module 14 is a block diagram of an embodiment of the invention. 图5为本发明一实施例中,时钟信号CLK、第二延迟时钟信号CLKD2'、逻辑运算输出信号CLKLO以及单触发信号CLKS的波形图。 5 embodiment, a clock signal CLK embodiment of the present invention, the second delayed clock signal CLKD2 ', the output signal of the logic operation waveform diagram CLKLO and single trigger signal CLKS.

[0061] 逻辑运算模块14包含:第一逻辑运算模块140以及第二逻辑运算模块142。 [0061] The logic operation module 14 comprises: a first logic operation and second logic operation module 140, module 142. 其中,在本实施例中,第一逻辑运算模块140包含:异或门(Exclusive-ORgate) 40以及非门42。 In the present embodiment, the first logic operation module 140 comprises: an exclusive-OR gates (Exclusive-ORgate) 40 and a NAND gate 42. 异或门40接收时钟信号CLK以及第二延迟时钟信号CLKD2'进行逻辑运算,并再经由非门42产生逻辑运算输出信号CLKLO。 Exclusive OR gate 40 CLK receives the clock signal and the second delayed clock signal CLKD2 'logical operation, logic operation and then generate an output signal of the NAND gate 42 via CLKLO.

[0062] 异或门40在时钟信号CLK以及第二延迟时钟信号CLKD2'为相反逻辑状态时输出高态。 [0062] XOR gate 40 'output a logic high state to the opposite state when the clock signal CLK delayed clock signal and a second CLKD2. 相反地,异或门40在时钟信号CLK以及第二延迟时钟信号CLKD2'为相同逻辑状态时输出低态。 Conversely, the exclusive OR gate 40 'output a logic low state is the same state when the clock signal CLK delayed clock signal and a second CLKD2. 因此,在经过非门42后,第一逻辑运算模块140将如图5所示产生包含两个低态脉冲Pl及P2的逻辑运算输出信号CLKLO。 Therefore, a logic operation output signal comprises two low state pulses Pl and P2 is CLKLO after a NAND gate 42, a first logic operation module 140 as shown in FIG.

[0063] 第二逻辑运算模块142在本实施例中包含或门44,以进一步根据时钟信号CLK以及逻辑运算输出信号CLKLO进行逻辑运算,以产生单触发信号CLKS。 [0063] The second module 142 comprises a logic operation in the present embodiment, the OR gate 44, to further a logical operation clock signal CLK and the output signal of a logic operation CLKLO, to generate a one-shot signal CLKS.

[0064] 或门44将仅在时钟信号CLK以及逻辑运算输出信号CLKLO均为低态时输出低态。 [0064] OR gate 44 will output a low state only when the clock signal CLK and the output signal of a logic operation CLKLO are low. 因此,单触发信号CLKS将如图5所示,仅包含单一个低态脉冲P2。 Thus, one-shot signal CLKS to 5, comprising only a single active low pulse P2.

[0065] 因此,单触发电路I中的定电压产生模块10可产生固定电压VDDL,并供应至时钟偏移模块12的第一反相器122进行转态,以避免在时钟偏移模块12的延迟电路120延迟时钟时造成过长的上升缘及下降缘时,容易受系统电压VDD影响造成时序变动的缺点,因而可产生精准而不受系统电压VDD影响的延迟时钟信号,并与时钟信号进行逻辑运算后产生精准的单触发信号。 [0065] Accordingly, the one-shot circuit I in the constant voltage generation module 10 may generate a fixed voltage VDDL, and supplied to a first clock offset module 122 of the inverter 12 is transited to avoid clock skew module 12 the delay circuit 120 is a delay caused by clock rising edge and a falling edge of the long, the system voltage VDD changes affect the timing disadvantages of vulnerable, and thus can be produced without precise impact of the system voltage VDD delayed clock signal, and the clock signal logic operation to generate accurate one-shot signal.

[0066] 请同时参照图6及图7。 [0066] Please refer to FIGS. 6 and 7. 图6为本发明一实施例中,逻辑运算模块14的方块图。 6 embodiment, the logic operation module 14 is a block diagram of an embodiment of the invention. 图7为本发明一实施例中,时钟信号CLK、第二延迟时钟信号CLKD2'、逻辑运算输出信号CLKLO以及单触发信号CLKS的波形图。 7 embodiment, a clock signal CLK embodiment of the present invention, the second delayed clock signal CLKD2 ', the output signal of the logic operation waveform diagram CLKLO and single trigger signal CLKS.

[0067] 类似图5所绘示的逻辑运算模块14,图6绘示的逻辑运算模块14包含:第一逻辑运算模块140以及第二逻辑运算模块142。 [0067] The logical operations depicted in block 5 shown in FIG. 14 is similar to FIG. 6 shows the logic operation module 14 comprises: a first logic operation and second logic operation module 140, module 142.

[0068] 在本实施例中,第一逻辑运算模块140包含异或门60。 [0068] In the present embodiment, the first logic operation module 140 comprises an exclusive OR gate 60. 异或门60接收时钟信号CLK以及第二延迟时钟信号CLKD2'进行逻辑运算,以产生逻辑运算输出信号CLKL0。 XOR gate 60 receives the clock signal CLK delayed clock signal and a second CLKD2 'performs a logic operation, a logic operation to generate an output signal CLKL0.

[0069] 异或门60在时钟信号CLK以及第二延迟时钟信号CLKD2'为相反逻辑状态时输出高态,并在时钟信号CLK以及第二延迟时钟信号CLKD2'为相同逻辑状态时输出低态。 [0069] XOR gate 60 'output a high logic state is the opposite state, and the clock signal CLK delayed clock signal and a second CLKD2' the clock signal CLK and outputs a second delayed clock signal CLKD2 low state when the same logic state. 因此,第一逻辑运算模块140如图7所示产生包含两个高态脉冲P3及P4的逻辑运算输出信号CLKLOο Thus, the first logic operation module 140 shown in FIG logic operation to generate an output signal comprising a high state CLKLOο two pulses P3 and P4, 7

[0070] 第二逻辑运算模块142在本实施例中包含与门62,以进一步根据时钟信号CLK以及逻辑运算输出信号CLKLO进行逻辑运算,以产生单触发信号CLKS。 [0070] The second module 142 comprises a logic operation in the present embodiment, the AND gate 62, to further a logical operation in accordance with the clock signal CLK and the output signal of the logic operation CLKLO, to generate a one-shot signal CLKS.

[0071] 与门62将仅在时钟信号CLK以及逻辑运算输出信号CLKLO均为高态时输出高态。 [0071] The AND gate 62 outputs a high state are high state only when the clock signal CLK and a logical operation output signal CLKLO. 因此,单触发信号CLKS将如图7所示,仅包含单一个高态脉冲P3。 Thus, the one-shot signal CLKS shown in FIG. 7, only containing a single high state pulse P3.

[0072] 因此,本实施例中的逻辑运算模块14可选择性地以图6绘示的架构实现。 [0072] Accordingly, in the present embodiment a logical arithmetic module 14 may alternatively be implemented in the architecture shown in FIG. 6 is a schematic.

[0073] 虽然本发明内容已以实施方式揭示如上,然而其并非用以限定本发明内容,任何本领域技术人员在不脱离本发明内容的精神和范围内,可做各种的更动与润饰,因此本发明内容的保护范围是以本发明的权利要求为准。 [0073] Although the present invention has been disclosed in the above embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the spirit and scope of the spirit of the invention, that various modifications and variations , Therefore, the scope of the present disclosure is claimed in the invention claims and their equivalents.

Claims (12)

  1. 1.一种单触发电路,包含: 一定电压产生模块,根据一系统电压运作,以产生小于该系统电压且不随该系统电压改变的一定电压; 一时钟偏移模块,包含: 一延迟电路,用以接收并延迟一时钟信号,以产生一第一延迟时钟信号;以及至少一个第一反相器,电性连接于该延迟电路,根据该固定电压运作而具有一固定的转态点,以接收该第一延迟时钟信号并产生与该时钟信号具有相同周期但延迟一预设时间的一第二延迟时钟信号;以及一逻辑运算模块,接收该时钟信号以及该第二延迟时钟信号进行逻辑运算,以产生一单触发信号。 A one-shot circuit, comprising: a constant voltage generating module, the system voltage according to an operation to produce not less than the system voltage with the voltage change of the system voltage constant; a clock offset module, comprising: a delay circuit for and to receive a delayed clock signal to generate a first delayed clock signal; and at least a first inverter electrically connected to the delay circuit, based on the operation of the fixed voltage transient having a fixed point, to receive the first delayed clock signal having the same period and generates the clock signal but delayed a second clock signal delayed by a predetermined time; and a logic operation module for receiving the clock signal and the second delayed clock signal to a logic operation, to generate a single trigger signal.
  2. 2.如权利要求1所述的单触发电路,其中该定电压产生模块包含: 一电流源,具有一电流源输出端; 一定压负载,电性连接于该电流源输出端,以使该电流源输出端的一输出端电压固定于一预设电平;以及一晶体管,该晶体管的一栅极电性连接于该电流源输出端,以根据该输出端电压导通,并于该晶体管的一源/漏极产生该固定电压。 2. The one-shot circuit according to claim 1, wherein the constant voltage generating module comprises: a current source having a current source output terminal; constant-pressure load, electrically connected to the output terminal of the current source, so that the current an output terminal of the source voltage of the output terminal is fixed to a predetermined level; and a transistor, a gate of the transistor is electrically connected to the current source output terminal, the output terminal voltage according to the conduction, and the transistor in a source / drain electrodes to generate the fixed voltage.
  3. 3.如权利要求2所述的单触发电路,其中该定压负载包含多个串联的二极管。 One-shot circuit according to claim 2, wherein the constant pressure load includes a plurality of diodes connected in series.
  4. 4.如权利要求3所述的单触发电路,其中该固定电压为这些二极管的一总跨压与该晶体管的一临界电压之差。 4. The one-shot circuit according to claim 3, wherein the fixed voltage is a threshold voltage of a difference between the total voltage across the diode and the transistor.
  5. 5.如权利要求1所述的单触发电路,其中该延迟电路包含互相电性连接的一第二反相器以及一电容,其中该第二反相器包含一充电路径以及一放电路径,根据该时钟信号对该电容进行充放电,以产生该第一延迟时钟信号。 5. The one-shot circuit according to claim 1, wherein the delay circuit comprises a second inverter electrically connected to each other and a capacitor, wherein the second inverter includes a charging path and a discharging path, in accordance with the clock signal to the capacitor charging and discharging, to generate the first delayed clock signal.
  6. 6.如权利要求5所述的单触发电路,其中该第二反相器的该放电路径的一放电速度高于该充电路径的一充电速度。 6. The one-shot circuit according to claim 5, wherein a discharge speed of the discharge path of the second inverter is higher than a charging speed of the charging path.
  7. 7.如权利要求1所述的单触发电路,其中该时钟偏移模块还包含一电平提升电路,以提升该第二延迟时钟信号的电压电平,以使该第二延迟时钟信号的电压电平与该时钟信号相同。 7. The one-shot circuit according to claim 1, wherein the clock module further comprises an offset level-up circuit to boost the voltage level of the second delayed clock signal, so that the voltage of the second delayed clock signal the same level of the clock signal.
  8. 8.如权利要求1所述的单触发电路,其中该逻辑运算模块包含: 一第一逻辑运算模块,接收该时钟信号以及该第二延迟时钟信号进行一第一逻辑运算以产生每周期包含二脉冲的一逻辑运算输出信号,其中该逻辑运算输出信号在该时钟信号以及该第二延迟时钟信号为相反逻辑状态时对应该二脉冲输出一第一状态,并在该时钟信号以及该第二延迟时钟信号为相同逻辑状态时输出一第二状态;以及一第二逻辑运算模块,接收该时钟信号以及该逻辑运算输出信号进行一第二逻辑运算,以产生每周期包含该二脉冲其中之一的该单触发信号。 Includes two first logic operation a module for receiving the clock signal and the second delayed clock signal to generate a first logic operation per cycle: 8. The one-shot circuit according to claim 1, wherein the logic operation module comprises a logic operation signal output pulse wherein the output signal of the logic operation clock signal and the second delayed clock signal to the opposite logic state when a first pulse output to be two state, and the clock signal and the second delay when the clock signal is output as the same logic state to a second state; and a second logic operation module for receiving the clock signal and the output signal of the logic operation performed a second logical operation, to generate one of the two pulses per period which comprises the one-shot signal.
  9. 9.如权利要求8所述的单触发电路,其中该第一逻辑运算模块包含一异或门以及一非门,该第二逻辑运算模块包含一或门。 9. The single-triggering circuit of claim 8, wherein the first computing module comprises a logical exclusive OR gate and a NAND gate, the second logic operation module comprises an OR gate.
  10. 10.如权利要求8所述的单触发电路,其中该第一逻辑运算模块包含一异或门,该第二逻辑运算模块包含一与门。 10. The single shot circuit of claim 8, wherein the first computing module comprises a logical XOR gate, the second logic block comprises an AND gate operation.
  11. 11.如权利要求1所述的单触发电路,其中该单触发信号于每周期包含单一高态脉冲。 11. The one-shot circuit according to claim 1, wherein the signal comprises a single one-shot pulse to the high state per period.
  12. 12.如权利要求1所述的单触发电路,其中该单触发信号于每周期包含单一低态脉冲。 12. The one-shot circuit according to claim 1, wherein the signal comprises a single one-shot pulse to the low state per period.
CN 201410506251 2014-09-26 2014-09-26 Single trigger circuit CN105515549A (en)

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CN102364851A (en) * 2011-10-24 2012-02-29 无锡芯朋微电子有限公司 Circuit converting high-voltage power supply into low-voltage power supply for enabling zero switching current of chip

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