CN100377258C - Shift register circuit - Google Patents
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- CN100377258C CN100377258C CNB031412491A CN03141249A CN100377258C CN 100377258 C CN100377258 C CN 100377258C CN B031412491 A CNB031412491 A CN B031412491A CN 03141249 A CN03141249 A CN 03141249A CN 100377258 C CN100377258 C CN 100377258C
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Abstract
The present invention relates to a shift register circuit which has a plurality of cascade shift cache units. The shift register circuit comprises the following assemblies: a first transistor, a reversed-phase device, a second transistor, a third transistor and a fourth transistor, wherein the grid electrode of the first transistor is coupled to a reversed-phase clock signal, and the first source/drain electrode is connected to the output terminal of a previous cascade shift cache unit; the reversed-phase device has a first input terminal and a first output terminal, and the first input terminal is connected to the first source/drain electrode of the first transistor; the grid electrode of the second transistor is connected to the second source/drain electrode of the first transistor, the first source/drain electrode of the second transistor is coupled to the clock signal, and the second source/drain electrode of the second transistor is connected to the output terminal; the grid electrode of the third transistor is connected to the first output terminal of the reversed-phase device, the first source/drain electrode of the third transistor is connected to the output terminal, and the second source/drain electrode of the third transistor is connected to a first power source; the grid electrode of the fourth transistor is connected to the output terminal of a rear cascade shift cache unit, the first source/drain electrode of the fourth transistor is connected to the second source/drain electrode of the second transistor, and the second source/drain electrode of the fourth transistor is connected to the first power source.
Description
Technical field
The present invention is relevant for a kind of shift register circuit, particularly relevant for a kind of shift register circuit that is applied to the liquid crystal announcer.
Background technology
Fig. 1 represents the patent number US4 that Ullrich proposed in 1978,084,106 disclosed traditional shift register circuit (shift register) circuit structures, in Fig. 1, only represent the single shift buffer unit, the shift cache unit of a plurality of serial connections can constitute complete shift register circuit, as shown in Figure 1, inversion clock signal XCK is connected to the gate terminal of 3 nmos pass transistor Q1-Q3, and each nmos pass transistor all has an internal capacitance Cgd.
The formula of dynamic power dissipation (dynamic powerloss) is: p=fcv
2, wherein, p represents dynamic power dissipation, and f represents the frequency of inversion clock signal XCK, and c represents electric capacity, and v represents inversion clock signal XCK by the voltage difference of electronegative potential to noble potential; By following formula as can be known, when electric capacity was big more, power attenuation was also just big more.
Summary of the invention
In view of this, in order to solve described problem, fundamental purpose of the present invention is to provide a kind of shift register circuit, reduces the quantity that transistorized grid capacitance is connected to clock signal, to reduce the loss of dynamic power.
For realizing described purpose, the present invention proposes a kind of shift register circuit, shift cache unit with a plurality of serial connection levels, described shift cache unit, comprise following assembly: the first transistor, its grid couples the inversion clock signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level; Anti-phase device has the first input end and first output terminal, and first input end is connected to first source/drain electrode of the first transistor; Transistor seconds, its grid are connected to second source/drain electrode of the first transistor, and its first source/drain electrode couples clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; The 3rd transistor, its grid are connected to first output terminal of anti-phase device, and its first source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Its second source/drain electrode is connected to first power supply; And the 4th transistor, its grid is connected to the output terminal of the shift cache unit of back one serial connection level, and its first source/drain electrode is connected to second source/drain electrode of transistor seconds, and its second source/drain electrode is connected to first power supply.
In addition, the present invention proposes a kind of shift register circuit, has the shift cache unit of a plurality of serial connection levels, described shift cache unit, comprise: the first transistor, its grid couples the inversion clock signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level; Transistor seconds, its grid are connected to second source/drain electrode of the first transistor, and its first source/drain electrode couples clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Anti-phase device has the first input end and first output terminal, and first input end is connected to the output terminal of shift cache unit at the corresponding levels; The 3rd transistor, its grid are connected to first output terminal of anti-phase device, and its first source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Its second source/drain electrode is connected to first power supply; And the 4th transistor, its grid is connected to the output terminal of the shift cache unit of back one serial connection level, and its first source/drain electrode is connected to second source/drain electrode of transistor seconds, and its second source/drain electrode is connected to first power supply.
In addition, the present invention proposes a kind of shift register circuit, has the shift cache unit of a plurality of serial connection levels, and described shift cache unit comprises following assembly: the first transistor, and its grid couples the inversion clock signal, and its first source/drain electrode is connected to trigger end; Anti-phase device has first input and output side, and first input end is connected to first source/drain electrode of the first transistor; Transistor seconds, its grid are connected to second source/drain electrode of the first transistor, and its first source/drain electrode couples clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; The 3rd transistor, its grid are connected to first output terminal of anti-phase device, and its first source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Its second source/drain electrode is connected to first power supply; The 4th transistor, its grid connects the end of resetting, and its first source/drain electrode is connected to second source/drain electrode of transistor seconds, and its second source/drain electrode is connected to first power supply; And direction-control apparatus, in order to the order direction of control shift register circuit output.
Described direction-control apparatus, comprise: the 5th transistor, its grid receive to left signal, export left in order to the control shift register circuit, its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to the end of resetting; The 6th transistor, its grid receive to left signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to trigger end; The 7th transistor, its grid receive to right signal, export to the right in order to the control shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to trigger end; And the 8th transistor, its grid receives to right signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to replacement and holds.
In addition, the present invention proposes a kind of shift register circuit, has the shift cache unit of a plurality of serial connection levels, and described shift cache unit comprises: the first transistor, and its grid couples the inversion clock signal, and its first source/drain electrode is connected to trigger end; Transistor seconds, its grid are connected to second source/drain electrode of the first transistor, and its first source/drain electrode couples clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Anti-phase device has first input and the output terminal, and first input end is connected to the output terminal of shift cache unit at the corresponding levels; The 3rd transistor, its grid are connected to first output terminal of anti-phase device, and its first source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels; Its second source/drain electrode is connected to first power supply; The 4th transistor, its grid are connected to the end of resetting, and its first source/drain electrode is connected to second source/drain electrode of transistor seconds, and its second source/drain electrode is connected to first power supply; And direction-control apparatus, in order to the order direction of control shift register circuit output.
Described direction-control apparatus, comprise: the 5th transistor, its grid receive to left signal, export left in order to the control shift register circuit, its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to the end of resetting; The 6th transistor, its grid receive to left signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to trigger end; The 7th transistor, its grid receive to right signal, export to the right in order to the control shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to trigger end; And the 8th transistor, its grid receives to right signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to replacement and holds.
For described and other purpose of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 represents the circuit structure of traditional shift register circuit.
Fig. 2 represents the circuit structure diagram of the described shift cache unit of first embodiment of the invention.
Fig. 3 represents the sequential chart according to the described shift register circuit of the embodiment of the invention.
Fig. 4 represents the circuit structure diagram of the described shift cache unit of second embodiment of the invention.
Fig. 5 represents the circuit structure diagram of the described shift cache unit of third embodiment of the invention.
Fig. 6 represents the circuit structure diagram of the described shift cache unit of fourth embodiment of the invention.
Fig. 7 represents the circuit structure diagram of the described shift cache unit of fifth embodiment of the invention.
Fig. 8 represents the circuit structure diagram of the described shift cache unit of sixth embodiment of the invention.
Fig. 9 represents the circuit structure diagram of the described shift cache unit of seventh embodiment of the invention.
Figure 10 represents that the present invention is applicable to the directional control circuit structural drawing of shift cache unit.
Symbol description
Q1-Q10: transistor; C: capacitor;
10: directional control circuit; 20: anti-phase device; 21: phase inverter;
A-C: node; CK: clock signal; XCK: inversion clock signal;
VSS: first power supply; VDD: second source
Embodiment
Shift register circuit of the present invention is made of the shift cache unit of a plurality of serial connections, below describes the inner structure of each shift cache unit; In addition, shift cache unit disclosed in this invention can be made up of nmos tft or PMOS thin film transistor (TFT), if be made up of nmos tft, then the first power supply VSS is a low voltage level, and second source VDD is a high-voltage level; If be made up of the PMOS thin film transistor (TFT), then the first power supply VSS is a high-voltage level, and second source VDD is a low voltage level; All embodiment of the present invention form by nmos tft.
Fig. 2 represents the circuit structure diagram of the described shift cache unit of first embodiment of the invention.Only representing single level shift cache unit at this, is example with N level shift cache unit, and the shift cache unit of a plurality of serial connections can constitute complete shift register circuit.The shift cache unit of first embodiment of the invention comprises: a first transistor Q1, its grid couple inversion clock signal XCK, and its first source/drain electrode is connected to output terminal (N-1) OUT of the shift cache unit of last serial connection level;
One anti-phase device 20, its low-voltage source is VSS, and high voltage source is XCK, has a first input end and one first output terminal, and first input end is connected to first source/drain electrode of the first transistor Q1; One transistor seconds Q2, its grid are connected to second source/drain electrode of the first transistor Q1, and its first source/drain electrode couples clock signal C K, and its second source/drain electrode is connected to an output terminal (N) OUT; One the 3rd transistor Q3, its grid are connected to first output terminal of anti-phase device 20, and its first source/drain electrode is connected to output terminal (N) OUT; Its second source/drain electrode is connected to the first power supply VSS;
And one the 4th transistor Q4, its grid are connected to output terminal (N+1) OUT of the shift cache unit of back one serial connection level, and its first source/drain electrode is connected to second source/drain electrode of transistor seconds Q2, and its second source/drain electrode is connected to the first power supply VSS.In all embodiment of the present invention, also comprise: a capacitor C (being represented by dotted lines) makes that the output terminal OUT of N level is more stable;
When the grid of the first transistor Q1 receives the high level signal of inversion clock signal XCK, the first transistor Q1 conducting, the high level signal that makes last output terminal (N-1) OUT that is connected in series the shift cache unit of level (N-1) level be exported passes through the first transistor Q1 and conducting transistor seconds Q2, so output terminal (N) OUT clock signal CK is to the next stage shift cache unit.
In addition, because output (N+1) OUT of next stage (N+1) shift cache unit feeds back to the grid of the 4th transistor Q4, therefore, when output terminal (N+1) OUT of next stage (N+1) shift cache unit is high level signal, the 4th transistor with conducting so that output terminal (N) OUT is a low level signal.
And during output terminal (N-1) the OUT output low level signal of the shift cache unit of current serial connection level (N-1) level, make by anti-phase device 20 the 3rd transistor Q3 conducting to make output terminal (N) OUT when not exporting, can remain on low level.
Fig. 3 represents the sequential chart according to the described shift register circuit of the embodiment of the invention.With Fig. 2 is example, and (N) OUT represents the output terminal of the shift cache unit of N level; (N-1) output terminal of the shift cache unit of the last serial connection level of OUT representative; (N+1) OUT represents the output terminal of the shift cache unit of back one serial connection level; As shown in the figure, according to the described shift register circuit of the embodiment of the invention, the output signal of shift cache units at different levels all differs the time of a clock period, meets the requirement of shift register circuit.
In addition, when the first transistor Q1 is switched on, the level signal that A is ordered is identical with output terminal (N-1) OUT of the shift cache unit of last serial connection level, then, when inversion clock signal XCK was high level signal, the A point was quick condition (floating state), utilize coupling pressure reduction (feed-though voltagedrop) principle, when clock signal CK is high level signal, be the grid of maintenance transistor seconds Q2 and the pressure reduction of first source/drain electrode, the level that can make A order is higher.
Fig. 4 represents the circuit structure diagram of the described shift cache unit of second embodiment of the invention.As shown in the figure, anti-phase device 20 is a phase inverter 21, and its input end is connected to first source/drain electrode of the first transistor Q1, and the output terminal of phase inverter 21 is connected to the grid of the 3rd transistor Q3.
Fig. 5 represents the circuit structure diagram of the described shift cache unit of third embodiment of the invention.As shown in the figure, anti-phase device 20 comprises: one the 5th transistor Q5, and its grid and first source/drain electrode couple inversion clock signal XCK, and its second source/drain electrode is connected to the gate terminal of the 3rd transistor Q3; And one the 6th transistor Q6, its grid is connected to first source/drain electrode of the first transistor Q1, and its first source/drain electrode is connected to the gate terminal of the 3rd transistor Q3, and its second source/drain electrode is connected to the first power supply VSS.
Fig. 6 represents the circuit structure diagram of the described shift cache unit of fourth embodiment of the invention.As shown in the figure, the input end of anti-phase device 20 is connected to output terminal (N) OUT, and the output terminal of anti-phase device 20 is connected to the grid of the 3rd transistor Q3.
Fig. 7 represents the circuit structure diagram of the described shift cache unit of fifth embodiment of the invention.As shown in the figure, anti-phase device 20 is a phase inverter 21; Its input end is connected to output terminal (N) OUT, and the output terminal of phase inverter 21 is connected to the grid of the 3rd transistor Q3, with so that output terminal (N) OUT when not exporting, can remain on low level.
Fig. 8 represents the circuit structure diagram of the described shift cache unit of sixth embodiment of the invention.As shown in the figure, anti-phase device 20 comprises: one the 5th transistor Q5, and its grid and first source/drain electrode couple inversion clock signal XCK, and its second source/drain electrode is connected to the gate terminal of the 3rd transistor Q3; And one the 6th transistor Q6, its grid is connected to output terminal (N) OUT, and its first source/drain electrode is connected to the grid of the 3rd transistor Q3, and its second source/drain electrode is connected to the first power supply VSS.
Fig. 9 represents the circuit structure diagram of the described shift cache unit of seventh embodiment of the invention.The 7th embodiment and the 6th embodiment difference are: the grid of the 5th transistor Q5 and first source/drain electrode are connected to second source VDD, and making only has the grid of the first transistor Q1 to receive inversion clock signal XCK, thereby reduce dynamic power dissipation.
Figure 10 represents that the present invention is applicable to the directional control circuit structural drawing of shift cache unit.As shown in the figure, directional control circuit 10 comprises: one the 7th transistor Q7, its grid receives one to left signal L, export left in order to the control shift register circuit, its first source/drain electrode is connected to output terminal (N-1) OUT of the shift cache unit of last serial connection level (N-1), and its second source/drain electrode is connected to node C; One the 8th transistor Q8, its grid receive to left signal L, and its first source/drain electrode is connected to output terminal (N+1) OUT of the shift cache unit of back one serial connection level (N+1), and its second source/drain electrode is connected to Node B;
One the 9th transistor Q9, its grid receives one to right signal R, export to the right in order to the control shift register circuit, its first source/drain electrode is connected to output terminal (N-1) OUT of the shift cache unit of last serial connection level (N 1), and its second source/drain electrode is connected to Node B; And 1 the tenth transistor Q10, its grid receive to right signal R, and its first source/drain electrode is connected to output terminal (N+1) OUT of the shift cache unit of back one serial connection level (N+1), and its second source/drain electrode is connected to node C.
If with the shift cache unit of Fig. 9 is example, the Node B of directional control circuit 10 is connected to (N-1) OUT end of Fig. 9, the node C of directional control circuit 10 is connected to (N+1) OUT end of Fig. 9; At this moment, a plurality of shift cache units with directional control circuit 10 are connected in series the shift register circuit that forms, the function of its outbound course of may command.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (21)
1. a shift register circuit has a plurality of shift cache units that are connected in series level, is applicable to a clock signal, an inversion clock signal and one first power supply, and described shift cache unit comprises:
One the first transistor, its grid couple described inversion clock signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level;
One anti-phase device has a first input end and one first output terminal, and described first input end is connected to first source/drain electrode of described the first transistor;
One transistor seconds, its grid are connected to second source/drain electrode of described the first transistor, and its first source/drain electrode couples described clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels;
One the 3rd transistor, its grid are connected to first output terminal of described anti-phase device, and its first source/drain electrode is connected to the output terminal of described shift cache unit at the corresponding levels; Its second source/drain electrode is connected to described first power supply; And
One the 4th transistor, its grid are connected to the output terminal of the shift cache unit of back one serial connection level, and its first source/drain electrode is connected to second source/drain electrode of described transistor seconds, and its second source/drain electrode is connected to described first power supply.
2. shift register circuit as claimed in claim 1, wherein, described anti-phase device comprises:
One the 5th transistor, its grid and first source/drain electrode couple described inversion clock signal, and its second source/drain electrode is connected to the described the 3rd transistorized gate terminal; And
One the 6th transistor, its grid are connected to first source/drain electrode of described the first transistor, and its first source/drain electrode is connected to the described the 3rd transistorized gate terminal, and its second source/drain electrode is connected to described first power supply.
3. shift register circuit as claimed in claim 1 wherein, also comprises: one first capacitor is connected between the grid and second source/drain electrode of described transistor seconds.
4. shift register circuit as claimed in claim 1, wherein, described transistor is the MOS thin film transistor (TFT).
5. shift register circuit as claimed in claim 2, wherein, described transistor is the MOS thin film transistor (TFT).
6. a shift register circuit has a plurality of shift cache units that are connected in series level, is applicable to a clock signal, an inversion clock signal and one first power supply, and described shift cache unit comprises:
One the first transistor, its grid couple described inversion clock signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level;
One transistor seconds, its grid are connected to second source/drain electrode of described the first transistor, and its first source/drain electrode couples described clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels;
One anti-phase device has a first input end and one first output terminal, and described first input end is connected to the output terminal of described shift cache unit at the corresponding levels;
One the 3rd transistor, its grid are connected to first output terminal of described anti-phase device, and its first source/drain electrode is connected to the output terminal of described shift cache unit at the corresponding levels; Its second source/drain electrode is connected to described first power supply; And
One the 4th transistor, its grid are connected to the output terminal of the shift cache unit of back one serial connection level, and its first source/drain electrode is connected to second source/drain electrode of described transistor seconds, and its second source/drain electrode is connected to described first power supply.
7. shift register circuit as claimed in claim 6, wherein, described anti-phase device comprises:
One the 5th transistor, its grid and first source/drain electrode couple a trigger pip, and its second source/drain electrode is connected to the described the 3rd transistorized gate terminal; And
One the 6th transistor, its grid is connected to the output terminal of described shift cache unit at the corresponding levels, and its first source/drain electrode is connected to the described the 3rd transistorized gate terminal, and its second source/drain electrode is connected to described first power supply.
8. shift register circuit as claimed in claim 7, wherein, described trigger pip is described inversion clock signal.
9. shift register circuit as claimed in claim 7, wherein, described trigger pip is a second source signal, and the level of described second source signal is greater than the level of described first power supply signal.
10. shift register circuit as claimed in claim 6 wherein, also comprises: one first capacitor is connected between the grid and second source/drain electrode of described transistor seconds.
11. shift register circuit as claimed in claim 6, wherein, described transistor is the MOS thin film transistor (TFT).
12. shift register circuit as claimed in claim 7, wherein, described transistor is the MOS thin film transistor (TFT).
13. a shift register circuit, the shift cache unit with a plurality of serial connection levels is applicable to a clock signal, an inversion clock signal and one first power supply, and described shift cache unit comprises:
One the first transistor, its grid couple described inversion clock signal, and its first source/drain electrode is connected to a trigger end;
One anti-phase device has a first input end and one first output terminal, and described first input end is connected to first source/drain electrode of described the first transistor;
One transistor seconds, its grid are connected to second source/drain electrode of described the first transistor, and its first source/drain electrode couples described clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels;
One the 3rd transistor, its grid are connected to first output terminal of described anti-phase device, and its first source/drain electrode is connected to the output terminal of described shift cache unit at the corresponding levels; Its second source/drain electrode is connected to described first power supply;
One the 4th transistor, its grid connect a replacement end, and its first source/drain electrode is connected to second source/drain electrode of described transistor seconds, and its second source/drain electrode is connected to described first power supply; And
One direction-control apparatus, in order to control the direction of described shift register circuit output, described direction-control apparatus comprises:
One the 7th transistor, its grid receive one to left signal, export left in order to control described shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to described replacement end;
One the 8th transistor, its grid receives described to left signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to described trigger end;
One the 9th transistor, its grid receive one to right signal, export to the right in order to control described shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to described trigger end; And
The tenth transistor, its grid receives described to right signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to described replacement end.
14. shift register circuit as claimed in claim 13, wherein, described anti-phase device comprises:
One the 5th transistor, its grid and first source/drain electrode couple described inversion clock signal, and its second source/drain electrode is connected to the described the 3rd transistorized gate terminal; And
One the 6th transistor, its grid are connected to first source/drain electrode of described the first transistor, and its first source/drain electrode is connected to the described the 3rd transistorized gate terminal, and its second source/drain electrode is connected to described first power supply.
15. shift register circuit as claimed in claim 14, wherein, described transistor is the MOS thin film transistor (TFT).
16. a shift register circuit, the shift cache unit with a plurality of serial connection levels is applicable to a clock signal, an inversion clock signal and one first power supply, and described shift cache unit comprises:
One the first transistor, its grid couple described inversion clock signal, and its first source/drain electrode is connected to a trigger end;
One transistor seconds, its grid are connected to second source/drain electrode of described the first transistor, and its first source/drain electrode couples described clock signal, and its second source/drain electrode is connected to the output terminal of shift cache unit at the corresponding levels;
One anti-phase device has a first input end and one first output terminal, and described first input end is connected to the output terminal of described shift cache unit at the corresponding levels;
One the 3rd transistor, its grid are connected to first output terminal of described anti-phase device, and its first source/drain electrode is connected to the output terminal of described shift cache unit at the corresponding levels; Its second source/drain electrode is connected to described first power supply;
One the 4th transistor, its grid are connected to a replacement end, and its first source/drain electrode is connected to second source/drain electrode of described transistor seconds, and its second source/drain electrode is connected to described first power supply; And
One direction-control apparatus, in order to control the direction of described shift register circuit output, described direction-control apparatus comprises:
One the 7th transistor, its grid receive one to left signal, export left in order to control described shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to described replacement end;
One the 8th transistor, its grid receives described to left signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to described trigger end;
One the 9th transistor, its grid receive one to right signal, export to the right in order to control described shift register circuit, and its first source/drain electrode is connected to the output terminal of the shift cache unit of last serial connection level, and its second source/drain electrode is connected to described trigger end; And
The tenth transistor, its grid receives described to right signal, and its first source/drain electrode is connected to the output terminal of the shift cache unit of back one serial connection level, and its second source/drain electrode is connected to described replacement end.
17. shift register circuit as claimed in claim 16, wherein, described anti-phase device comprises:
One the 5th transistor, its grid and first source/drain electrode are connected to a trigger pip, and its second source/drain electrode is connected to the described the 3rd transistorized gate terminal; And
One the 6th transistor, its grid is connected to the output terminal of described shift cache unit at the corresponding levels, and its first source/drain electrode is connected to the described the 3rd transistorized gate terminal, and its second source/drain electrode is connected to described first power supply.
18. shift register circuit as claimed in claim 17, wherein, described trigger pip is described inversion clock signal.
19. shift register circuit as claimed in claim 18, wherein, described trigger pip is a second source signal, and the level of described second source signal is greater than the level of described first power supply signal.
20. shift register circuit as claimed in claim 16, wherein, described transistor is the MOS thin film transistor (TFT).
21. shift register circuit as claimed in claim 17, wherein, described transistor is the MOS thin film transistor (TFT).
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| CNB031412491A CN100377258C (en) | 2003-06-04 | 2003-06-04 | Shift register circuit |
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| CNB031412491A CN100377258C (en) | 2003-06-04 | 2003-06-04 | Shift register circuit |
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| TWI281673B (en) | 2005-02-21 | 2007-05-21 | Au Optronics Corp | Shift registers, display panels using same, and improving methods for leakage current |
| CN100517511C (en) * | 2005-03-18 | 2009-07-22 | 友达光电股份有限公司 | Shift buffer, display panel utilizing the buffer and method for improving leakage current |
| CN101079325B (en) * | 2006-05-24 | 2010-12-29 | 奇美电子股份有限公司 | Shift register circuit |
| CN100533539C (en) * | 2006-12-30 | 2009-08-26 | 友达光电股份有限公司 | Grid drive circuit and its drive circuit unit |
| CN101556830B (en) * | 2008-04-10 | 2011-06-15 | 北京京东方光电科技有限公司 | Shift register and grid electrode driving device thereof |
| CN102708796B (en) | 2012-02-29 | 2014-08-06 | 京东方科技集团股份有限公司 | Gate driver on array unit, gate driver on array circuit and display device |
| CN102651208B (en) | 2012-03-14 | 2014-12-03 | 京东方科技集团股份有限公司 | Grid electrode driving circuit and display |
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|---|---|---|---|---|
| US4084106A (en) * | 1975-12-17 | 1978-04-11 | Itt Industries, Incorporated | Dynamic shift register using insulated-gate field-effect transistors |
| US5103116A (en) * | 1991-04-15 | 1992-04-07 | California Institute Of Technology | CMOS single phase registers |
| CN1236173A (en) * | 1998-05-14 | 1999-11-24 | 卡西欧计算机株式会社 | Shift register, display device,image sensing element driving apparatus, and image sensing apparatus |
| CN1369871A (en) * | 2001-02-13 | 2002-09-18 | 三星电子株式会社 | Shift register and liquid crystal display using same |
| CN1395256A (en) * | 2001-06-29 | 2003-02-05 | 卡西欧计算机株式会社 | Shift register and electronic device |
-
2003
- 2003-06-04 CN CNB031412491A patent/CN100377258C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4084106A (en) * | 1975-12-17 | 1978-04-11 | Itt Industries, Incorporated | Dynamic shift register using insulated-gate field-effect transistors |
| US5103116A (en) * | 1991-04-15 | 1992-04-07 | California Institute Of Technology | CMOS single phase registers |
| CN1236173A (en) * | 1998-05-14 | 1999-11-24 | 卡西欧计算机株式会社 | Shift register, display device,image sensing element driving apparatus, and image sensing apparatus |
| CN1369871A (en) * | 2001-02-13 | 2002-09-18 | 三星电子株式会社 | Shift register and liquid crystal display using same |
| CN1395256A (en) * | 2001-06-29 | 2003-02-05 | 卡西欧计算机株式会社 | Shift register and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1553456A (en) | 2004-12-08 |
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