CN102651208B - Grid electrode driving circuit and display - Google Patents

Grid electrode driving circuit and display Download PDF

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Publication number
CN102651208B
CN102651208B CN201210067475.3A CN201210067475A CN102651208B CN 102651208 B CN102651208 B CN 102651208B CN 201210067475 A CN201210067475 A CN 201210067475A CN 102651208 B CN102651208 B CN 102651208B
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China
Prior art keywords
transistor
circuit
signal
clock
gate driver
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CN201210067475.3A
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Chinese (zh)
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CN102651208A (en
Inventor
李天马
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN201210067475.3A priority Critical patent/CN102651208B/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/18Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using capacitors as main elements of the stages
    • G11C19/182Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms

Abstract

The invention provides a grid electrode driving circuit and a display. The grid electrode driving circuit comprises a plurality of cascaded shift registers, wherein each shift register comprises a signal output circuit, a signal input circuit, a reverse circuit and a logic circuit, the signal output circuit receives positive clock signals form an external circuit, the signal output circuit comprises a clock transistor and a level transistor, the clock transistor outputs clock signals, the level transistor outputs constant low level signals, the signal input circuit receives the output signal of the previous shift register, in addition, the clock transistor is conducted, the reverse circuit receives reverse clock signals form the external circuit, the clock transistor stops, meanwhile, the clock transistor is conducted, and the clock transistor is kept conducted through the logic circuit before the level transistor conduction. The power consumption of the grid electrode circuit is low, the anti-interference capability is high, and the output waveform is stable.

Description

A kind of gate driver circuit and display

Technical field

The invention belongs to field of display, be specifically related to a kind of for Thin Film Transistor-LCD gate driver circuit and the display of (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD).

Background technology

In TFT-LCD, the ultimate principle that shows each frame picture is by the required data-signal output from top to bottom successively of every one-row pixels by source electrode driver (source driver), meanwhile, gate drivers (gate driver) carries out gating to the square wave of every a line pixel gates input certain width successively from top to bottom.

Traditional method is that grid-driving integrated circuit (gate driver IC) and source electrode driven integrated circuit (source driver IC) are passed through to COG (Chip on Glass) technique nation line (bounding) on face glass.Yet, in actual production process, when the resolution of TFT-LCD is higher, the output that grid drives is more, and can increase the length of grid-driving integrated circuit, this has not only increased the difficulty of COG (Chip on Glass) technique, and has reduced the yield of product.

For this reason, person skilled has proposed the capable driving of array base palte (Gate Driver on Array, hereinafter to be referred as GOA) technology, it is that grid-driving integrated circuit is produced on face glass by array processes, this not only can reduce production costs, increase the reliability of panel, and for undersized TFT-LCD, can also reduce the difficulty of integrated circuit binding (IC bounding).

Shift register is for generation of the gate driver circuit of the required waveform of grid in GOA technology.Fig. 1 is the circuit theory diagrams of existing shift register.Refer to Fig. 1, shift register comprises four transistors and two electric capacity, and each transistor includes grid, source electrode and drain electrode.Wherein, the source electrode of the drain electrode of the first transistor T1, transistor seconds T2, the grid of the 3rd transistor T 3, the first capacitor C 1 and the second capacitor C 2 cross and form node P.The grid of the first transistor T1 is connected with source electrode, and as the signal input part STV of shift register, the drain electrode of the first transistor T1 is connected with the source electrode of transistor seconds T2; The grid of transistor seconds T2 is connected with the grid of the 4th transistor T 4, and receive from outside reset signal Reset, the drain electrode of transistor seconds T2 receives the low level signal Voff from external circuit; The source electrode of the 3rd transistor T 3 receives the second clock signal CLK2 from external circuit, the grid of the 3rd transistor T 3 is connected with node P, the drain electrode of the 3rd transistor T 3 is connected with source electrode, second capacitor C 2 of the 4th transistor T 4, and as the output terminal Row of shift register; The grid of the 4th transistor T 4 is connected with the grid of transistor seconds T2, and the drain electrode of the 4th transistor T 4 is connected with the drain electrode of transistor seconds T2, and receives the low level signal Voff from external circuit; One end of the first capacitor C 1 is connected with the first clock signal clk 1, and the other end is connected with node P; One end of the second capacitor C 2 is connected with node P, and the other end is connected with the drain electrode of the 3rd transistor T 3, the source electrode of the 4th transistor T 4.

Yet the clock frequency that above-mentioned shift register uses is higher, not only power consumption is higher to cause gate driver circuit for generation of the required waveform of grid, antijamming capability a little less than, and output power is less, burr is more, larger, sometimes also there will be unsettledly, cause output waveform unstable.

Summary of the invention

The technical problem to be solved in the present invention is exactly for the above-mentioned defect existing in prior art, and a kind of gate driver circuit is provided, and it is not only low in energy consumption, and antijamming capability is strong, and waveform stabilization.

For this reason, the present invention also provides a kind of display, and it is low in energy consumption, and antijamming capability is strong.

The technical scheme adopting solving the problems of the technologies described above is to provide a kind of gate driver circuit, comprises a plurality of cascade shift registers, and described shift register comprises:

Signal output apparatus, described signal output apparatus receives the forward clock signal from external circuit, described signal output apparatus comprises clock transistor and level transistor, and described clock transistor is at clock signal, and described level transistor is exported permanent low level signal;

Signal input circuit, described signal input circuit is connected with described clock transistor, and it receives the output signal of last shift register, and makes described clock transistor conducting;

Negater circuit, described negater circuit is connected with level transistor with described clock transistor, and it receives the reverse clock signal from external circuit, and makes described clock transistor cut-off, makes described level transistor turns simultaneously;

Logical circuit, described logical circuit is connected with described clock transistor, and it makes described clock transistor keep conducting before described level transistor turns.

Wherein, described signal input circuit, described signal output apparatus, described negater circuit and the described logical circuit formation first node that crosses; Described signal output apparatus and the described negater circuit formation Section Point that crosses.

Wherein, described signal output apparatus, described signal input circuit and described negater circuit are all comprised of MOS transistor npn npn.

Wherein, described signal input circuit comprises the first transistor, and the source electrode of described the first transistor is connected the output signal of last shift register with grid; The drain electrode of described the first transistor is connected to described first node.

Wherein, described clock transistor comprises transistor seconds, and described level transistor comprises the 3rd transistor; The source electrode of described transistor seconds receives the forward clock signal from external circuit; The grid of described transistor seconds is connected to described first node; The drain electrode of described transistor seconds is connected with described the 3rd transistorized source electrode, and in the lump as the output terminal of described signal output apparatus; Described the 3rd transistorized grid is connected to described Section Point; Described the 3rd transistorized drain electrode receives the low level signal from external circuit.

Wherein, described negater circuit comprises the 4th transistor and the 5th transistor, and described the 4th transistorized source electrode receives the high level signal from external circuit; Described the 4th transistorized grid is connected with described the 5th transistorized grid, and all receives the reverse clock signal from external circuit; Described the 4th transistorized drain electrode is connected to described Section Point; Described the 5th transistorized source electrode is connected to described first node; Described the 5th transistorized drain electrode receives the low level signal from external circuit.

Wherein, described logical circuit comprises electric capacity, and one end of described electric capacity is connected to described first node, and the other end of described electric capacity connects and is connected with the low level signal of external circuit.

Wherein, also comprise: holding circuit, described holding circuit is when described clock transistor conducting, guarantees described level transistor remain off.

Wherein, described holding circuit comprises the 6th transistor and the 7th transistor, and described the 6th transistorized source electrode is connected with described the 7th transistorized source electrode, and is connected to described Section Point; Described the 6th transistorized grid is connected to described first node; Described the 6th transistorized drain electrode is connected with described the 7th transistorized drain electrode, and receives in the lump the low level signal from external circuit; Described the 7th transistorized grid receives the forward clock signal from external circuit.

The present invention also provides a kind of display, comprises gate driver circuit, and described gate driver circuit adopts described gate driver circuit provided by the invention.

The present invention has following beneficial effect:

One, the signal input circuit of gate driver circuit provided by the invention is the output signal that receives last shift register, and makes described clock transistor conducting; And negater circuit receives after the reverse clock signal from external circuit, make described clock transistor cut-off, and make described level transistor turns; Thereby reduced clock frequency, and then reduced the power consumption of gate driver circuit, improved the antijamming capability of gate driver circuit.

Its two, logical circuit is before described level transistor turns, makes described clock transistor keep conducting, has reduced the burr of output waveform, thereby has improved the stability of gate driver circuit output waveform.

Its three, the transistor that gate driver circuit provided by the invention is used is less, that is, adopt less transistor to obtain the required waveform of terrible grid, thereby reduced the cost of gate driver circuit.

Therefore, display provided by the invention is when carrying out line scanning, and the clock frequency of use is lower, thereby has reduced the power consumption of display, has improved the antijamming capability of display, and then has improved the image quality of display.In addition, the transistor that gate driver circuit is used is less, thereby can reduce the cost of display.

Accompanying drawing explanation

Fig. 1 is the circuit theory diagrams of existing shift register;

Fig. 2 is the structured flowchart of embodiment of the present invention gate driver circuit;

Fig. 3 is the circuit theory diagrams of the shift register in embodiment of the present invention gate driver circuit;

Fig. 4 is the working timing figure of the shift register in embodiment of the present invention gate driver circuit;

Fig. 5 is the output waveform figure of embodiment of the present invention gate driver circuit;

Fig. 6 is the structural representation of embodiment of the present invention display.

Embodiment

For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with accompanying drawing, gate driver circuit provided by the invention and display are described in detail.

Fig. 2 is the structured flowchart of embodiment of the present invention gate driver circuit.Refer to Fig. 2, the gate driver circuit that the present embodiment provides comprises a plurality of shift register OUT1, OUT2 and OUT3 with same circuits structure, a plurality of shift register cascades, receive successively forward clock signal clk that external circuit provides and the reverse clock signal clk B contrary with this forward clock signal clk, the input end STV of a rear shift register connects the output terminal OUTPUT of last shift register.

Fig. 3 is the circuit theory diagrams of the shift register in embodiment of the present invention gate driver circuit.See also Fig. 2 and Fig. 3, each shift register includes:

One signal output apparatus 32, it receives the forward clock signal clk from external circuit, and signal output apparatus 32 comprises clock transistor and level transistor, clock transistor clock signal, level transistor is exported permanent low level signal;

One signal input circuit 31, signal input circuit 31 is connected with clock transistor, and it receives the output signal of last shift register, and makes clock transistor conducting;

One negater circuit 33, negater circuit 33 is connected with level transistor with clock transistor, and the reverse clock signal clk B that it receives from external circuit makes clock transistor cut-off simultaneously, makes level transistor turns;

One logical circuit 34, logical circuit 34 is connected with clock transistor, and it makes clock transistor keep conducting before level transistor turns; And

Wherein, signal input circuit 31, signal output apparatus 32, negater circuit 33, logical circuit 34 and holding circuit 35 cross and form first node P; Signal output apparatus 32, negater circuit 33 and holding circuit 35 cross and form Section Point Q.And signal input circuit 31, signal output apparatus 32, negater circuit 33 and holding circuit 35 are all comprised of nmos type transistor.

Signal input circuit 31 comprises the first transistor M1, the source electrode of the first transistor M1 is connected with its grid, and as the input end STV of register, be connected with the output terminal of last shift register (output terminal of signal output apparatus 32) OUTPUT in the lump, to receive the output signal of last shift register; The drain electrode of the first transistor M1 is connected to first node P.

Clock transistor in signal output apparatus 32 comprises transistor seconds M2, and level transistor comprises the 3rd transistor M3; The source electrode of transistor seconds M2 receives the forward clock signal clk from external circuit; The grid of transistor seconds M2 is connected to first node P; The drain electrode of transistor seconds M2 is connected with the source electrode of the 3rd transistor M3, and in the lump as the output terminal OUTPUT of register; The grid of the 3rd transistor M3 is connected to Section Point Q; The drain electrode of the 3rd transistor M3 receives the low level signal Vss from external circuit.

Negater circuit 33 comprises the 4th transistor M4 and the 5th transistor M5, and the source electrode of the 4th transistor M4 receives the high level signal Vdd from external circuit; The grid of the 4th transistor M4 is connected with the grid of the 5th transistor M5, and all receives the reverse clock signal clk B from external circuit; The drain electrode of the 4th transistor M4 is connected to Section Point Q; The source electrode of the 5th transistor M5 is connected to first node P; The drain electrode of the 5th transistor M5 receives the low level signal Vss from external circuit.

Logical circuit 34 comprises capacitor C 0, and one end of capacitor C 0 is connected to first node P, and the other end of capacitor C 0 connects and is connected with the low level signal Vss of external circuit.

When the 3rd transistor M3 cut-off, logical circuit 34 can make first node P keep high level, thereby makes transistor seconds M2 keep conducting, makes the clock signal of signal output apparatus stable output, and then makes the stable waveform of shift register output.

Preferably, shift register also comprises:

One holding circuit 35, it is when clock transistor conducting, guarantees level transistor remain off.

Holding circuit 35 comprises the 6th transistor M6 and the 7th transistor M7, and the source electrode of the 6th crystal M6 pipe is connected with the source electrode of the 7th transistor M7, and is connected in the lump Section Point Q; The grid of the 6th transistor M6 is connected to first node P; The drain electrode of the 6th transistor M6 is connected with the drain electrode of the 7th transistor M7, and receives in the lump the low level signal Vss from external circuit; The grid of the 7th transistor M7 receives the forward clock signal clk from external circuit.

The present embodiment by holding circuit 35 when the transistor seconds M2 conducting, make the 3rd transistor M3 remain off, thereby can avoid affecting because of the 3rd transistor M3 conducting the clock signal of signal output apparatus output, and then make the stable waveform of shift register output.

Fig. 4 is the working timing figure of the shift register in embodiment of the present invention gate driver circuit.See also Fig. 3 and Fig. 4, at t1, before the time period, first reverse clock signal clk B is applied to a high level, make the 5th transistor M5 conducting, capacitor C 0 electric discharge, thus make first node P in low level, and then transistor seconds M2 is disconnected.Meanwhile, the 4th transistor M4 conducting, makes Section Point Q in high level, thereby makes the 3rd transistor M3 conducting, shift register output low level.

At t1 in the time period, reverse clock signal clk B input low level signal, the 4th transistor M4 and the 5th transistor M5 cut-off.The input end STV of shift register receives start signal, or title Input signal, start signal is high level signal, the first transistor M1 conducting, capacitor C 0 charging, first node P is in high level, thereby makes the 6th transistor M6 conducting, guarantee that Section Point Q is in low level, the 3rd transistor M3 cut-off; Make transistor seconds M2 conducting, forward clock signal clk output low level clock signal, the output end vo ut output low level of shift register simultaneously.

At t2 in the time period, reverse clock signal clk B input low level signal, the 4th transistor M4 and the 5th transistor M5 cut-off.First node P because capacitor C 0 is recharged still in high level, transistor seconds M2 and the 6th transistor M6 conducting, Section Point Q is in low level, the 3rd transistor M3 cut-off.Forward clock signal clk output high level clock signal, the output end vo ut output high level of shift register; The 7th transistor M7 conducting simultaneously, the 6th transistor M6 and the 7th transistor M7 conducting, can guarantee that Section Point Q is in low level, thereby can guarantee the 3rd transistor M3 cut-off, thereby the output signal of the output end vo ut of shift register is synchronizeed with the output of forward clock signal clk, be that forward clock signal clk is while being high level, the output end vo ut of shift register is output as high level, when forward clock signal clk is low level, the output end vo ut of shift register is output as low level.

At t3 in the time period, reverse clock signal clk B input low level signal, the 4th transistor M4 and the 5th transistor M5 cut-off.First node P is due to the former of capacitor C 0 thereby still in high level, transistor seconds M2 and the 6th transistor M6 conducting, and Section Point Q is in low level, the 3rd transistor M3 cut-off.Forward clock signal clk output low level clock signal, the output end vo ut output low level of shift register; The 7th transistor M7 cut-off simultaneously, the 6th transistor M6 conducting, can guarantee that Section Point Q is in low level, the 3rd transistor M3 cut-off.

At t4 in the time period, forward clock signal clk output low level clock signal, the 7th transistor M7 cut-off.Reverse clock signal clk B input high level signal, the 4th transistor M4 and the 5th transistor M5 conducting.The 5th transistor M5 conducting makes capacitor C 0 electric discharge, and first node P is in low level, and transistor seconds M2 and the 6th transistor M6 end.The 4th transistor M4 conducting, Section Point Q is in high level, the 3rd transistor M3 conducting, the output end vo ut output low level of shift register.

From work schedule, the clock frequency that shift register uses is lower, thereby can effectively reduce the power consumption of gate driver circuit, and can improve the antijamming capability of gate driver circuit.In addition, the output waveform of shift register is stable, thereby makes the stable output of gate driver circuit, and as shown in Figure 5, Fig. 5 is the output waveform figure of embodiment of the present invention gate driver circuit.In addition, the present embodiment gate driver circuit has adopted less transistor can obtain the required waveform of grid of waveform stabilization, has used less transistor, thereby can reduce the production cost of gate driver circuit.

It should be noted that, although the present embodiment gate driver circuit is comprised of nmos type transistor, but the present invention is not limited thereto, gate driver circuit also can adopt pmos type transistor to form, and can obtain the technical matters identical with nmos type transistor.

The gate driver circuit that the present embodiment provides has the following advantages:

One, the signal input circuit of gate driver circuit is the output signal that receives last shift register, and makes described clock transistor conducting; And negater circuit receives after the reverse clock signal from external circuit, make described clock transistor cut-off, and make described level transistor turns; Thereby reduced clock frequency, and then reduced the power consumption of gate driver circuit, improved the antijamming capability of gate driver circuit.

Its two, logical circuit is before described level transistor turns, makes described clock transistor keep conducting, has reduced the burr of output waveform, thereby has improved the stability of gate driver circuit output waveform.

Its three, gate driver circuit adopts less transistor to obtain the required waveform of grid, thereby has reduced the cost of gate driver circuit.

Fig. 6 is the structural representation of embodiment of the present invention display.Refer to Fig. 6, display comprises display panels, gate driver circuit 200 and data drive circuit 300, liquid crystal panel comprises array base palte 100, color membrane substrates (not shown) and is arranged on the liquid crystal molecule (not shown) between array base palte 100 and color membrane substrates, on array base palte 100, be provided with the thin film transistor (TFT) array of controlling liquid crystal molecule windup-degree, gate driver circuit 200 output horizontal-drive signals are to control conducting or the cut-off of thin film transistor (TFT).And, the gate driver circuit that gate driver circuit 200 adopts the present embodiment to provide.

The present embodiment display is due to the gate driver circuit that adopts above-mentioned the present embodiment to provide, it is when carrying out line scanning, and the clock frequency of use is lower, thereby has reduced the power consumption of display, improve the antijamming capability of display, and then improved the image quality of display.In addition, the transistor that gate driver circuit is used is less, thereby can reduce the cost of display.

Be understandable that, above embodiment is only used to principle of the present invention is described and the illustrative embodiments that adopts, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.

Claims (10)

1. a gate driver circuit, comprises a plurality of cascade shift registers, it is characterized in that, described shift register comprises:
Signal output apparatus, described signal output apparatus receives the forward clock signal from external circuit, described signal output apparatus comprises clock transistor and level transistor, described clock transistor clock signal, and described level transistor is exported permanent low level signal;
Signal input circuit, described signal input circuit is connected with described clock transistor, and it receives the output signal of last shift register, and makes described clock transistor conducting;
Negater circuit, described negater circuit is connected with level transistor with described clock transistor, and it receives the reverse clock signal from external circuit, and makes described clock transistor cut-off, makes described level transistor turns simultaneously;
Logical circuit, described logical circuit is connected with described clock transistor, and it makes described clock transistor keep conducting before described level transistor turns.
2. gate driver circuit according to claim 1, is characterized in that, described signal input circuit, described signal output apparatus, described negater circuit and the described logical circuit formation first node that crosses; Described signal output apparatus and the described negater circuit formation Section Point that crosses.
3. gate driver circuit according to claim 2, is characterized in that, described signal output apparatus, described signal input circuit and described negater circuit are all comprised of MOS transistor npn npn.
4. gate driver circuit according to claim 3, is characterized in that, described signal input circuit comprises the first transistor, and the source electrode of described the first transistor is connected the output signal of last shift register with grid; The drain electrode of described the first transistor is connected to described first node.
5. gate driver circuit according to claim 3, is characterized in that, described clock transistor comprises transistor seconds, and described level transistor comprises the 3rd transistor; The source electrode of described transistor seconds receives the forward clock signal from external circuit; The grid of described transistor seconds is connected to described first node; The drain electrode of described transistor seconds is connected with described the 3rd transistorized source electrode, and in the lump as the output terminal of described signal output apparatus; Described the 3rd transistorized grid is connected to described Section Point; Described the 3rd transistorized drain electrode receives the low level signal from external circuit.
6. gate driver circuit according to claim 3, is characterized in that, described negater circuit comprises the 4th transistor and the 5th transistor, and described the 4th transistorized source electrode receives the high level signal from external circuit; Described the 4th transistorized grid is connected with described the 5th transistorized grid, and all receives the reverse clock signal from external circuit; Described the 4th transistorized drain electrode is connected to described Section Point; Described the 5th transistorized source electrode is connected to described first node; Described the 5th transistorized drain electrode receives the low level signal from external circuit.
7. gate driver circuit according to claim 3, is characterized in that, described logical circuit comprises electric capacity, and one end of described electric capacity is connected to described first node, and the other end of described electric capacity connects and is connected with the low level signal of external circuit.
8. gate driver circuit according to claim 2, is characterized in that, also comprises:
Holding circuit, described holding circuit is when described clock transistor conducting, guarantees described level transistor remain off.
9. gate driver circuit according to claim 8, is characterized in that, described holding circuit comprises the 6th transistor and the 7th transistor, and described the 6th transistorized source electrode is connected with described the 7th transistorized source electrode, and is connected to described Section Point; Described the 6th transistorized grid is connected to described first node; Described the 6th transistorized drain electrode is connected with described the 7th transistorized drain electrode, and receives in the lump the low level signal from external circuit; Described the 7th transistorized grid receives the forward clock signal from external circuit.
10. a display, comprises gate driver circuit, it is characterized in that, described gate driver circuit adopts the gate driver circuit described in claim 1-9 any one.
CN201210067475.3A 2012-03-14 2012-03-14 Grid electrode driving circuit and display CN102651208B (en)

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Application Number Priority Date Filing Date Title
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CN201210067475.3A CN102651208B (en) 2012-03-14 2012-03-14 Grid electrode driving circuit and display
PCT/CN2012/084022 WO2013135061A1 (en) 2012-03-14 2012-11-02 Gate drive circuit and display
US13/995,142 US9201445B2 (en) 2012-03-14 2012-11-02 Gate driving circuit for thin film transistor liquid crystal display and thin film transistor liquid crystal display

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CN102651208B true CN102651208B (en) 2014-12-03

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US20140085283A1 (en) 2014-03-27

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