KR960016140A - Output buffer circuit of memory device - Google Patents

Output buffer circuit of memory device Download PDF

Info

Publication number
KR960016140A
KR960016140A KR1019940026223A KR19940026223A KR960016140A KR 960016140 A KR960016140 A KR 960016140A KR 1019940026223 A KR1019940026223 A KR 1019940026223A KR 19940026223 A KR19940026223 A KR 19940026223A KR 960016140 A KR960016140 A KR 960016140A
Authority
KR
South Korea
Prior art keywords
output
switching means
gate
pull
voltage
Prior art date
Application number
KR1019940026223A
Other languages
Korean (ko)
Other versions
KR0127220B1 (en
Inventor
백대봉
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940026223A priority Critical patent/KR0127220B1/en
Priority to US08/362,301 priority patent/US5537060A/en
Priority to JP7041808A priority patent/JP3032694B2/en
Publication of KR960016140A publication Critical patent/KR960016140A/en
Application granted granted Critical
Publication of KR0127220B1 publication Critical patent/KR0127220B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements

Landscapes

  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

본 발명은 메모리소자의 출력버퍼에 관한 것으로, 특히 갑작스런 피크전류에 의해 출력신호가 왜곡되는 현상을 방지하기 위하여, 로드캐패시턴스의 충진 및 방진이 출력 전압의 레벨에 따라 병렬의 경로를 선택적으로 통하여 이루어지게 함으로써 피크전류를 낮추어 출력신호의 안정화를 도모한 것이다. 이를 위하여 본 발명은 2개의 병렬경로를 형성하고 있는 제1, 제2스위칭수단이 출력단자의 전압레벨에 따라 각각 신택되어 출력단자에 연결된 로드캐패시턴스를 충전시키는 풀업패스(path)와, 2개의 병렬경로를 형성하고 있는 제3, 제4스위칭수단이 출력단자의 전압레벨에 따라 각각 선택되어 로드인덕턴스를 통하여 로드 캐패시턴스를 방전시키는 풀다운패스를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer of a memory device. In particular, in order to prevent the output signal from being distorted due to a sudden peak current, charging and dusting of the load capacitance are selectively performed through parallel paths according to the level of the output voltage. By reducing the peak current, the output signal is stabilized. To this end, the present invention provides a pull-up path for charging a load capacitance connected to an output terminal by first and second switching means forming two parallel paths, respectively, depending on the voltage level of the output terminal, and two parallel paths. The third and fourth switching means forming the paths are respectively selected according to the voltage level of the output terminal and include a pull-down pass for discharging the load capacitance through the load inductance.

Description

메모리소자의 출력버퍼회로Output buffer circuit of memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 출력버퍼회로의 구성도.3 is a configuration diagram of an output buffer circuit according to the present invention.

Claims (8)

2개의 병렬경로를 형성하고 있는 제1, 제2스위칭수단이 출력단자의 전압레벨에 따라 각각 선택되어 출력단자에 연결된 로드 캐패시턴스를 충진시키는 풀업패스(path)와; 2개의 병렬경로를 형성하고 있는 제3, 제4스위칭수단이 출력단자의 전압레벨에 따라 각각 선택되어 로드인덕턴스를 통하여 로드캐패시턴스를 방전시키는 풀다운패스를 포함하는 메모리 소자의 출력버퍼회로.First and second switching means forming two parallel paths, each of which is selected according to the voltage level of the output terminal and fills a load capacitance connected to the output terminal; And a pull-down pass for discharging the load capacitance through the load inductance, wherein the third and fourth switching means respectively forming two parallel paths are selected according to the voltage level of the output terminal. 제1항에 있어서, 상기 제1, 제3스위칭수단과, 제2, 제4스위칭수단은 각각 상호 대칭적으로(complement arily) 구성됨을 특징으로 하는 메모리 소자의 출력버퍼회로.2. The output buffer circuit as claimed in claim 1, wherein the first and third switching means and the second and fourth switching means are configured to be symmetric with each other. 제1항에 있어서, 상기 풀업패스의 스위칭수단은 피모스트탠지스터임을 특징으로 하는 메모리소자의 출력 버퍼회로.2. The output buffer circuit of claim 1, wherein the switching means of the pull-up path is a pitistoristor. 제1항에 있어서, 상기 풀다운패스의 스위칭 수단은 엔모스트랜지스터임을 특징으로 하는 메모리소자의 출력버퍼회로.2. The output buffer circuit as claimed in claim 1, wherein the switching means of the pull-down path is an enMOS transistor. 제1항에 있어서, 상기 풀업패스는 데이타 신호와 인버터에서 반전된 출력인에이블신호(OE)를 노아연산하는 제1노아게이트와; 출력단자의 전압과 인버터에서 반전된 출력 인에이블신호(OE)를 노아연산하여 제1,제2트랜스미션게이트를 선택하는 제2노아게이트와; 상기 제2노아게이트의 출력신호에 의해 신택되어 상기 제1노아게이트의 출력신호를 제1, 제2스위칭수단에 각각 전달하는 제1, 제2트랜스미션게이트와; 인버터에서 반전된 상기 제1, 제2트랜스미션게이트의 출력신호에 의해 스위칭되어 전원전압이 로드캐패시턴스에 충진되게 하는 제1, 제2스위칭수단을 포함하는 메모리소자의 출력버퍼회로.2. The apparatus of claim 1, wherein the pull-up path comprises: a first noble gate for nil computing a data signal and an enable signal OE inverted by an inverter; A second NOR gate configured to select the first and second transmission gates by performing a NO operation on the voltage of the output terminal and the output enable signal OE inverted by the inverter; First and second transmission gates, which are syntaxed by the output signal of the second Noah gate and transfer the output signal of the first Noah gate to first and second switching means, respectively; And first and second switching means configured to be switched by output signals of the first and second transmission gates inverted in the inverter so that a power supply voltage is filled in the load capacitance. 제5항에 있어서, 상기 제2노아게이트는 문턱 전압의 조정에 의해 병렬 충전 경로의 스위칭 타임을 조정가능함을 특징으로 하는 메모리소자의 출력버퍼회로.6. The output buffer circuit as claimed in claim 5, wherein the second NOR gate is capable of adjusting the switching time of the parallel charging path by adjusting the threshold voltage. 제1항에 있어서, 상기 풀다운패스는 데이타 신호와 출력 인에이블신호(OE)를 낸드연산하는 제1낸드게이트와; 출력단자의 전압과 출력 인에이블신호(OE)를 낸드연산하여 제3, 제4트랜스미선게이트를 선택하는 제2낸드게이트와; 상기 제2낸드케이트의 출력신호에 의해 선택되어 상기 제1낸드게이트의 출력신호를 제3, 제4스위칭수단에 각각 전달하는 제3, 제4트랜스미선게이트와; 인버터에서 반전된 상기 제3, 제4트랜스미선게이트의 출력신호에 의해 스위칭되어 상기 로드개패시턴스의 전압이 로드인덕턴스를 통해 방진되게 하는 제3, 제4스위칭수단을 포함하는 메모리소자의 출력 버퍼회로.The display device of claim 1, wherein the pull-down path comprises: a first NAND gate NAND-operating a data signal and an output enable signal (OE); A second NAND gate for NAND-operating the voltage of the output terminal and the output enable signal OE to select the third and fourth transistor lines; Third and fourth transistor lines selected by the output signal of the second NAND gate and transferring the output signal of the first NAND gate to third and fourth switching means, respectively; An output buffer of a memory device including third and fourth switching means for switching by an output signal of the third and fourth transistor gates inverted in an inverter to cause the voltage of the load capacitance to be dustproof through the load inductance Circuit. 제7항에 있어서, 상기 제2낸드게이트는 문턱 전압의 조정에 의해 병렬 방전경로의 스위칭타임을 조정가능함을 특징으로 하는 메모리소자의 출력버퍼회로.8. The output buffer circuit as claimed in claim 7, wherein the second NAND gate is capable of adjusting switching times of parallel discharge paths by adjusting threshold voltages. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026223A 1994-10-13 1994-10-13 Output buffer circuit of memory device KR0127220B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940026223A KR0127220B1 (en) 1994-10-13 1994-10-13 Output buffer circuit of memory device
US08/362,301 US5537060A (en) 1994-10-13 1994-12-22 Output buffer circuit for memory device
JP7041808A JP3032694B2 (en) 1994-10-13 1995-03-01 Output buffer circuit of memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940026223A KR0127220B1 (en) 1994-10-13 1994-10-13 Output buffer circuit of memory device

Publications (2)

Publication Number Publication Date
KR960016140A true KR960016140A (en) 1996-05-22
KR0127220B1 KR0127220B1 (en) 1998-04-02

Family

ID=19395042

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940026223A KR0127220B1 (en) 1994-10-13 1994-10-13 Output buffer circuit of memory device

Country Status (3)

Country Link
US (1) US5537060A (en)
JP (1) JP3032694B2 (en)
KR (1) KR0127220B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402241B1 (en) * 2001-06-30 2003-10-17 주식회사 하이닉스반도체 Current controlled low noise output driver
KR100457343B1 (en) * 1997-11-15 2005-04-06 삼성전자주식회사 Double buffer circuit for low consumption current in uncertainty region

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5486782A (en) * 1994-09-27 1996-01-23 International Business Machines Corporation Transmission line output driver
US5568084A (en) * 1994-12-16 1996-10-22 Sgs-Thomson Microelectronics, Inc. Circuit for providing a compensated bias voltage
US5877647A (en) * 1995-10-16 1999-03-02 Texas Instruments Incorporated CMOS output buffer with slew rate control
US5701275A (en) * 1996-01-19 1997-12-23 Sgs-Thomson Microelectronics, Inc. Pipelined chip enable control circuitry and methodology
US5801563A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Output driver circuitry having a single slew rate resistor
KR0175279B1 (en) * 1996-04-04 1999-04-01 김광호 CMOS output buffer circuit
US5898315A (en) * 1996-05-17 1999-04-27 Cypress Semiconductor Corp. Output buffer circuit and method having improved access
US5966031A (en) * 1996-09-02 1999-10-12 Yahama Corporation Output circuit for integrated circuit devices
US5760634A (en) * 1996-09-12 1998-06-02 United Microelectronics Corporation High speed, low noise output buffer
KR100246336B1 (en) * 1997-03-22 2000-03-15 김영환 Output circuit of memory
US6184703B1 (en) * 1997-06-06 2001-02-06 Altera Corporation Method and circuit for reducing output ground and power bounce noise
US5929667A (en) * 1997-06-10 1999-07-27 International Business Machines Corporation Method and apparatus for protecting circuits subjected to high voltage
US5966036A (en) * 1997-09-09 1999-10-12 S3 Incorporated System and method for a mixed voltage drive system for floating substrate technology
US6169419B1 (en) 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6191606B1 (en) * 1998-09-10 2001-02-20 Intel Corporation Method and apparatus for reducing standby leakage current using input vector activation
US6329874B1 (en) 1998-09-11 2001-12-11 Intel Corporation Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
US6242942B1 (en) 1998-11-13 2001-06-05 Integrated Device Technology, Inc. Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics
US6356102B1 (en) 1998-11-13 2002-03-12 Integrated Device Technology, Inc. Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals
US6091260A (en) * 1998-11-13 2000-07-18 Integrated Device Technology, Inc. Integrated circuit output buffers having low propagation delay and improved noise characteristics
KR100301068B1 (en) * 1999-08-31 2001-11-01 윤종용 Bus driving apparatus and method with consuming low power
US6414523B1 (en) * 2000-01-24 2002-07-02 Matsushita Electrical Industrial Co., Ltd. Pull-up method and apparatus for a universal serial bus output driver
US6441643B1 (en) * 2000-02-28 2002-08-27 International Business Machines Corporation Method and apparatus for driving multiple voltages
KR100833414B1 (en) * 2002-06-29 2008-05-29 주식회사 하이닉스반도체 Tri-state buffer
US6879191B2 (en) * 2003-08-26 2005-04-12 Intel Corporation Voltage mismatch tolerant input/output buffer
DE10355509A1 (en) * 2003-11-27 2005-07-07 Infineon Technologies Ag Circuit and method for delayed switching on of an electrical load
US7760006B2 (en) * 2008-05-08 2010-07-20 Texas Instruments Incorporated Method and system to reduce electromagnetic radiation from semiconductor devices
JP6333028B2 (en) * 2013-04-19 2018-05-30 株式会社半導体エネルギー研究所 Memory device and semiconductor device
CN106249453B (en) * 2016-03-25 2023-08-15 北京集创北方科技股份有限公司 Low-power source electrode driving circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6310818A (en) * 1986-06-30 1988-01-18 Mitsubishi Electric Corp Output buffer circuit
US4959561A (en) * 1989-01-04 1990-09-25 Motorola, Inc. MOS output buffer with reduced supply line disturbance
KR920002426B1 (en) * 1989-05-31 1992-03-23 현대전자산업 주식회사 Output buffer circuitry of integrated circuit
US5319260A (en) * 1991-07-23 1994-06-07 Standard Microsystems Corporation Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
US5332932A (en) * 1991-09-16 1994-07-26 Advanced Micro Devices, Inc. Output driver circuit having reduced VSS/VDD voltage fluctuations
US5426376A (en) * 1993-04-23 1995-06-20 Vlsi Technology, Inc. Noise isolated I/O buffer that uses two separate power supplies

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100457343B1 (en) * 1997-11-15 2005-04-06 삼성전자주식회사 Double buffer circuit for low consumption current in uncertainty region
KR100402241B1 (en) * 2001-06-30 2003-10-17 주식회사 하이닉스반도체 Current controlled low noise output driver

Also Published As

Publication number Publication date
JP3032694B2 (en) 2000-04-17
US5537060A (en) 1996-07-16
KR0127220B1 (en) 1998-04-02
JPH08124382A (en) 1996-05-17

Similar Documents

Publication Publication Date Title
KR960016140A (en) Output buffer circuit of memory device
KR930003540A (en) Noise suppressed data output buffer
KR950006850A (en) Selector circuit
US6084459A (en) Voltage level shifting circuit
US5097159A (en) Delay circuit for delaying an output signal relative to an input signal for a specified time interval
KR100211758B1 (en) Multi-power data buffer
US5210449A (en) Edge triggered tri-state output buffer
US5739701A (en) Input/output buffer circuit having reduced power consumption
EP0139904B1 (en) Improved tristate control circuitry for a driver circuit
EP0202582A2 (en) A NMOS data storage cell and shift register
US4242738A (en) Look ahead high speed circuitry
WO1982000741A1 (en) Clocked igfet logic circuit
KR960012723A (en) Output Circuit of Gunning Transceiver Logic
US6236234B1 (en) High-speed low-power consumption interface circuit
KR20010058871A (en) Logic gate circuit having low sub-threshold leakage current
GB2059707A (en) Power-on reset circuit
KR100470162B1 (en) Semiconductor device with improved precharge operation according to power supply voltage
JP2937349B2 (en) Semiconductor integrated circuit
KR100243020B1 (en) Output buffer circuit
KR0154728B1 (en) Memory circuit with high voltage generator
KR950022139A (en) Input buffer of semiconductor memory device
KR100305645B1 (en) Data path circuit of semiconductor memory device
KR100253347B1 (en) Output buffer circuit
KR0150160B1 (en) Semiconductor apparatus having loading compensating circuit of bus line
KR970002828A (en) Pull-Up / Pull-Down Bidirectional Data Input and Output Short Circuit with Enable

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120924

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20130916

Year of fee payment: 17

EXPY Expiration of term