KR100253347B1 - Output buffer circuit - Google Patents

Abstract

PURPOSE: An output buffer circuit is provided which pre-charges an output terminal before data are output to reduce access time and prevents noise from generating in output data. CONSTITUTION: An output buffer circuit includes an input part(1), a pre-charge controller(2) and a pre-charge driver(3). The input part outputs input data and inverted input data according to an output control signal. The pre-charge controller blocks the output signal of the input part from being transmitted or transmits the output signal according to a pre-charge control signal. The pre-charge driver outputs output data when the output signal is applied under the control of the pre-charge controller, and pre-charges an output terminal according to the pre-charge control signal and inverted pre-charge control signal when there is no application of the output signal of the input part.

Description

Output buffer circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly, to an output buffer circuit that precharges an output stage before data is output to reduce the access time and to prevent noise from occurring in the output data.

In general, the output buffer circuit, the output buffer circuit delays the input signal for a predetermined time and outputs it in synchronization with other circuits, or changes the input signal in the range of voltage used in other peripheral circuits and outputs it. In general, it comprises a delay means such as an inverter and switching means for controlling the same. Usually, the output stage performs an operation of precharging to a predetermined value in order to minimize the noise effect of the output signal, which will be described in detail with reference to the accompanying drawings.

1 is a conventional output buffer circuit diagram, which shows inverters INV1 and INV2 for inverting input data DIN, respectively, as shown therein; A NAND gate NAND1 for NAND combining the output signal of the inverter INV1 and the output control signal ODE; A NOA gate NOR1 for performing a NOA combination of the output signal of the inverter INV2 and the output control signal ODE input through the inverter INV3; An inverter INV4 for inverting the output signal of the inverter INV2; A NOA gate NOR2 for NOR combining the output signals of the inverters INV1, INV3, and INV4; The precharge driver 10 receives the output signals of the NAND gate NAND1, the NOA gate NOR1, and the NOR2, precharges the output terminal to a predetermined value, and then outputs the output data DOUT.

The precharge driver 10 is connected in series between the output terminal of the NAND gate NAND1 and the output terminal of the NOR gate NOR1, and the output signal of the NOR gate NOR2 and its noar gate NOR2 are connected to respective gates. An NMOS transistor NM1 and a PMOS transistor PM1 that are connected to and controlled by receiving an output signal from the inverter INV5; A PMOS transistor PM2 connected in series between a power supply voltage VCC and a ground voltage VSS and electrically controlled according to output signals of the NAND gate NAND1 and the NOR gate NOR1 applied to respective gates; An NMOS transistor NM2; A load capacitor C1 having one end connected in common to the contact point of the NMOS transistor NM1 and the PMOS transistor PM1 and the contact point of the PMOS transistor PM2 and the NMOS transistor NM2, and the other end thereof grounded. It consists of.

Hereinafter, the operation of the conventional output buffer circuit configured as described above will be described.

First, when the output control signal ODE is input at the low potential, the output signal of the NAND gate NAND1 is fixed at high potential regardless of the input signal DIN, and the low potential output control signal ODE is converted into an inverter ( The output signals of the NOA gates NOR1 and NOR2 input through INV3) output a low potential output signal regardless of the input eater DIN. As a result, the NMOS transistors NM1 and NM2 and the PMOS transistors PM1 and PM2 are both turned off, and the output data DOUT becomes a tri-state.

VCC정도의 전압 범위에서는 이를 반전한 인버터(INV1)의 출력신호는 저전위, 인버터(INV2)의 출력신호는 고전위가 되도록 인버터(INV1),(INV2)의 로직문턱전압이 다른 것을 사용한다.Next, FIG. 2 is an operation waveform diagram of FIG. 1, in which the output control signal ODE is applied at high potential, and the input data DIN is applied.

In the voltage range of about VCC, the output signal of the inverter INV1 which has been inverted is low potential, and the logic threshold voltages of the inverters INV1 and INV2 are different so that the output signal of the inverter INV2 becomes high potential.

VCC일 때만 고전위의 출력신호를 출력한다.In this way, the high-voltage output control signal ODE is input through the inverter INV3, and the NOA gate receives the output signal of the inverter INV1 and the output signal of the inverter INV2 through the inverter INV4. The output signal of NOR2 is the input data DIN

Only when VCC, high potential output signal is output.

VCC인 경우 노아게이트(NOR2)의 고전위 출력신호를 직접 및 인버터(INV5)를 통해 각각의 게이트에 입력받은 엔모스 트랜지스터(NM1) 및 피모스 트랜지스터(PM1)는 모두 도통된다. 또한 이때의 낸드게이트(NAND1)와 노아게이트(NOR1)의 출력은 약

VCC 정도의 전압범위를 갖게 되어 이는 출력단에 접속된 부하 캐패시터(C1)에 충전된다. 즉, 프레차지 된다.Then, the input data DIN

In the case of VCC, both the NMOS transistor NM1 and the PMOS transistor PM1 that receive the high potential output signal of the NOA gate NOR2 directly and through the inverter INV5 are connected to each other. At this time, the outputs of the NAND gate NAND1 and the NOR gate NOR1 are approximately

It has a voltage range of about VCC, which is charged to the load capacitor C1 connected to the output terminal. That is, precharged.

Then, when the input data DIN is input at high potential, the output signal of the NAND gate NAND1 is output at high potential, and the output signal of the NOR gate NOR1 is also output at high potential. At this time, the output signal of the NOA gate NOR2 is output at a low potential to turn off both the NMOS transistor NM1 and the PMOS transistor PM1.

In this operation, the PMOS transistor PM2 is turned off, the NMOS transistor NM2 is turned on, and the output data DOUT is output at a low potential.

Next, when the input data DIN is input at the low potential, the output signal of the NAND gate NAND combining NAND of inverted input data DIN through the high potential output control signal ODE and the inverter INV1 is The NOA gate NOR1, which is output at a low potential, receives the output control signal ODE through the inverter INV3, and receives the input data DIN through the inverter INV2, has its output signal also at a low potential. Is output.

The NOA gate NOR2 has a high potential output signal of the inverter INV1, a low potential output signal of the inverter INV3, and a low potential output signal of the inverter INV4 inverting the output signal of the inverter INV2. The output signal of the low potential is input in the same manner as the input of the high potential input data DIN.

Accordingly, the NMOS transistors NM1, NM2 and PMOS transistor PM1 are turned off, the PMOS transistor PM2 is turned on, and the output data DOUT is output at high potential.

VCC전위를 갖는 부분에서 출력단을 프레차지 시켜 입력데이터(DIN)가 고전위일 때와 저전위일 때 출력데이터(DOUT)의 억세스 속도를 증가시켰다.As described above, the conventional output buffer circuit has a potential between the high potential and the low potential of the input data DIN.

The output stage is precharged at the portion with the VCC potential to increase the access speed of the output data DOUT when the input data DIN is at a high potential and at a low potential.

VCC인 동안에만 특정한 값으로 출력단을 프레차지 함으로써, 그 프레차지를 위한 엔모스와 피모스 트랜지스터의 크기가 짧은 시간내에 일정전압을 출력하기 위해 증가하며 이에 따라 낸드게이트에 구비된 피모스 트랜지스터 등을 통해 전류패스가 형성되어 소비전력이 증가하며, 각 인버터의 로직 문턱전압을 다르게 변화시켜 제조해야 하고, 그 값에 대한 정확한 동작범위를 맞춰주기가 용이하지 않은 문제점이 있었다.However, in the conventional output buffer circuit as described above, the potential of the input data

By precharging the output stage to a specific value only during VCC, the size of the NMOS and PMOS transistors for the precharge increases to output a constant voltage within a short time. Through the current path is formed to increase the power consumption, the logic threshold voltage of each inverter to be manufactured by changing differently, there was a problem that it is not easy to match the exact operating range for the value.

It is an object of the present invention to reduce the power consumption and to provide an output buffer circuit which can easily precharge an output stage.

1 is a conventional output buffer circuit diagram.

2 is an operational waveform diagram of FIG.

Figure 3 is an output buffer circuit diagram of the present invention.

4 is an operational waveform diagram of FIG.

* Description of the symbols for the main parts of the drawings *

1: input unit 2: precharge control unit

3: precharge drive unit

The above object includes an input unit for outputting input data and inverted input data according to an output control signal; A precharge control unit which blocks the output signal of the input unit from being transmitted or transmits an output signal of the input unit according to the input of the precharge control signal; Output data is output when the output signal of the input unit is applied under the control of the precharge control unit, and when the output signal of the input unit is not applied, the output terminal is precharged according to the precharge control signal and the inverted precharge control signal. It consists of a precharge driving unit to block input data in the precharge section by using the precharge control signal, and after the precharge is completed, input and output the input data again to block a path where current leakage occurs. This is achieved by, when described in detail with reference to the accompanying drawings, the present invention as follows.

Fig. 3 is an output buffer circuit diagram of the present invention, and as shown therein, an input unit 1 for outputting input data DIN and inverted input data DIN according to the output control signal OED; A precharge control unit (2) which blocks the transmission of the output signal of the input unit (1) or transmits the output signal of the input unit (1) according to the input of the precharge control signal (PRE); When the output signal of the input unit 1 is applied under the control of the precharge control unit 2, the output data DOUT is output. There is no application of the output signal of the input unit 1, and the precharge control signal PRE is applied. ) And a precharge driver 3 for precharging the output stage according to the inverted precharge control signal PRE.

The input unit 1 includes a NAND gate NAND1 for NAND combining the output control signal ODE and the input data DIN; The output control signal (ODE) is input through the inverter INV1, and the input data DIN is input to the noah gate NOR for combining the noah.

The precharge control unit 2 includes an inverter INV2 for inverting the precharge control signal PRE; The precharge control signal PRE and the inverter INV2 are inputted and the output signals of the NAND gate NAND1 and the NOA gate NOR1 of the input unit 1 are transmitted when the precharge signal PRE is at low potential, respectively. It consists of a transmission gate (TG1), (TG2).

The precharge driver 3 is connected in series between the output terminals of the transmission gates TG1 and TG2 of the precharge control unit 2, and outputs the precharge control signal PRE and the output signal of the inverter INV2. An NMOS transistor NM1 and a PMOS transistor PM1 which are electrically connected to each other by being applied to each gate; It is connected in series between the power supply voltage VCC and the ground voltage VSS, and outputs the output signals of the NAND gate NAND1 and the NOR gate NOR1 applied through the transfer gates TG1 and TG2 to respective gates. A PMOS transistor PM2 and an NMOS transistor NM2 that are applied and controlled to be applied; A load capacitor C1 having one end connected in common to the contact point of the NMOS transistor NM1 and the PMOS transistor PM1 and the contact point of the PMOS transistor PM2 and the NMOS transistor NM2, and the other end being grounded. It is composed of

Hereinafter, the operation of the output buffer circuit of the present invention configured as described above will be described.

First, when the output control signal ODE and the precharge control signal PRE are applied at a low potential, the output signal of the NAND gate NAND1 is related to the input data DIN by this low potential output control signal ODE. The output signal of the high potential without output, and the low potential output control signal (ODE) is inverted through the inverter INV1 and the NOA gate NOR1 input to one input terminal is input data DIN input to the other end. Irrespective of the output signal of low potential.

At this time, the transfer gates TG1 and TG2 of the precharge control unit 2 are applied to the gates of the PMOS transistor PM2 and the NMOS transistor NM2 of the precharge driving unit 3 respectively, and both are turned off.

In addition, the precharge control signal PRE is applied at a low potential to turn off the NMOS transistor NM1 of the precharge driver 3, and the precharge control signal PRE is gated through the inverter INV2. The PMOS transistor PM1 applied to is turned off, and the output terminal becomes a tri-state.

VCC의 전위로 입력되는 구간에서, 프레차지 제어신호(PRE)를 고전위로 인가한다.Next, FIG. 4 is an operation waveform diagram of FIG. 3. As shown in FIG. 4, in the precharge operation of the output terminal, when the output control signal ODE is input at high potential, the input data DIN is input.

In the section inputted to the potential of the VCC, the precharge control signal PRE is applied at high potential.

That is, when the precharge control signal PRE is applied at high potential, the output signal of the NAND gate NAND1 and the output signal of the NOA gate NOR1 are blocked by the transmission gates TG1 and TG2. The MOS transistor PM2 and the NMOS transistor NM2 are turned off.

At this time, the NMOS transistor NM1 applying the precharge control signal PRE to the gate is turned on, and the PMOS transistor PM1 receiving the precharge control signal PRE to the gate through the inverter INV2. It is also turned on. In this operation, when the previous state of the output terminal is low potential, the drain side of the NMOS transistor NM1 becomes low potential, and the source of the PMOS transistor PM1 has a constant voltage value (VSS-Vtp: Vtp is a PMOS transistor). Precharge is started to the load capacitor C1, and when the voltage value of the drain side of the NMOS transistor NM1 and the source side of the PMOS transistor PM1 becomes equal, the precharge starts. The charge is complete.

After the precharge is completed, the precharge control signal PRE is input at the low potential when the input data DIN is input at the high potential or the low potential.

Accordingly, output signals of the NAND gate NAND1 and the NOA gate NOR1 are applied to the gates of the PMOS transistor PM2 and the NMOS transistor NM2 by the transfer gates TG1 and TG2. At this time, both the NMOS transistor NM1 and the PMOS transistor PM1 that receive the low-potential precharge control signal PRE directly through the respective gates and through the inverter INV2 are turned off.

In addition, the output signal of the NAND gate NAND1 outputs a low potential output signal when the input data DIN is input at a high potential, and the output data of the NOR gate NOR1 outputs a high potential output signal. That is, the NAND gate NAND1 inverts and outputs the input data DIN, and the NOR gate NOR1 outputs the same output signal as the input data DIN.

Then, the PMOS transistor PM2 and the NMOS transistor NM2, which have received the output signals of the NAND gate NAND1 and the NOR gate NOR1 as described above, are controlled on and off, respectively. The same output data DOUT as the input data DIN is output.

As described above, the output buffer circuit of the present invention adds a precharge control signal to block the input data transmission from the input unit during the precharge operation, and then precharges the output terminal using the precharge control signal, thereby easily outputting the output terminal. After precharging, outputting the output data increases the access speed of the output data and reduces the power consumption by eliminating the leakage factor of the current.

Claims (4)

An input unit for outputting input data and inverted input data according to the output control signal; A precharge control unit which blocks the output signal of the input unit from being transmitted or transmits an output signal of the input unit according to the input of the precharge control signal; Output data is output when the output signal of the input unit is applied under the control of the precharge control unit, and when the output signal of the input unit is not applied, the output terminal is precharged according to the precharge control signal and the inverted precharge control signal. An output buffer circuit comprising a precharge driving unit. 2. The apparatus of claim 1, wherein the input unit comprises: a NAND gate NAND combining an output control signal and input data; An output buffer circuit, comprising: a noar gate configured to receive the output control signal through a first inverter, and to receive the input data, and to combine the NOR. 2. The apparatus of claim 1, wherein the precharge control unit comprises: a second inverter for inverting the precharge control signal; The first and second transmission gates receiving the precharge control signal and the output signal of the second inverter and transmitting the output signals of the NAND gate and the NOA gate of the input unit when the precharge signal is low potential, respectively. Output buffer circuit characterized by. 2. The precharge driver of claim 1, wherein the precharge driver is connected in series between the output terminals of the first and second transfer gates of the precharge controller, and applies the precharge control signal and the output signal of the second inverter to the respective gates. A first NMOS transistor and a first PMOS transistor that are electrically connected and controlled; The second PMOS transistor and the second yen connected in series between a power supply voltage and a ground voltage and electrically controlled by receiving output signals of the NAND and NOA gates applied through the first and second transfer gates to respective gates. A MOS transistor; And a load capacitor having one end connected in common to the contact point of the first NMOS transistor and the first PMOS transistor and the contact point of the second PMOS transistor and the second NMOS transistor, and the other end being grounded. Output buffer circuit.

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