JPS5911993B2 - drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention conditions a circuit in anticipation of the application of a data signal, so that when the data signal is applied, the data propagates through the circuit and the 30 speed It concerns means for increasing the quality of life.

There are many problems in the design of high speed circuits, especially where the inputs of the circuit are connected to high impedance, low energy signal sources and the output of the circuit is required to drive a relatively large load. For example, in a storage device, a 35 drive circuit transmits a data signal from a signal source with an impedance of no more than a few picofarads (e.g., the output of a storage cell or sense amplifier) to a load of 50 picofarads or more in a few nanoseconds. Must. The devices that make up the output stage of a circuit pass through (sink) the relatively large current required to charge or discharge the load capacitance in a given amount of time.
It must be relatively large in order to be used (as an agent or as a source).

However, using a larger size device increases the capacitance associated with the device and increases the delay in the circuit. This poses various problems since the devices for configuring the input stage of a circuit are generally made small in order to reduce their input capacitance and ensure compatibility with the input signal source. That is, the input stage devices are too small to supply the current needed to rapidly charge and discharge the internal connections of the drive circuit. This presents the problem of having to meet the conflicting requirements of a) the need to have a large output device and a small input device, and b) the need to have circuitry that responds extremely quickly. Even when using large output devices, this
Yet another problem arises because it takes a very long time to drive the output of the circuit between two binary levels.

Thus, in a circuit according to the invention, the output of the circuit is driven between a high level and a low level prior to the application of said data signal, which drives the output either to a high level or to a low level when the data signal is applied. The battery is equipped with means for precharging to the level of .

A circuit embodying the invention includes a first pull-up transistor receiving a binary data input signal and having a conductive path connected between a first voltage terminal of the circuit and an output point. ing. The circuit also includes a second pulldown transistor having a conductive path connected between the output point and a second voltage terminal. ``Turn on one transistor and turn off the other transistor in response to a data input signal of one value, and turn off one transistor and turn on the other transistor in response to an input signal of the other value. First means are provided for: the circuit being of the form of receiving a second control signal indicating that a new data signal is to be applied thereto; the circuit according to the invention comprises: It comprises an improved precharging circuit responsive to a second control signal.

This precharging circuit uses a conduction path of the pull-up and pull-down transistors to precharge the output point to a voltage that is intermediate in value between the voltage supplied to the first terminal and the voltage supplied to the second terminal. control. The circuit has normally non-conducting means connected to the control electrodes of the pull-up and pull-down transistors, momentarily making both transistors conductive and thereby causing the second control signal to turn on when the second control signal is generated. The output point is charged to a value intermediate between the voltage applied to the first voltage terminal and the voltage applied to the second voltage terminal. Hereinafter, the present invention will be explained in detail with reference to the drawings. The actual devices suitable for use in practicing this invention are of the type known in the art as insulated gate field effect transistors (IGFETs).

For this reason, the circuit is illustrated and described as using such transistors below. However, this does not preclude the use of other suitable devices, and therefore the term transistor, which is used without limitation in the claims, is used in its general sense. In the drawings, enhancement mode IGFETs of P conductivity type are indicated by a specific reference number after P, and enhancement mode IGFETs of N conductivity type are indicated by a specific reference number after N.

The characteristics of IGFETs are well known and I do not think it is necessary to explain them in detail. However, in order to understand the following description more clearly, the relevant definitions and characteristics suitable for the present invention are listed below. 1. Each GFET has first and second electrodes defining opposite ends of a conductive path, and a control electrode (gate), the voltage applied to which determines the conductivity of the conductive path.

The first and second electrodes of the IGFET are called source and drain electrodes. In the P-type 1GFET, the source electrode is specified as the electrode to which a more positive (higher) voltage is applied between the first and second electrodes. In an N-type 1GFET, the source electrode is specified as the electrode to which a lower positive (lower) voltage is applied between the first and second electrodes. 2. Applied gate −
The source-to-source voltage (VGs) is what makes the transistor conductive, and the threshold voltage (VT) of the transistor
A conductive state occurs when the value is larger than a predetermined value defined as .

For a P-type enhancement IGFET to be conductive, its gate voltage VG is at least an amount T more negative than its source voltage Vs. N type enhancement IG
To make a FET conductive, its VG is lower than Vs.
It is more positive than T alone. 3. The IGFET becomes bidirectional in a sense when an energizing signal is applied to the control electrode, and the first
Current may flow in either direction through the conductive path defined by the second electrode and the second electrode.

In other words, the source and drain can be interchanged. In the following explanation, the ground potential or a potential close to it will be referred to as logic [0
] That is, it is defined as low logic, and +VDD or +V volts or a potential close to it is defined as logic [1], that is, high logic.

FIG. 1 shows a portion of a storage device in which address lines 201 are connected to change detection and decoder 203. FIG. Circuit 203 can take many different forms, but for purposes of describing the invention, it will be understood that a) the storage device is in read mode, and b) a particular storage array (chip) 200 is selected. Time T of waveform A in FIG. As shown in FIG. 3, when there is a change in the signal on address line 201 (from high to low or from low to high), lines 11 and 13 receive a first precharge as shown in waveforms B and C of FIG. 3, respectively. Pulse (PPl),
A second precharge pulse (PP2) is generated. PP1 and PP2 occur within 5 to 10 nanoseconds after the address signal change. Although PP1 and PP2 can occur simultaneously, for ease of explanation it is assumed that PP1 occurs at time t1 before PP2 occurs at time T2.
In any case, both PP1 and PP2 continue simultaneously between T2 and T4 as shown in FIG. PPl
, PP2 are shown as being generated by circuit 203, but the circuitry capable of generating these pulses could also be part of drive stage 5. PPl, PP2
Upon the occurrence of , the decoder portion of circuit 203 decodes the address signal change information and generates an enable signal that is applied to the corresponding word line 205 .

The word line conducts the enable signal to the gate electrode of pass transistor 207, which is connected to storage cell 20.
9 is read onto the bit line 211. Sense amplifier 213 connected on bit line 211 amplifies the signal on line 211 and produces an output signal labeled DATA on line 15. The new DATA signal generated in response to an address change becomes valid (i.e., the signal with the data bit read value) within 30 to 35 nanoseconds after the address change occurs, as shown in waveform D of Figure 3. ). That is, 30 to 35 nanoseconds is the time it takes for the decoder to determine which word line has been selected and then for the selected data to appear on line 15. The precharge pulses PPl, PP2 and the DATA signal are supplied to a quad-state output drive circuit 5. This drive circuit 5 generates a signal at its output 22 as quickly as possible (20 nanoseconds or less) in response to DATA when it becomes valid. The drive stage 5, shown in detail in FIG. 2, includes an output stage 10, a predictive precharge circuit 12, and a circuit 1 for controlling the precharge level and data flow.
It has 4. Output stage 10 has a pull-up transistor 20 whose source electrode is connected to power supply terminal 20 and whose drain electrode is connected to output terminal 22. The output stage 10 also has a pull-down transistor N1, whose drain electrode is connected to the output terminal 22 and whose source electrode is connected to the power supply terminal 24. Terminal 24 has a ground potential or O volts applied, and terminal 20 has a positive VDD volts applied to ground. Pl and Nl are output terminals 2
It is dimensionally large so as to be able to drive a relatively large load connected to CL, one example of which is capacitive and which is assumed to have a value of about 50 pf. circuit 1
2 consists of a pulse forming network consisting of transistors P2 and N2, an inverter 11, a NAND gate G1 and an inverter 12.

The source-drain path of transistor N2 is connected between the gate and drain of transistor P1, and
The source-drain path of is connected between the gate and drain of transistor N1. The output of the inverter 11 is connected to the gate of a transistor N2, the input of which is connected together to the transistor P2 and to the node to which the output signal V1 of the two-input NAND gate G1 is supplied. The PPl pulse, which acts as a prediction signal, is connected to the first input of gate G1 and to the input of inverter 12;
The output of is fed to the other input of gate G1. The combination of gate G1 and inverter 11 acts as a pulse shaping network as explained below. The inverter 12 is asymmetrical and its switching point is Vcc volts (
high level).

This is because inverter 12 is a complementary inverter structurally the same as 14 or 15 in FIG. 2, and a P-type transistor connected between the inverter output and VDD is connected between the inverter output and ground. This can be achieved by making the device considerably larger than the N-type transistor to which it is connected, while still making both transistors relatively small devices. Therefore, inverter 12 responds relatively slowly to positive going input signals and its output (high to low output) is therefore delayed in response to positive going inputs. Therefore, when PPI changes from low to high, one (1) input of gate G1 immediately goes high, and the other (2) input remains high until the output of inverter 12 switches from high to low. It is worshiped. Therefore, when PPl changes in the positive direction as shown in waveform B in FIG. 2, a negative direction pulse as shown in waveform E is generated at the output of gate G1. Gate G1
When the output signal 1 of 1 becomes negative, it indicates that the output 22 is charged to a predetermined level.

The negative going V1 signal is applied directly to the gate of transistor P2, making it conductive, and is also applied to the input of inverter 11, the positive going output appearing at its output is applied to the gate of transistor N2, making it conductive. To simplify the explanation, it is assumed that the impedance ZN2 of the conductive path of transistor N2 is equal to the impedance ZP2 of the conductive path of transistor P2 for the same value of VGS.

When transistors P2 and N2 become conductive, the gate and drain of transistor P1 and the gate and drain of transistor N1 are brought into a relatively low impedance state,
Transistors Nl and Pl are brought into conduction. The gate electrodes are connected to output terminals 2 through transistors N2 and P2, respectively.
The transistors Pl and Nl connected to
mode, and operates to drive the output voltage VO to a voltage level intermediate between VDD and O volts. The charge level of the output is determined by the impedance of the conductive path of the transistors Pl, Nl, P2, N2 and the inverter 14 for supplying the drive signal to the gate electrodes of the transistors Pl, Nl.
, 15 states. The exact level at which VO is charged depends on which of three possible conditions applies.

Condition 1: Transistors P2 and N2 become conductive as transistors N4 and N5 become conductive.

This condition is, for example, when the DATA signal is low level and the PP2
Exists when not supplied. Because transistor N4 is a much larger device than transistor N5, the gate of transistor P1 is maintained very close to O volts as transistor N2 conducts current from its output to the drain of transistor N4. Transistors P2 and N5 operate as a voltage divider connected between the output and ground, while generating the gate voltage of transistor N1 at their junction. As a result, the VGS of transistor P1 will be significantly greater than the VGS of transistor N1. Transistor P1 conducts more strongly than N1 and VO is pulled down from DO, but not to VDD/2. The output signal for this condition is shown by dotted line 1 of waveform F in FIG. Condition 2: Transistors N2 and P2 are conductive due to conduction of transistors P4 and P5.

This condition is, for example, when the DATA signal is high level and the PP
Exists when 2 is not supplied. Since transistor P5 is significantly larger than P4, the voltage for conduction supplied to transistor N1 is greater than the voltage for conduction supplied to transistor P1. As a result, transistor N1 conducts more strongly than P1. As a result, the potential of VO is reduced to VDD by the conduction of transistor P1.
/2, but not to that level. This condition is shown by dotted line 1 of waveform F in FIG. ．． Condition 3: Transistors P2 and N2 are conductive, and transistor P
4. N5 is also conductive.

This condition appears when PP2 is present (going straight). Under this signal condition, the output is driven towards VDD/2 as described below. equal value VGS
In contrast, it is assumed that the impedance ZPI of the source-drain circuit of the transistor P1 is equal to the impedance ZNI of the source-drain circuit of the transistor N1.

Transistors P1 and N1 therefore operate to drive the output voltage VO at terminal 22 toward VDD/2. It may be easier to understand charging toward VDD/2 by using an extreme example.

Therefore, assume that VO is initially at o volts and transistors P2 and N2 are conducting. Depending on the dimensions of the various transistors, transistor P1 with its source at the potential of VDD and its gate connected to o volts at VO through transistor N2 will conduct, even though VO will also cause transistor N1 to conduct. Pull the output towards VDD until it is fully positive. Since ZNI and ZPI operate exactly like a voltage divider network, transistor N
1 conducts, VO continues to rise, but the limit of rise is V
It is DD/2. Transistor N2 (and P2) is connected as a source follower, ensuring that transistors N2 and P1 initially conduct rapidly as the conductivity becomes progressively smaller. Initially, VO is 0 volts, and V from inverter 1 to the gate.
Transistor N2, supplied with DD, is strongly conducting, while transistor P1, whose gate and source are at o volts, is non-conducting. However, as VO rises towards VDD, transistor N2 conducts weakly and P2 conducts strongly, while current is supplied by inverters 14 and 15 until equilibrium is reached. Therefore, if VO was at o volts prior to conduction of transistors P1 and N1, VO is pulled toward VDD/2 as shown in waveform F of FIG. On the other hand, VO is the transistor P1
and was at VDD before conduction of N1, then it is VDD
It will be lowered towards DD/2. Therefore, due to the source follower operation of transistors N2 and P2, if a high level is present prior to the conduction of transistors P1 and N1, VO will be VDD/2 (ZNI = ZPI, ZN2
If a low level is present prior to conduction of transistors P1 and N1, VO is charged to a level close to VDD/2. The level at which the output is precharged can also be other than close to VDT,/2 depending on the design of transistors P1 and N1. However, for ease of explanation, VDD/2 is chosen as the output logic level transition point. It is therefore clear that each time an address change occurs, a prediction pulse PPI is generated, precharging the output of the circuit 5 towards a voltage level close to VDD/2 prior to the arrival of the new data signal.

This makes it possible to speed up the response to the propagation of the DATA signal via the output circuit. Output to VDD/2
Although precharging to 100% provides fast response to normal data level changes, it is not necessary to approach this level too closely for the present invention to be effective.

First, if the data does not change, the output will be the intermediate value V
Not very close to DD/2 level, but V
The advantage is that it remains at a reasonable voltage limit away from DD/2. Second, dynamic power consumption is reduced if the output voltage does not change and the device in the shut-off state does not conduct as strongly. Finally, the conduction impedance of precharged transistors N2 and P2 is:
If the precharge pulse PPI still maintains transistors N2 and P2 in a strong state, the data change signal is still able to propagate through inverters 14 and 15 to change the output level. The timing of the precharge pulse PPI is the shortest critical value. Even in the absence of the second precharge pulse PP2, an overall speed advantage is obtained as long as the output level is charged towards an intermediate level by the predicted precharge pulse PPI. The circuit 14 includes a first signal control line 14a for supplying signals taken from lines 13 and 15 to the control electrode of transistor P1, and a first signal control line 14a for supplying signals taken from lines 13 and 15 to the control electrode of transistor N1. A second signal control circuit 14b is provided for controlling the signal.

Circuit 14a has a two-input canor gate G2, the output signal 2 of which is applied to the input of inverter 14, and the output signal V4 of inverter 14 is applied to the gate electrode of transistor P1. Electrical path 14b has an inverter 13 whose output signal Vl3 is fed to one input of a two-input NAND gate G3, whose output signal V3 is fed to the input of an inverter 15 whose output signal V5 is supplied to the gate electrode of transistor N1. DATA
The signal is fed to one (1) input of gates G2 and G3, while PP2, present on line 13, is fed to the second (2) input of gate G2 and to the input of inverter 13. Signal path 14a ensures that the signal attempting to turn on transistor P1 passes through gate G2 and inverter 14 very quickly, even at the expense of the signal attempting to turn off transistor P1 being propagated more slowly. Preferably, it is designed to be propagated.
Similarly, signal path 14b is designed such that the signal that turns on transistor N1 is propagated very quickly through gate G3 and inverter 15, while the signal that turns off transistor N1 is propagated more slowly. is desirable. This includes gates G2, G3, inverter 14,
This is achieved by offsetting (ie making asymmetrical) the 15 switching points. Inverter 14 and 1
5 is a complementary inverter, each inverter has VDD
It consists of a P-conductivity type GFET and an N-conductivity type IGFET, each of which has a conductive path connected in series between the GFET and the ground.

The gate electrodes of the two IGFETs are commonly connected to the input of the inverter, and the drain electrodes of the two IGFETs are commonly connected to the output of the inverter.

The shape of the transmission curve of a complementary inverter, and therefore the switching point, is
Among other things, it depends on the characteristics and impedances of the N-type and P-type transistors that make up the inverter.

The impedance Z of each transistor is a function of the ratio of its channel length L to channel width W [Z-f(L/W)
]. Therefore, the switching point of the inverter is adjusted by appropriately selecting and designing the width-to-length ratio (W/L) of the IGFETs that make up the inverter. However, this assumes that other parameters of the IGFET are the same, such as threshold voltage, oxide thickness, doping level, etc. By making transistor P4 smaller than N4, the switching (or tripping) point of inverter 14 is set close to ground (but higher than the VT of transistor N4).

Therefore, the positive going signal at the input of inverter 4 is V
4 goes low quickly, while a negative going signal from VDD to ground with the same slope takes relatively longer to reach the switching point. Also, once the switching point is reached, transistor P4, a small device (i.e. high impedance), charges its output capacitor rather than discharging the capacitance of transistor N4, a large device, to ground. It also takes a long time. Therefore,
4 tends to a high level relatively slowly, and in contrast, it tends to a low level rapidly. Regarding inverter 15,
It is desirable that transistor P5 be made larger than N5.

This sets the switching point of inverter 15 close to VDD so that 5 quickly goes high and slowly goes low, similar to what was described for inverter 14. Regarding gates G2 and G3, gate G2
consists of two P-type transistors connected in series between VDD and the gate output, and two N-type transistors connected in parallel between the gate output and ground.

As shown in FIG. 2, the P-type transistor of gate G2 is larger than the N-type transistor. Therefore, the switching point of gate G2 is set near VDD so that its output goes high quickly and goes low slowly. Gate G3 is a two-input complementary consisting of two P-type transistors connected in parallel between VDD and the gate output and two N-type transistors connected in series between the gate output and ground. Assume that it consists of NAND gates.

As shown in FIG. 2, the N-type transistor with gate G3 has P
It is larger than a type transistor. The switching point of gate G3 is therefore set close to ground potential, so that the output V3 slowly goes to a low level and quickly goes to a high level. Since the signal propagation path of the signal path shown by blocks 14a and 14b in FIG. This makes it possible to further improve the responsiveness of the output.

This approach is most effective when it is known exactly when new data arrives, such as in a latched data transmission system. Alternatively, the circuit of FIG. 4, which provides a precharge pulse PPl to inverters 14 and 15, overlaps the data pulse with PPl on, and also holds the inputs and outputs of inverters 14 and 5 at an intermediate level. It is also extremely advantageous when trying to propagate data through it. Regarding the operation of this speed-up circuit of PP2, as shown in waveforms C and B in FIG.
The description will be made assuming that PP2 changes in the positive direction at time T2 immediately after Pl changes in the positive direction. As mentioned above, P.P.
After l goes high, 1 goes low, transistors N2 and P2 become conductive (and remain conductive), and transistors N1 and P1 also become conductive, reducing VO to a suitable value close to VDD/2. Drive towards intermediate level.

When PP2 becomes positive, the output of NOR gate G2 is at time T
As shown by waveform G from 2 to T3, the output of the inverter 14 is driven toward a low level, and the output of the inverter 14 is driven toward a high level.

However, as described above, transistor P4 slowly becomes conductive, and V4 slowly rises toward VDD (waveform 1 after time T3). This ensures that transistor P
1 can reliably increase VO toward VDD/2. As a result, as PP2 goes positive, the output of the inverter 3 goes to a low level, as shown in the waveform H for times T2 and T3, and as described above, the output of the inverter 3 goes to VD.
The voltage is slowly raised toward D, and the transistor N5 is slowly turned on.

This allows transistor N1 to reliably reduce VO towards VDD/2 before the effect of transistor N5 is sensed. The conduction of transistor P4 causes V4 and thus the voltage VGPl at the gate of transistor P1.

On the other hand, conduction of transistor N5 lowers V5, and thus the heavy pressure VGNl at the gate of transistor N1, to below VDD/2. This reduces the degree of conduction through transistors P1 and N1. However, it should be noted that transistors P1 and N1 are already charging VO to a value at or near VDD/2. Furthermore, transistor P4
and conduction of N5, transistors P1 and N1
The conductivity of VO decreases, but the operation of driving VO toward VDD/2 is maintained. Transistor P4 is connected between VDD and ground as transistors P4 and N5 become conductive.
, N2, P2 and N5 are formed.

The conduction path of transistor P4 is between VDD and transistor P1.
Provide impedance between the gate and the gate. The conductive path of transistor N2 also provides an impedance between the gate of transistor P1 and output 22. Furthermore, the conductive path of transistor P2 provides an impedance between the output 22 and the gate of transistor N1, and the conductive path of transistor P2 provides an impedance between the output 22 and the gate of transistor N1.
The conductive path provides an impedance between the gate of N1 and ground. The relative dimensions of the transistors P4, N5, P2, and N2 are such that when all four transistors are conductive, the impedance ZP4 of the conduction path of the transistor P4 is approximately equal to the impedance ZN5 of the conduction path of the transistor N5, and Assume that the impedance of is such that it is significantly larger than ZN2, which is approximately equal to ZP2.

Since ZP4 and ZN have relatively high impedance,
The conductive path made up of transistors P4, N2, P2, and N5 has high impedance and low power consumption. ZP4
Since the impedance of +ZN2 is approximately equal to the impedance of ZP2+ZN5, o continues to be driven towards VDD/2 or remains at VOO/2. Further, due to the action of the single drive stage, VO becomes V as shown after time T3 in waveforms F, I and J of FIG. While changing toward D/2, V4, which is the voltage (GPl) supplied to the gate of transistor P1, is driven (or held) to a voltage slightly higher than DO/2 and is supplied to the gate of transistor N1. The voltage V5 that becomes the voltage is driven (or held) to a voltage slightly lower than VDD/2. As a result, in response to PPl going high at time t1, transistors P1 and N1 become conductive, causing VO to D
Drive rapidly towards D/2.

Then, in response to PP2 going high at time T2, inverters 14 and 15 switch transistors P1 and N1
is driven in the direction of decreasing the conduction level of VO
continues to change reliably toward VDD/2, and further holds the gates of transistors P1 and N1 at a potential close to VDD/2. Reducing the conductivity of transistors P1 and N1 facilitates turning off unselected devices when a data signal is applied. Similarly, by keeping the potential of VGPl slightly higher than VDD/2, it is easier to turn it off or on. Also, by keeping GNl slightly lower than VDD/2, it is easier to turn it off or on. Next, the operation of the circuit when DATA becomes valid at time T4 will be described.

When DATA becomes valid and becomes high level, V1 becomes high level (or just becomes high level)
, PP2 go low (or just go low).

When V1 goes high, transistors P2 and N2
is in a cut-off state. Depending on the capacity of each connection point, DATA
Just before T4 goes high, the voltages in each mode are maintained as described above and as shown in FIG. 3 for T4. When DATA goes high, the output of G3, which is asymmetrical so that it responds quickly to positive signals, quickly goes low.

The inverter 15, which is asymmetrical to respond quickly to negative-going signals, switches rapidly with transistor P5 conducting strongly, with VGNl slightly lower than VDD/2. Drive towards D. Since VGPl is driven toward VDD by transistor P4, transistor P1 becomes conductive. Therefore,
Transistor N1, which becomes strongly conductive, rapidly discharges terminal 22 towards ground potential. When DATA is high, the output of gate G2 remains low (PP
2), the output of inverter 14 remains at a high level.

Note that in this case there is no delay due to the need to switch any element. Transistor N2 turns off, transistor P4
charges the gate of transistor P1, which was at a level slightly higher than VDO/2, toward DD, and quickly shuts off this transistor P1. Therefore, the transistors Nl, P2 and Pl, N2 that precharged the output 22, the transistors P4 and N5 that precharged the gates of transistors P1 and N1, and the asymmetrical current path move the data signal through the circuit very quickly. can be propagated,
It is also possible to rapidly generate a stable output signal.

The waveform F shows how fast VO is driven to steady state compared to a conventional circuit that does not precharge the output and/or the connection points in the circuit and/or does not include a desymmetrizing signal propagation path.
It is shown in The operation of the circuit when new DATA is low is a mirror image or complement of the operation described above.

If PP2 is low and DATA is low, 2 will be high and 4 will be low. Gate G2 and inverter 1 are configured to respond quickly to these signals.
Since 4 is asymmetric and VO is charged to the level mentioned above, transistor P1 becomes conductive very quickly, driving VO 1 towards VDD. the result,
With DATA at a low level, the output of V3 is maintained at a high level without unnecessarily dissipating power, and transistor N5 quickly and easily closes the gate of transistor N1 by blocking transistor P2. By pulling it down to ground potential, it is quickly turned off, and transistor P1 can then pull VO up to VDD. PP
Under steady state conditions where V1 is low and V1 is low, the value of the DATA signal on line 15 determines whether transistor P1 or N1 is rendered conductive.

This specifies the two binary output states of circuit 5. PP2
When is at a high level, ie when a positive signal is applied to line 13, and when V1 is at a low level, transistors P1 and N1 are cut off regardless of the value of the signal on line 15.

This means that the output is virtually floating,
Not tightly coupled to any potential point, O volts and V
Since it can take almost any value between DD volts,
Set the third (tri-state) state. Finally line 11
When there is a low to high change in , transistors P2 and N2 conduct and the output 22 is charged to a value intermediate between VDD and o volts, whether PP2 is high or low.

This sets the fourth (quad-state) state on the output. Thus, predictive charging circuit 12 connects pull-up transistor P1 and pull-down transistor of a tri-state circuit.
Both transistors N1 are turned on instantly, and the tri-
The output of the state can be viewed as a circuit for presetting the output to a voltage level intermediate between the high and low voltages at which the output is driven when data is present. As modified and shown in FIG. 4, the circuit of FIG. 2 can also be operated so that the output is charged near the midpoint.

This is because when it is possible to know exactly when the 0ATA signal is applied to the circuit with respect to the occurrence of the precharge pulse,
This is the preferred mode of operation of the circuit. However, DAT
When it is not possible to know exactly when the A signal is applied,
No PP2 pulse or very short P
Preferably, it operates with P2 pulses.

The PPI pulse still precharges the output and gate potentials of transistors P1 and N1 somewhat. The degree of precharging is P
Although it is not the same as when P2 exists, the effects of the present invention can be sufficiently obtained. An important factor in the extent to which the output and the gates of transistors P1 and N1 are charged depends on the impedance ratio of transistors N2 and P2 to each other and to the impedances of the transistors in inverters 4 and 15. Of course, these can be varied to set the precharge range to the desired range. The circuit of FIG. 2 can be modified as shown in FIG. The conductive path of transistor P4l is connected between the input and output of inverter E4, and the conductive path of transistor N5l
A conductive path is connected between the input and output of the inverter 15. The gate electrode of transistor P4l is connected to the output of G1, and the gate electrode of transistor N5l is connected to the output of inverter E1. As a result, when V1 goes low, transistors P4l and N5l are conductive and inverters 4 and 15 are driven towards their toggle or switching point, thereby causing the incoming DATA signal to Responsiveness will be extremely fast. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a portion of a storage device embodying the present invention, and Fig. 2 is a block diagram of a portion of a drive circuit embodying the invention, and a schematic circuit diagram of the other portions. A diagram shown in the form of
FIG. 3 is a diagram showing waveforms related to each point in FIG. 2, and FIG. 4 is a diagram showing another embodiment of the drive circuit of the present invention.

5... Drive circuit, 12... Precharging circuit, 14... First means, 14a... First propagation path, 14b... ...Second propagation path, 20.
...First voltage terminal, 22...Output point,
24...second voltage terminal, P1...pull transistor, N11...pull transistor, N2...transistor (means normally in a non-conducting state) ), P2...transistor (means normally in a non-conducting state), 1...inverter (means normally in a non-conducting state).

Claims (1)

[Claims] 1. A drive circuit to which a binary data input signal is supplied, comprising: a first pull-up transistor with a conductive path connected between a first voltage terminal and an output point; a second pull-down transistor connected between a second voltage terminal and a second pull-down transistor, and one of the first and second transistors is rendered conductive in response to the input signal having one value; a first means for turning off the other transistor and turning on the other transistor in response to the input signal having the other value; and applying new data to the circuit. and second means including a precharging circuit responsive to a control signal indicating that a signal is to be applied, the precharging circuit controlling the conductivity of the conductive path of the transistor to cause the output point to be connected to the output point. The precharging circuit precharges the control electrodes of the first and second transistors to a voltage having an intermediate value between the voltages supplied to the first voltage terminal and the second voltage terminal. is connected to, when the control signal is supplied, momentarily makes both the first and second transistors conductive, thereby causing the output point to be connected to the first voltage terminal and the second voltage terminal. and third means, normally non-conducting, for charging to a voltage having a value intermediate the voltage applied to the first and second separate propagation paths. one end of each of these propagation paths is supplied with the data input signal, the other end of the first propagation path is connected to the control electrode of the first pull-up transistor, The other end of the second propagation path is connected to the control electrode of the second pull-down transistor, and the first propagation path quickly transmits the turn-on signal of the one value to the first pull-down transistor. and wherein the second propagation path is operative to rapidly transmit the turn-on signal of the other value to the second pull-down transistor.