CN100423132C - Shift register - Google Patents
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- CN100423132C CN100423132C CNB2006100940027A CN200610094002A CN100423132C CN 100423132 C CN100423132 C CN 100423132C CN B2006100940027 A CNB2006100940027 A CN B2006100940027A CN 200610094002 A CN200610094002 A CN 200610094002A CN 100423132 C CN100423132 C CN 100423132C
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Abstract
The present invention relates to a shift register which comprises a shift register circuit unit and a buffer, wherein the buffer is coupled with the output end of the shift register circuit unit. Therefore, the overlapping part of two adjacent output signals of the shift register circuit unit is reduced by delaying the output signal of the shift register circuit unit.
Description
Technical field
The present invention relates to a kind of shift register circuit, particularly relate to the driving circuit of a LCD.
Background technology
Figure 1 shows that the circuit structure of a traditional shift register circuit, it is disclosed in the U.S. Pat 6834095, only is the shift register circuit of single unit shown in it, and a plurality of shift register circuits unit can constitute a complete shift register circuit after being connected in series together.And according to circuit structure shown in Figure 1, (N-1) out is the prime signal of prime shift register circuit output, and (N+1) out be a back grade of signal of back level shift register circuit output, (N) the out output signal of shift register circuit for this reason then.
Figure 2 shows that three output signal skeleton diagrams that couple the shift register circuit output terminal, overlap each other together, the then enlarged drawing of overlapping region for this reason shown in Figure 3 by the output signal subregion that can find out two adjacent shift register circuits among the figure.Enlarged drawing according to this, the output signal of adjacent shift register circuit overlaps each other approximately in 11 volts, therefore, use the formed output signal of this kind shift register circuit to drive a threshold voltage (threshold voltage) respectively when a LCD and be about 2 volts transistor, use when a data-signal taken a sample, owing to couple the transistor of adjacent shift register circuit, can open simultaneously in the output signal overlapping region, the existing picture of this kind may cause missampling.
Summary of the invention
Therefore, fundamental purpose of the present invention provides a kind of circuit structure, and it can minimize the overlapping voltage of adjacent shift register circuit element output signal.
A purpose of the present invention provides a kind of circuit structure, and it can increase the resolution of sampling.
In view of above-mentioned purpose, the present invention proposes a kind of shift-register circuit structure, comprises a shift register circuit unit and an impact damper.Wherein the shift register circuit unit is made up of two inverter circuits and four transistors.Impact damper then is made up of four transistors.
According to an embodiment, be to form these transistors with NMOS.
According to an embodiment, two inverter circuits are formed by two transistors that are connected in series.
According to another embodiment, the present invention proposes a kind of shift-register circuit structure, driven by one first signal, a secondary signal, one the 3rd signal and one the 4th signal, this shift register comprises: a first transistor, its gate terminal couples secondary signal, and first source/drain electrode end is coupled to the 3rd signal; One transistor seconds, its first source/drain electrode end end coupled with first signal, grid then is connected with the second source/drain electrode end of the first transistor; One the 3rd transistor, its first source/drain electrode end couple the second source/drain electrode end of transistor seconds, and its second source/drain electrode end is coupled to an electronegative potential; One the 4th transistor, its first source/drain electrode end are coupled to the second source/drain electrode end of transistor seconds, and its second source/drain electrode end is coupled to electronegative potential, and its gate terminal is coupled to the 4th signal; One first phase inverter, its input end couples the 3rd signal; One second phase inverter, its input end couple the 4th transistorized first source/drain electrode end, and its output terminal couples the 3rd transistorized gate terminal; One the 5th transistor, its first source/drain electrode end couples the output terminal of first phase inverter, and its gate terminal is coupled to the second source/drain electrode end of the first transistor; One the 6th transistor, its grid and first source/drain electrode end serial connection also couples the 5th transistorized second source/drain electrode end; One the 7th transistor, its first source/drain electrode end couple the 5th transistorized second source/drain electrode end, and its second source/drain electrode end couples electronegative potential, and its gate terminal is coupled to the output terminal of second phase inverter; And one the 8th transistor, its first source/drain electrode end couples the 6th transistorized second source/drain electrode end, and its second source/drain electrode end is coupled to electronegative potential, and its gate terminal is coupled to the output terminal of second phase inverter.
According to an embodiment, wherein first signal is a clock signal, and secondary signal is an inversion clock signal, and the 3rd signal is the signal that last serial connection level shift register is exported, and the 4th signal is back one a serial connection level shift register institute output signal.
According to an embodiment, two inverter circuits are formed by two transistors that are connected in series.
According to an embodiment, comprise that also at least one delay circuit is coupled to the 5th and the 6th transistor.
Because the present invention is by coupling a buffer circuit in the shift register circuit unit, make the mistiming between two adjacent shift register circuit element output signals strengthen, use the overlapping region that minimizes adjacent shift register circuit element output signal, avoid when carrying out data sampling, open the transistor that couples simultaneously, so it can increase the resolution of sampling.
Description of drawings
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, accompanying drawings is as follows.
Figure 1 shows that the circuit structure of traditional shift register circuit unit.
Figure 2 shows that three output signal skeleton diagrams that couple the shift register circuit output terminal.
Shown in Figure 3 then is the enlarged drawing of output signal overlapping region.
Figure 4 shows that the shift register circuit skeleton diagram of preferred embodiment according to the present invention.
Figure 5 shows that circuit structure according to shift register circuit of the present invention unit.
Figure 6 shows that the sequential chart of operation shift register circuit of the present invention.
Figure 7 shows that three of the present invention couple shift register circuit element output signal skeleton diagram.
Figure 8 shows that the enlarged drawing of output signal overlapping region.
Fig. 9 and the delay circuit synoptic diagram that Figure 10 shows that according to other embodiments of the invention.
The reference numeral explanation
500 shift registers
501 shift register circuit unit
502 impact dampers
5001 and 5002 inverter circuits
5003,5004,5005 and 5006 end points
Q1, Q2, Q 3, Q4, Q5, Q6, Q7, Q8, Q9 and Q10 transistor
Embodiment
Shift register of the present invention comprises a shift register circuit unit and an impact damper.Impact damper is coupled in the output of shift register circuit unit, uses the output signal that postpones the shift register circuit unit, reduces the lap of adjacent two shift register circuit element output signals.Consult the shift register circuit skeleton diagram that Figure 4 shows that the preferred embodiment according to the present invention, wherein the output of each shift register circuit unit all couples an impact damper.For example, the output of shift register circuit unit N couples impact damper N, and output signal (N) out feedbacks to shift register circuit unit N-1, is sent to shift register circuit unit N+1 simultaneously, and as input signal, the rest may be inferred in each shift register circuit unit.
Consult the detailed circuit diagram that Figure 5 shows that according to shift register of the present invention, wherein shift register 500 comprises shift register circuit unit 501 and impact damper 502.Shift register circuit unit 501 comprises two inverter circuits 5001 and 5002, and four transistor Q1, Q2, Q3 and Q4.And impact damper 502 then comprises four transistor Q5, Q6, Q7, Q8, Q9 and Q10.In this most preferred embodiment, be to form this ten transistors wherein with NMOS.In other embodiment, can also be formed by PMOS.Two inverter circuits 5001 and 5002 in the present embodiment are formed by two transistors that are connected in series in addition, and a transistorized grid wherein is with source/drain electrode end serial connection.
Shift register circuit of the present invention unit 501 is controlled by clock signal C K, inversion clock signal XCK, prime signal (N-1) out and back level signal (N+1) out.Wherein the grid of transistor Q1 is coupled to inversion clock signal XCK, and wherein first source/drain electrode is coupled to prime signal (N-1) out, and second source/drain electrode then couples with the grid of transistor Q2 and transistor Q5, uses switching transistor Q2 and transistor Q5.First source/drain electrode of transistor Q2 is coupled to clock signal C K, and second source/drain electrode then couples with first source/drain electrode of transistor Q3 and Q4.The grid of transistor Q3 is coupled to the output terminal of inverter circuit 5002, couples the grid of transistor Q7, Q8 in the impact damper 502 and Q10 simultaneously, uses these transistorized switchings of control, and second source/drain electrode then is coupled to an electronegative potential VSS.The grid of transistor Q4 is controlled by back level signal (N+1) out, and first source/drain electrode is coupled to the input end of inverter circuit 5002, and second source/drain electrode then is coupled to an electronegative potential VSS.Inverter circuit 5001 receives prime signal (N-1) out in addition, it is sent to first source/drain electrode of transistor Q5 after anti-phase.
Figure 6 shows that the sequential chart of operation shift register circuit of the present invention.Please consult Fig. 5 and Fig. 6 simultaneously.When period T 1, anticlockwise signal XCK is a high level signal, and clock signal C K is a low level signal, the anticlockwise signal XCK meeting turn-on transistor Q1 of high level, make high level prime signal (N-1) out that previous stage register circuit unit N-1 is exported, make end points 5003 also be high level state via the first transistor Q1, and conducting transistor seconds Q2 and the 5th transistor Q5.Low level clock signal C K then can make end points 5005 present low level state via transistor Q2, and this low level state signal can be sent to phase inverter 5002, makes exit point 5006 present high level state after it is anti-phase.On the other hand, high level prime signal (N-1) out can be sent to phase inverter 5001, makes end points 5004 present low level state after it is anti-phase.Wherein the high level state signal of end points 5006 transistor Q7, Q8 and the Q10 that can switch impact damper 502 makes its conducting, thereby signal at the corresponding levels (N) out of output low level.On the other hand, level signal (N+1) out after the low level that shift register circuit unit N+1 is exported, the grid of feedbacking back the 4th transistor Q4 because it is a low level state, therefore is in closing state in cycle t1 the 4th transistor Q4.
When period T 2, anticlockwise signal XCK is a low level signal, and clock signal C K is a high level signal, low level anticlockwise signal XCK meeting switching transistor Q1, make it be in closed condition, and make end points 5003 present quick condition (floating state), the end points 5003 conducting transistor seconds Q2 and the 5th transistor Q5 of this quick condition.The clock signal C K of high level then can make end points 5005 present high level state via transistor Q2, this high level state signal can be by the coupling of transistor Q2 stray capacitance C, and draw high the level of end points 5003 once more, the high level state signal of end points 5005 in addition, can be sent to phase inverter 5002, after it is anti-phase, make exit point 5006 present low level state.On the other hand, low level prime signal (N-1) out can be sent to phase inverter 5001, after it is anti-phase, make end points 5004 present high level state, this high level state signal can be via transistor Q5, make the transistor Q6 conducting of grid and source/drain electrode serial connection, and make its conducting via the transistor Q6 switching transistor Q9 of conducting.At this moment, a noble potential VDD exports via transistor Q9 becomes the signal at the corresponding levels of high level (N) out.On the other hand, low level prime signal (N+1) out that shift register circuit unit N+1 is exported, the grid of feedbacking back the 4th transistor Q4 because it is a low level state, therefore is in closing state in cycle t2 the 4th transistor Q4.
When period T 3, anticlockwise signal XCK is the high-low level signal, and clock signal C K is a low level signal, and prime signal (N-1) out is a low level signal, and then level signal (N+1) out is a high level signal.The anticlockwise signal XCK meeting turn-on transistor Q1 of high level, make end points 5003 be coupled to low level prime signal (N-1) out via the first transistor Q1, and presenting low level state, this low level signal makes transistor seconds Q2 and the 5th transistor Q5 close.Low level prime signal (N-1) out is sent to phase inverter 5001 in addition, makes end points 5004 present high level state after it is anti-phase.And back level signal (N+1) the out meeting turn-on transistor Q4 of high level, make end points 5005 be coupled to an electronegative potential VSS via transistor Q4, and present low level state, this low level state signal can be sent to phase inverter 5002, after it is anti-phase, make exit point 5006 present high level state, transistor Q7, Q8 and Q10 that this high level state signal switches impact damper 502 make its conducting, thereby signal at the corresponding levels (N) out of output low level.
Because signal at the corresponding levels of the present invention (N) out is sent out after via an impact damper 502, be not directly to send by shift register circuit unit 501, promptly allow signal at the corresponding levels (N) out postpone time output by an impact damper 502, the output time of using between increasing and prime signal (N+1) out is poor, the overlapping region that reduces adjacent shift register circuit element output signal.This signal at the corresponding levels (N) out can be sent to shift register circuit unit N+1 in addition, becomes the prime signal of its input, is sent to shift register circuit unit N-1 simultaneously, becomes the back level signal of its input.
Consult and Figure 7 shows that three of the present invention couple shift register circuit element output signal skeleton diagram.Shown in Figure 8 then is the enlarged drawing of output signal overlapping region.Compare with Fig. 2, the present invention can significantly reduce the overlapping region of two adjacent shift register circuit element output signals.And according to enlarged drawing, output signal according to adjacent shift register circuit of the present invention unit overlaps each other approximately in 1.5 volts, therefore, drive threshold voltage (threshold voltage) is about 2 volts transistor when a LCD uses the formed output signal of this kind shift register circuit to come respectively, use when a data-signal taken a sample, because overlapping voltage is at 1.5 volts, therefore couple the transistor of adjacent shift register circuit, can not open simultaneously in the output signal overlapping region, can avoid missampling.
In sum, the present invention is by coupling a buffer circuit in the shift register circuit unit, make the mistiming between two adjacent shift register circuit element output signals strengthen, use the overlapping region that minimizes adjacent shift register circuit element output signal, avoid when carrying out data sampling, open the transistor that couples simultaneously, so it can increase the resolution of sampling.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can be used for a variety of modifications and variations under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (14)
1. a shift register is driven by one first signal, a secondary signal, one the 3rd signal and one the 4th signal, and this shift register comprises at least:
One the first transistor, the gate terminal of this first transistor couples this secondary signal, and first source of this first transistor/drain electrode end is coupled to the 3rd signal;
One transistor seconds, first source of this transistor seconds/drain electrode end couple this first signal, and the gate terminal of this transistor seconds is coupled to second source of this first transistor/drain electrode end;
One the 3rd transistor, the 3rd transistorized first source/drain electrode end couples the second source/drain electrode end of this transistor seconds, and the 3rd transistorized second source/drain electrode end is coupled to an electronegative potential;
One the 4th transistor, the 4th transistorized first source/drain electrode end couples the second source/drain electrode end of this transistor seconds, and the 4th transistorized second source/drain electrode end is coupled to this electronegative potential, and the 4th transistorized gate terminal is coupled to the 4th signal;
One first phase inverter, the input end of this first phase inverter couples the 3rd signal;
One second phase inverter, the input end of this second phase inverter couple the 4th transistorized first source/drain electrode end, and the output terminal of this second phase inverter couples the 3rd transistorized gate terminal;
One the 5th transistor, the 5th transistorized first source/drain electrode end couples the output terminal of this first phase inverter, and the 5th transistorized gate terminal is coupled to the second source/drain electrode end of this first transistor;
One the 6th transistor, the 6th transistorized grid and first source/drain electrode end serial connection also couples the 5th transistorized second source/drain electrode end;
One the 7th transistor, the 7th transistorized first source/drain electrode end couples the 5th transistorized second source/drain electrode end, the 7th transistorized second source/drain electrode end is coupled to this electronegative potential, and the 7th transistorized gate terminal is coupled to the output terminal of this second phase inverter; And
One the 8th transistor, the 8th transistorized first source/drain electrode end couples the 6th transistorized second source/drain electrode end, the 8th transistorized second source/drain electrode end is coupled to this electronegative potential, and the 8th transistorized gate terminal is coupled to the output terminal of this second phase inverter.
2. shift register as claimed in claim 1, wherein this first transistor to the described transistor of the 8th transistor is a nmos pass transistor.
3. shift register as claimed in claim 1, wherein this first signal is a clock signal.
4. shift register as claimed in claim 1, wherein this secondary signal is an inversion clock signal.
5. shift register as claimed in claim 1, wherein this first signal and secondary signal are inverting each other.
6. shift register as claimed in claim 1, wherein the 3rd signal is the signal that last serial connection level shift register is exported.
7. shift register as claimed in claim 1, wherein the 4th signal is back one a serial connection level shift register institute output signal.
8. shift register as claimed in claim 1 comprises also that wherein at least one delay circuit is coupled to the 5th and the 6th transistor.
9. shift register as claimed in claim 8, wherein this delay circuit comprises at least:
One the 9th transistor, the 9th transistorized first source/drain electrode end connects the 9th transistorized gate terminal, and joins with the 5th transistorized second source/drain electrode end, and the 9th transistorized second source/drain electrode end is coupled to the 7th transistorized gate terminal; And
The tenth transistor, the tenth transistorized first source/drain electrode end couples the 9th transistorized second source/drain electrode end, the tenth transistorized second source/drain electrode end is coupled to this electronegative potential, and the tenth transistorized gate terminal is coupled to the output terminal of this second phase inverter.
10. shift register as claimed in claim 9, wherein the 9th transistor and the tenth transistor are nmos pass transistor.
11. shift register as claimed in claim 1, wherein this first phase inverter also comprises:
The 11 transistor, the 11 transistorized first source/drain electrode end connects the 11 transistorized gate terminal, and couples with this noble potential, and the 11 transistorized second source/drain electrode end is coupled to the 5th transistorized first source/drain electrode end; And
The tenth two-transistor, first source of the tenth two-transistor/drain electrode end couples the 11 transistorized second source/drain electrode end, second source of the tenth two-transistor/drain electrode end is coupled to this electronegative potential, and the gate terminal of the tenth two-transistor is coupled to the 3rd signal.
12. shift register as claimed in claim 11, wherein the 11 transistor and the tenth two-transistor are nmos pass transistor.
13. shift register as claimed in claim 1, wherein this second phase inverter also comprises:
The 13 transistor, the 13 transistorized first source/drain electrode end connects the 13 transistorized gate terminal, and couple with this noble potential, the 13 transistorized second source/drain electrode end is coupled to the 3rd transistorized gate terminal, and the 6th transistorized gate terminal; And
The 14 transistor, the 14 transistorized first source/drain electrode end couples the 13 transistorized second source/drain electrode end, the 14 transistorized second source/drain electrode end is coupled to this electronegative potential, and the 14 transistorized gate terminal is coupled to the 4th transistorized first source/drain electrode end.
14. shift register as claimed in claim 13, wherein the 13 transistor and the 14 transistor are nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100940027A CN100423132C (en) | 2006-06-16 | 2006-06-16 | Shift register |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100940027A CN100423132C (en) | 2006-06-16 | 2006-06-16 | Shift register |
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| CN1866404A CN1866404A (en) | 2006-11-22 |
| CN100423132C true CN100423132C (en) | 2008-10-01 |
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| CNB2006100940027A Expired - Fee Related CN100423132C (en) | 2006-06-16 | 2006-06-16 | Shift register |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101340197B1 (en) * | 2011-09-23 | 2013-12-10 | 하이디스 테크놀로지 주식회사 | Shift register and Gate Driving Circuit Using the Same |
| CN103137058A (en) * | 2011-11-24 | 2013-06-05 | 群康科技(深圳)有限公司 | Image display system and grid drive circuit |
| CN104751816B (en) * | 2015-03-31 | 2017-08-15 | 深圳市华星光电技术有限公司 | Shift-register circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6770979B2 (en) * | 2002-07-18 | 2004-08-03 | Advanced Semiconductor Engineering Inc. | Semiconductor package and substrate thereof |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6770979B2 (en) * | 2002-07-18 | 2004-08-03 | Advanced Semiconductor Engineering Inc. | Semiconductor package and substrate thereof |
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