TW201539418A - Display panel and gate driver - Google Patents

Abstract

The display panel includes gate lines and a gate driver. The gate driver includes series-coupled driving stages, in which each of the driving stages includes an input unit, an output unit, a pull-down unit, and a control unit. The input unit outputs a shift signal to a first control node. The output unit generates a gate-driving signal according to the shift signal. The pull-down unit selectively pulls the gate-driving signal to a first predetermined voltage according to a voltage level of a second control node. The control unit includes an inverter, which generates a control signal according to the shift signal. The control unit pulls the second control node to the first predetermined voltage during a disable period of the control signal. The control unit pulls the second control node to a second predetermined voltage during an enable period of the control signal.

Description

Display panel and gate driver

The present invention relates to a display panel, and more particularly to a gate driver for a display panel.

Recently, various liquid crystal display products have become quite popular. In order to effectively increase the viewing area of a liquid crystal display, a display panel technology suitable for a narrow bezel has been continuously proposed.

FIG. 1 is a schematic diagram of a conventional shift register circuit 100. The shift register circuit 100 is a common shift register circuit architecture. As shown in FIG. 1, the shift register circuit 100 receives the shift signal SS and changes the voltage level of the control node A to generate the gate drive signal SR_OUT.

In detail, when the current stage shift register circuit 100 outputs the gate drive signal SR_OUT, the control node A of the stage shift register circuit 100 is pulled up to the high level voltage by the scan control signal CS. When the shift register circuit 100 of the current stage performs the output gate drive signal SR_OUT, the control node A is floating. At this time, the control node A may only be clocked by the clock signal CLK/XCLK again via the parasitic capacitance. Charging is performed so that the stage shift register circuit 100 can correctly output the gate drive signal SR_OUT.

However, if the switch N1~N3 is affected by component aging or process variation, the threshold voltage of the component becomes smaller and the leakage current Ioff becomes larger, which may prevent the voltage level of the floating control node A from being correctly maintained at a high level. Voltage. That is to say, when the shift register circuit 100 of the present stage performs the output gate drive signal SR_OUT, the voltage level of the control node A may be charged to a higher level voltage by the clock signal CLK/XCLK. Alternatively, the voltage level of the control node A may be pulled down to a low level voltage due to excessive leakage current, thereby causing circuit operation failure.

In addition, the conventional shift register circuit 100 is implemented using a larger number of switches. This architecture has a large circuit area and is difficult to apply to a narrow bezel display panel.

Therefore, how to improve the operation failure of the shift register circuit due to the influence of leakage current and reduce the circuit area at the same time is one of the current important research and development topics, and has become an urgent target for improvement in related fields.

One aspect of the present disclosure provides a display panel. The display panel contains multiple gate lines and gate drivers. The gate driver includes a plurality of serially connected driver stages. Each driver stage is configured to output a gate drive signal to a corresponding one of the plurality of gate lines. Each driver stage includes an input unit, an output unit, a pull-down unit, and a control unit. The input unit is configured to output a shift signal to the first control node. The output unit is configured to generate a gate drive signal according to the shift signal. The pull-down unit is configured to selectively pull the gate driving signal to the first preset voltage according to the voltage level of the second control node. Control unit contains the inverse Phase device. The inverter is configured to generate a control signal according to the shift signal. The control unit pulls down the second control node to the first preset voltage during the disable period of the control signal, and pulls up the second control node to the second preset voltage during the enablement of the control signal.

Another aspect of the present disclosure provides a gate driver. The gate driver includes a plurality of serially connected driver stages. Each of the driver stages includes an input unit, an output unit, a control unit, and a pull-down unit. The input unit has an output. The output unit includes a first input end and an output end, wherein the first input end of the output unit is electrically coupled to the output end of the input unit, and the output end of the output unit is configured to output a gate drive signal. The control unit includes an inverter, a first switch and a second switch. The inverter includes an input end and an output end, wherein an input end of the inverter is electrically coupled to an output end of the input unit. The first switch includes a first end, a second end, and a control end, wherein the control end of the first switch is electrically coupled to the output end of the inverting unit, and the first end of the first switch is configured to receive a voltage. The second switch includes a first end, a second end, and a control end, wherein the control end of the second switch is electrically coupled to the output end of the input unit, and the first end of the second switch is configured to receive the second end of the first switch And the second end of the second switch is configured to receive a power signal. The pull down unit contains a third switch. The third switch includes a first end, a second end, and a control end, wherein the control end of the third switch is electrically coupled to the first end of the second switch, and the first end of the third switch is electrically coupled to the output of the output unit And the second end of the third switch is configured to receive a power signal.

In summary, the display panel and the gate driver disclosed in the present disclosure can maintain the nodes of the internal circuit in a specific operation during operation. Pressure to avoid the problem of operational failure caused by voltage floating, and has a low circuit area.

In order to make the disclosure more obvious, the attached symbols are as follows:

100, 324, 440‧‧‧ shift register circuit

200‧‧‧ display panel

220‧‧‧Image display area

240‧‧‧Source Driver

STV‧‧‧ initial pulse wave

222‧‧‧ pixels

320, 400‧‧‧ drive level

260, 300‧‧ ‧ gate driver

U2D‧‧‧Down signal

322, 422‧‧‧ input unit

VGH, VGL‧‧‧ preset voltage

SS‧‧‧ Shift signal

CS‧‧‧Control signal

D2U‧‧‧Upshift signal

444‧‧‧ Pulldown unit

442‧‧‧Output unit

446a‧‧‧Inverter

446‧‧‧Control unit

460‧‧‧ buffer

XDONB‧‧‧ power signal

Ioff‧‧‧Leakage current

C‧‧‧ capacitor

X, Y, A, B‧‧‧ control nodes

DL1, DL2, DL3, DL4, DLN‧‧‧ data lines

CLK, XCLK‧‧‧ clock signal

GL1, GL2, GL3, GLM‧‧ ‧ gate line

SR[1], SR[2], SR[3], SR[n-1], SR[n], SR[n+1], SR_OUT, SR_OUT[n]‧‧‧ gate drive signals

T1, T2, T3‧‧‧

N1, N2, N3, M1, M2, M3, M4, M5, M6, M7, M8‧‧‧ switch

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A schematic diagram of a display panel according to an embodiment of the present disclosure; FIG. 3A is a schematic diagram showing a gate driver according to an embodiment of the present disclosure; FIG. 3B is a diagram illustrating an embodiment of the disclosure according to an embodiment of the present disclosure. FIG. 3A is a timing diagram of an operation signal for performing a scan from top to bottom; FIG. 3C is a diagram showing the operation of the gate driver in FIG. 3A for performing a bottom-up scan according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram showing a driving stage according to an embodiment of the present disclosure; FIG. 5 is a timing diagram showing an operation signal of a driving stage shown in FIG. 4 according to an embodiment of the present disclosure; 6A is a schematic diagram showing states of switches in the driving stage of FIG. 4 in the period T1 according to an embodiment of the present disclosure; FIG. 6B is shown in the period T2 according to an embodiment of the disclosure. A schematic diagram of states of switches in the driver stage of FIG. 4; and FIG. 6C is a schematic diagram showing states of switches in the driver stage of FIG. 4 in the period T3 according to an embodiment of the present disclosure.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or just operate.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within about 20%, preferably within about 10%, and more preferably, It is about five percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "roughly".

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

FIG. 2 is a schematic diagram of a display panel 200 according to an embodiment of the present disclosure. As shown in FIG. 2, the display panel 200 includes N data lines DL1 to DLN, M gate lines GL1 to GLM, an image display area 220, a source driver 240, and a gate driver 260. The image display area 220 includes a plurality of pixels 222. The plurality of pixels are disposed in the image display area 220. Each of the pixels 222 is electrically coupled to a corresponding one of the N data lines DL1 DL DLN and the corresponding one of the M gate lines GL1 GGLM.

The source driver 240 is coupled to the data lines DL1 DL DLN, and is configured to transmit the data signals to the image display area 220 to the corresponding pixels 222 through the data lines DL1 DL DLN, and the gate driver 260 is coupled to the gate lines GL1 GGLM. The output gate driving signals are sequentially transmitted to the gate lines GL1 G GLM and transmitted to the image display area 220 through the gate lines GL1 G GLM to the corresponding pixels 222 .

3A is a schematic diagram showing a gate driver in accordance with an embodiment of the present disclosure. For convenience of explanation, the gate driver 300 of FIG. 3A illustrates a driver stage 320 having three stages of series connection. However, the number of stages in FIG. 3A is merely an illustration, and the present invention is not limited thereto.

As shown in FIG. 3A, the gate driver 300 includes a multi-stage serially connected driver stage 320. Each driver stage 320 is configured to output a corresponding gate drive signal SR[n] to a corresponding one of the gate lines GL1 GGLM. The driver stage 320 includes an input unit 322 and a shift register circuit 324. The input unit 322 is configured to select the up-shift signal D2U and the bottom according to the gate drive signal SR[n-1] outputted by the pre-drive stage 320 and the gate drive signal SR[n+1] output by the subsequent stage drive stage 320. The shift signal U2D is output as a shift signal SS to the shift register circuit 324, To generate a corresponding gate drive signal SR[n]. For example, as shown in FIG. 3A, the second stage driving stage 320 can receive the gate driving signal SR[1] outputted by the first stage driving stage 320 and the gate driving signal SR outputted by the third stage driving stage 320. 3], and accordingly generate the gate drive signal SR[2] to the gate line GL2 indicated in FIG.

In this embodiment, the input unit 322 includes a switch M1 and a switch M2. The first end of the switch M1 is for receiving the downward shift signal U2D, the second end of the switch M1 is for outputting the shift signal SS, and the control end of the switch M2 is for receiving the gate drive signal SR of the output of the front stage drive stage 320 [ N-1]. The first end of the switch M2 is electrically coupled to the second end of the switch M2, the second end of the switch M2 is configured to receive the up-shift signal D2U, and the control end of the switch S2 is configured to receive the gate of the output of the rear-stage driver stage 320 Drive signal SR[n+1].

FIG. 3B is a timing diagram showing an operation signal of the gate driver 300 in FIG. 3A performing top-down scanning according to an embodiment of the present disclosure. FIG. 3C is a timing diagram showing an operation signal of the gate driver 300 in FIG. 3A for performing a bottom-up scan according to an embodiment of the present disclosure. In practice, the two-way scanning operation can be completed by setting the up-shift signal D2U and the down-shift signal U2D according to actual needs.

For example, please refer to FIG. 3A and FIG. 3B together, wherein the input unit 322 of the driver stage 320 of the first stage and the third stage is further configured to receive the initial pulse wave STV. In this example, the gate driver 300 is arranged to perform an operation of sequentially scanning from top to bottom. Wherein, the down shift signal U2D is set to a signal having a high voltage level, and the up shift signal D2U is set to a signal having a low voltage level. As shown in Figure 3B, when an initial high voltage level is received At the time of the pulse wave STV (that is, the period T1), the switch M1 of the input unit 322 of the first stage driving stage 320 and the switch M2 of the input unit 322 of the third stage driving stage 320 are turned on.

Therefore, the voltage level of the control node X can be pulled up to a high voltage level, and the voltage level of the control node Y is pulled down to a low voltage level. When the initial pulse STV transitions to the low voltage level (ie, the period T2), the switch M1 of the input unit 322 of the first stage driving stage 320 and the switch M2 of the input unit 322 of the third stage driving stage 320 are both turned off. At this time, the voltage level of the control node X remains at the high voltage level. In other words, at the time period T2, the input unit 322 of the first stage driving stage 320 can output the shift signal SS having a high voltage level, thereby completing the top-down scanning operation.

Alternatively, please refer to Figures 3A and 3C together. In this example, the gate driver 300 is arranged to perform an operation of sequentially scanning from bottom to top. Wherein, contrary to the setting mode of FIG. 3B, the down-shift signal U2D is set to a signal having a low voltage level, and the up-shift signal D2U is set as a signal having a high voltage level. As shown in FIG. 3C, when the initial pulse wave STV having a high voltage level is received (that is, the period T1), the input of the switch M1 of the input unit 322 of the first stage driving stage 320 and the input of the third stage driving stage 320 are shown. Switch M2 of unit 322 is conducting.

Therefore, the voltage level of the control node X is pulled down to the low voltage level, and the voltage level of the control node Y is pulled up to the high voltage level. At the time period T2, the initial pulse wave STV transitions to the low voltage level, and the switch M1 of the input unit 322 of the first stage drive stage 320 and the switch M2 of the input unit 322 of the third stage drive stage 320 are both turned off. When the voltage level of the control node Y is still guaranteed Hold at high voltage level. In other words, at the time period T2, the input unit 322 of the third stage driving stage 320 can output the shift signal SS having a high voltage level, thereby completing the bottom-up scanning operation.

The following paragraphs will set forth various embodiments to illustrate the functions and applications of the above-described driver stage 320, but the disclosure is not limited to the embodiments listed below.

4 is a schematic diagram showing a driver stage in accordance with an embodiment of the present disclosure. As shown in FIG. 4, the driver stage 400 includes an input unit 422 and a shift register circuit 440. The shift register circuit 440 includes an output unit 442, a pull down unit 444, and a control unit 446.

In operation, the input unit 422 is configured to output the shift signal SS to the control node A. The output unit 442 is configured to generate a gate drive signal SR[n] according to the shift signal SS. The pull-down unit 444 is configured to selectively pull down the gate drive signal SR[n] and the control node A to the preset voltage VGL according to the voltage level of the control node B. Control unit 446 includes an inverter 446a. The input end of the inverter 446a is electrically coupled to the control node A to receive the shift signal SS to generate the control signal CS, wherein the control signal CS is inverted to the shift signal SS.

In this embodiment, the control unit 446 pulls down the control node B to the preset voltage VGL during the disable period of the control signal CS (ie, at a low level). The control unit 446 pulls up the control node B to the preset voltage VGH during the enable period of the control signal CS (ie, at a high level). Wherein, the preset voltage VGH is set higher than the preset voltage VGL. As such, during the operation of the driver stage 400, it is ensured that its control node B is not A floating state will occur to prevent the circuit from failing due to excessive leakage current. Specific detailed operations will be explained later.

As shown in FIG. 4, the control unit 446 further includes a switch M3 and a switch M4. The first end of the switch M3 is configured to receive the preset voltage VGH, and the control end of the switch M3 is electrically coupled to the output end of the inverter 446a to receive the control signal CS. The second end of the switch M3 and the first end of the switch M4 are electrically coupled to the control node B, and the second end of the switch M4 is used to receive the power signal XDONB.

In operation, the switch M3 is selectively turned on according to the control signal CS to transmit the preset voltage VGH to the control node B. The switch M4 transmits the power signal XDONB to the control node B according to the shift signal SS (ie, the voltage level of the control node A). In the case of normal operation, the voltage level of the power signal XDONB is set to be the same as the preset voltage VGL. In other words, the voltage level of the control node B can be switched to the level of the preset voltage VGH or the preset voltage VGL by the switch M3 and the switch M4, respectively. When the system power supply is unstable or powered off, the voltage level of the power signal XDONB is switched to a high voltage (for example, a preset voltage VGH), and the driver stage 400 outputs a gate drive signal SR having a high voltage level. n] to reset multiple pixels 222.

Furthermore, the pull-down unit 444 includes a switch M5 and a switch M6. The first end of the switch M5 is electrically coupled to the control node A, and the control end of the switch M5 and the control end of the switch M6 are electrically coupled to the control node B. The first end of the switch M6 is used to output the gate drive signal SR[n], and the second end of the switch M5 and the second end of the switch M6 are used to receive the power signal XDONB.

Thus, the switch M5 can be turned on when the voltage level of the control node B is at a high voltage level (for example, the level of the preset voltage VGH) to pull the control node A down to the preset voltage VGL. That is to say, the voltage level of the control node A can be adjusted to a different voltage level by the shift signal SS transmitted by the input unit 422 and the switch M5. In addition, as previously described, the power signal XDONB is at the level of the preset voltage VGL under normal operation, so the switch M6 can be at a high voltage level at the control node B (for example, the level of the preset voltage VGH). When turned on, the gate drive signal SR[n] is pulled down to the level of the preset voltage VGH.

As shown in FIG. 4, the output unit 442 includes a switch M7, a switch M8, and a capacitor C. The first end of the switch M7 (that is, the input end of the output unit 442) is electrically coupled to the control node B to receive the shift signal SS, and the control end of the switch M7 is configured to receive the preset voltage VGH. The first end of the switch M8 (ie, the other input end of the output unit 442) is configured to receive the clock signal CLK/XCLK, and the second end of the switch M8 (ie, the output end of the output unit 442) is electrically coupled to the switch The first end of M6 is an output gate drive signal SR[n], wherein the clock signal CLK and the clock signal XCLK are mutually inverted. The capacitor C is electrically coupled between the control end of the switch M8 and the second end of the switch M8.

Moreover, in some embodiments, the driver stage 400 can further include a buffer 460. The buffer 460 is configured to output a gate driving signal SR_OUT[n] having a large driving capability to the corresponding gate lines GL1 G GLM.

FIG. 5 is a timing diagram showing the operation signals of the driving stage shown in FIG. 4 according to an embodiment of the present disclosure. Figure 6A is based on the disclosure One embodiment shows a state diagram of the switches in the driver stage 400 of FIG. 4 in the period T1. For convenience of explanation, please refer to FIGS. 3A, 5 and 6A together, and the operation of the driver stage 400 will be described below. In addition, the following operations will be based on the sequential scanning from top to bottom. Since the operations of sequentially scanning from bottom to top can be analogized, no further details are provided herein.

As shown in FIG. 5 and FIG. 6A, during the period T1, the gate drive signal SR[n-1] outputted by the (N-1)th stage of the driver stage 400 is an enable period (ie, at a high level voltage). The period of time), and the gate drive signal SR[n+1] outputted by the (N+1)th stage of the driver stage 400 is the disable period (that is, the period of the low level voltage). Therefore, the switch M1 in the input unit 422 is turned on, the switch M2 is turned off (ie, not turned on), and the down-shifted signal U2D is output as the shift signal SS to the control node A.

As described earlier, since the down-shift signal U2D is set to a high level voltage signal (as shown in FIG. 3B) in the sequential scanning operation from top to bottom, the shift signal SS at this time is also a high level voltage signal. . After receiving the shift signal SS, the inverter 446a generates a control signal CS having a low level. Therefore, the switch M3 is turned off, and the switch M4 is turned on. At this time, the control node B is pulled down to the preset voltage VGL by the power supply signal XDONB via the turned-on switch M3, and the switch M5 and the switch M6 are turned off.

In addition, since the pulse signal XCLK is at a low voltage level at this time, the voltage difference between the control terminal and the second terminal of the switch M7 is sufficient to turn on the switch M7, so the shift signal SS can turn on the switch M8 via the switch M7, so that The pulse signal XCLK is output as the gate drive signal SR[n].

FIG. 6B is illustrated in time period T2 according to an embodiment of the present disclosure. A schematic diagram of the states of the switches in the driver stage 400 of FIG. 4 . As shown in FIGS. 5 and 6B, during the period T2, the (N-1)th gate drive signal SR[n-1] is switched to the disable period, and the (N+1)th gate drive is driven. The signal SR[n+1] remains in the disable period. Therefore, both the switch M1 and the switch M2 are turned off. Since the voltage level of the control node A has been pulled up to a high voltage level (for example, the level of the preset voltage VGH) in the previous period T1, the switch M4 can remain turned on. Inverter 446a also continuously outputs a control signal CS having a low voltage level while leaving switch M3 off. As a result, during the period T2, the voltage level of the control node B can still be stably pulled down to the preset voltage VGL via the switch M5.

Further, at the time period T2, the clock signal XCLK is switched to the high voltage level, and the switch M7 is turned off. However, since the control terminal of the switch M7 has been charged to the high voltage level via the shift signal SS during the period T1, the switch M7 can remain turned on to use the clock signal XCLK having the high voltage level as the gate drive signal SR [ n] output.

FIG. 6C is a schematic diagram showing the state of each switch in the driving stage 400 of FIG. 4 in the period T3 according to an embodiment of the present disclosure. During the period T3, as shown in FIG. 5 and FIG. 6C, the Nth gate driving signal SR[n] is switched to the low level voltage signal, and the (N+1)th gate driving signal SR[n+ 1] Switch to the enable period. At this time, the switch M1 is turned off, and the switch M2 is turned on. Therefore, the shift signal D2U having the low voltage level is output as the shift signal SS to the control node A to turn off the switch M4. At the same time, the inverter 446a correspondingly generates the control signal CS having a high voltage level, and turns the switch M3 on. Control node B can be pulled up to a preset voltage via switch M3 VGH, and the switch M5 and the switch M6 are turned on, so that the voltage level of the control node A and the gate drive signal SR[n] are switched to the level of the preset voltage VGL.

As described above, in the period T1 and the period T2, the voltage level of the control node B can be maintained at the level of the preset voltage VGL via the turned-on switch M4. At the time period T3, the voltage level of the control node B can be switched and maintained at the level of the preset voltage VGH via the switch M3. In other words, during the overall operation, the voltage level of the control node B in the Nth stage driver stage 400 can be stably maintained at a specific voltage level (for example, the preset voltage VGH or the preset voltage VGL). Therefore, the gate driver 300 shown in the present disclosure can avoid the influence of process variation, component aging, leakage current or parasitic capacitance, etc., resulting in failure of circuit operation.

In various embodiments of the present disclosure, each switch may be a transistor of each type, such as a metal oxide semiconductor field effect transistor (MOSFET), a bottom gate transistor, a top gate transistor, a thin film transistor, or the like. Wait. The above is only an example, and the disclosure is not limited thereto.

Table 1 lists a comparison of the power consumption comparisons of the conventional shift register circuit 100 and the driver stage 400 shown in the present disclosure. As shown in Table 1, the more stages the driver stage 400 uses in the gate driver, compared to the conventional shift register circuit 100, can have more significant power consumption savings.

Table 2 lists the simulation results of the power consumption of the driver stage 400 of FIG. 4 and its threshold voltage. Vtn in Table 2 is the threshold voltage of the N-type transistor in the driver stage 400, and Vtp is the threshold voltage of the P-type transistor (for example, the P-type transistor in the inverter 446a) in the driver stage 400, and Tr is the gate. The rise time of the pole drive signal SR[n], and Tf is the fall time of the gate drive signal SR[n], the unit of which is microsecond.

In most applications, the rise time Tr and the fall time Tf need to be set at least within 0.8 microseconds. According to the above Table 2, when the components are mutated, the rise time Tr and the fall time Tf of the drive stage 400 can be stably operated within 0.8 microseconds. In other words, compared with the conventional shift register circuit 100, since the driver stage 400 uses fewer switches, and the plurality of switches in the driver stage 400 are mostly of the same type, it can be more stable and reliable. degree.

In summary, the display panel and the gate driver disclosed in the present disclosure can maintain the nodes of the internal circuit at a specific voltage during operation to avoid the problem of operation failure caused by voltage floating, and have Low circuit area.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the invention, and the present invention can be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

400‧‧‧Driver

440‧‧‧Shift register circuit

422‧‧‧Input unit

U2D‧‧‧Down signal

D2U‧‧‧Upshift signal

VGH‧‧‧Preset voltage

SS‧‧‧ Shift signal

CS‧‧‧Control signal

442‧‧‧Output unit

444‧‧‧ Pulldown unit

446‧‧‧Control unit

446a‧‧‧Inverter

XDONB‧‧‧ power signal

460‧‧‧ buffer

C‧‧‧ capacitor

A, B‧‧‧ control node

SR[n-1], SR[n], CLK, XCLK‧‧‧ clock signals

SR[n+1], SR_OUT[n]‧‧‧ gate drive signal

M1, M2, M3, M4, M5, M6, M7, M8‧‧‧ switch

Claims (10)

A display panel comprising: a plurality of gate lines; and a gate driver comprising a plurality of serially connected driver stages, wherein each driver stage is configured to output a gate drive signal to a corresponding one of the gate lines Each of the driver stages includes: an input unit for outputting a shift signal to a first control node; an output unit for generating the gate drive signal according to the shift signal; and a pull-down unit, The gate driving signal is selectively pulled down to a first preset voltage according to a voltage level of a second control node; and a control unit includes: an inverter for using the shift signal according to the shift signal Generating a control signal, wherein the control unit pulls the second control node to the first preset voltage during an disable period of the control signal, and during the enabling period of the control signal, the second control The node is pulled up to a second preset voltage. The display panel of claim 1, wherein the control unit comprises: a first switch for selectively conducting according to the control signal to transmit the second preset voltage to the second control node; and a second a switch for selectively conducting according to the shift signal for transmitting And a power signal to the second control node, wherein under normal operation, the voltage level of the power signal is the first preset voltage. The display panel of claim 2, wherein the pull-down unit comprises: a third switch, configured to be turned on when the voltage level of the second control node is the second preset voltage, to enable the first control node Pulling down to the first preset voltage; and a fourth switch for turning on when the voltage level of the second control node is the second preset voltage, to pull the gate driving signal to the first pre Set the voltage. The display panel of claim 3, wherein the first switch, the second switch, the third switch, and the fourth switch each comprise a first end, a second end, and a control end, The control end of the first switch is configured to receive the control signal, the first end of the first switch is configured to receive the second preset voltage, and the second end of the first switch is electrically coupled to the second control a node, the control end of the second switch is electrically coupled to the first control node, the first end of the second switch is electrically coupled to the second control node, and the second end of the second switch is used Receiving the power signal, the control end of the third switch is electrically coupled to the second control node, the first end of the third switch is electrically coupled to the first control node, and the second switch is the second The terminal is configured to receive the power signal, and the control end of the fourth switch is electrically coupled to the second control node, where the The first end of the fourth switch is configured to output the gate driving signal, and the second end of the fourth switch is configured to receive the power signal. The display panel of claim 1, wherein the input unit selects a shift signal and an up shift signal according to the gate drive signal outputted by a front stage drive stage and the gate drive signal output by a subsequent stage drive stage. One of them acts as the shift signal. The display panel of claim 1, wherein the output unit transmits a clock signal as the gate drive signal during an enable period of the shift signal. A gate driver comprising a plurality of serially connected driver stages, each of the driver stages comprising: an input unit having an output; an output unit comprising: a first input electrically coupled to the The output terminal of the input unit; and an output terminal for outputting a gate drive signal; and a control unit comprising: an inverter comprising: an input end electrically coupled to the output end of the input unit And an output; a first switch includes a first end, a second end, and a control end, wherein the control end of the first switch is electrically coupled to the output end of the inverting unit, the first end of the first switch The terminal is configured to receive a voltage, and the second switch includes a first end, a second end, and a control end, wherein the control end of the second switch is electrically coupled to the output end of the input unit, The first end of the second switch is configured to receive the second end of the first switch, and the second end of the second switch is configured to receive a power signal; and the pull-down unit includes: a third switch, a first end, a second end, and a control end, wherein the control end of the third switch is electrically coupled to the first end of the second switch, and the first end of the third switch is electrically coupled The output end of the output unit is connected to the second end of the third switch for receiving the power signal. The gate driver of claim 7, wherein the pull-down unit further comprises: a fourth switch comprising a first end, a second end, and a control end, wherein the control end of the fourth switch is electrically coupled The first end of the fourth switch is electrically coupled to the output end of the input unit, and the second end of the fourth switch is configured to receive the power signal. The gate driver of claim 7, wherein the output unit is further packaged The second input end is configured to receive a clock signal, and the output unit includes: a fourth switch, including a first end, a second end, and a control end, wherein the control end of the fourth switch is used Receiving the voltage, the first end of the first switch is electrically coupled to the first input end of the output unit; the fifth switch includes a first end, a second end, and a control end, wherein the The second end of the fifth switch is electrically coupled to the second end of the fourth switch, the first end of the fifth switch is electrically coupled to the second input end of the output unit, and the fifth switch is The second end is electrically coupled to the output end of the output unit; and a capacitor is electrically coupled between the control end of the fifth switch and the second end of the fifth switch. The gate driver of claim 7, wherein the input unit comprises: a fourth switch having a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive a a first-stage gate driving signal, the first end of the fourth switch is configured to receive an up-shift signal, the second end of the fourth switch is electrically connected to the output end of the input unit, and a fifth switch has a first end, a second end, and a control end, wherein the control end of the fifth switch is configured to receive a rear gate drive signal, and the first end of the fifth switch is electrically coupled to the fourth The second end of the switch, the second end of the fifth switch is configured to receive an upshift signal.