CN116054834A - Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter - Google Patents
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Abstract
The application discloses a four-way or eight-way time sequence interleaved high-speed digital-to-analog converter. The four-way time sequence interweaving high-speed digital-to-analog converter comprises a plurality of digital-to-analog conversion units, each comprising: two differential sets of a plurality of latch modules and a plurality of conversion modules, each latch module comprising: the first to sixth transistors, the first and second inverters, the grid of the first and second transistors receives one input clock signal, the source electrode of the second transistor is connected with the drain electrode of the third transistor, the grid of the third transistor receives one bit of input data, the drain electrodes of the first and second transistors are all connected with the input end of the first inverter, the output end of the first inverter is connected with the grid of the fifth transistor, the grid of the fourth and sixth transistors receives another input clock signal, the drain electrodes of the fourth and fifth transistors are all connected with the input end of the second inverter, and the source electrode of the fifth transistor is connected with the drain electrode of the sixth transistor; each conversion module includes: a seventh transistor and a plurality of eighth transistors.
Description
Technical Field
The present invention relates generally to the field of integrated circuits, and more particularly to a four-way or eight-way time-sequence interleaved high-speed digital-to-analog converter.
Background
In high-speed SerDes circuit applications based on digital-to-analog converter schemes, the transmit side (TX) typically employs a Half-speed architecture (Half Rate) and a Quarter-speed (Quarter Rate) architecture and is implemented by 2:1 or 4: a multiplexer of 1 input mode generates baud rate data and is connected to a high speed digital to analog converter (DAC). With the higher demands on SerDes speed for data interconnection and transmission, tradition 2:1 and 4: the multiplexer of the 1 input mode may generate Inter-symbol interference (Inter-symbol interference, ISI) and greatly affect the performance of the high-speed digital-to-analog converter. Currently, analog-to-digital converters (ADCs) of the high-speed multiplexing timing interleaving technique have been widely used at the receiving end (RX) of SerDes. The present application describes how a high-speed digital-to-analog converter (DAC) at the transmit end (TX) can be implemented by a four-way or eight-way timing interleaving technique. By implementing four-way or eight-way data timing interleaving in a high-speed digital-to-analog converter, performance of the high-speed digital-to-analog converter (DAC) in single-channel 112Gbp/s PAM4 and higher applications is improved.
Disclosure of Invention
The invention aims to provide a four-way or eight-way time sequence interleaved high-speed digital-to-analog converter which can reduce the speed on a clock path so as to realize better power consumption and jitter of the clock path.
The application discloses a high-speed digital-to-analog converter of four-way time sequence interweaving, including: the digital-to-analog conversion units comprise:
two differential sets of a plurality of latch modules, each latch module comprising: the first transistor to the sixth transistor, and the first and the second inverter, the gates of the first and the second transistors receive one input clock signal, the source of the first transistor is connected to the power supply terminal, the source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor receives one bit of input data, the sources of the third transistor are grounded, the drains of the first and the second transistors are connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the gate of the fifth transistor, the gates of the fourth and the sixth transistors receive the other input clock signal, the drains of the fourth and the fifth transistors are connected to the input terminal of the second inverter, the source of the fourth transistor is connected to the power supply terminal, the source of the fifth transistor is connected to the drain of the sixth transistor, and the source of the sixth transistor is connected to the ground terminal;
two differential sets of several conversion modules, each conversion module comprising: the grid electrodes of the seventh transistors are connected with the drains of the eighth transistors, the grid electrodes of the eighth transistors are connected with the output ends of the second inverters of the corresponding latch modules, and the source electrodes of the eighth transistors are connected with the ground.
In a preferred embodiment, the set of several latch modules includes four latch modules, in a first latch module, gates of the first and second transistors receive a 90 ° input clock signal, and gates of the fourth and sixth transistors receive a 0 ° input clock signal; in the second latch module, the gates of the first and second transistors receive a 180 ° input clock signal, and the gates of the fourth and sixth transistors receive a 90 ° input clock signal; in a third latch module, gates of the first and second transistors receive 270 ° input clock signals, and gates of the fourth and sixth transistors receive 180 ° input clock signals; in the fourth latch module, the gates of the first and second transistors receive a 0 ° input clock signal, and the gates of the fourth and sixth transistors receive a 270 ° input clock signal.
In a preferred embodiment, the gate of the third transistor receives the input data D <0>, in the first latch module, the gate of the third transistor receives the input data D <1>, in the third latch module, the gate of the third transistor receives the input data D <2>, and in the fourth latch module, the gate of the third transistor receives the input data D <3>.
In a preferred embodiment, the set of conversion modules includes four conversion modules.
In a preferred embodiment, the method further comprises: the power supply comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the power supply end, the other end of the first resistor is connected with the drain electrode of a seventh transistor of one group of a plurality of conversion modules, one end of the second resistor is connected with the power supply end, and the other end of the second resistor is connected with the drain electrode of a seventh transistor of the other group of a plurality of conversion modules.
In a preferred embodiment, the first and fourth transistors are PMOS transistors and the second, third, fifth through eighth transistors are NMOS transistors.
The application also discloses a high-speed digital-to-analog converter of eight paths of time sequence interweaving, which comprises: two four-way time-interleaved high-speed digital-to-analog converters as described above, wherein one four-way time-interleaved high-speed digital-to-analog converter receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <0>, D <2>, D <4>, and D <6>, and the other four-way time-interleaved high-speed digital-to-analog converter receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <1>, D <3>, D <5>, and D <7>.
Compared with the prior art, the application has the following beneficial effects:
firstly, through the concept of four-way or eight-way time sequence interleaving and corresponding latch modules, 1UI pulses with different time sequences are realized and sequentially sent into a high-speed digital-to-analog converter, so that ISI (Inter-symbol interference) of data output by each latch module is greatly reduced.
Second, by implementing multi-way (four-way or eight-way) timing interleaving, we can also greatly reduce the speed on the clock path to achieve better power consumption and jitter of the clock path. Thirdly, 1UI data generated by four or eight paths of time sequence interleaving can be connected with the high-speed digital-to-analog converter in a seamless way, and the data can be combined at a tailless current source to obtain output of the baud rate data. Fourth, this concept will show good scalability in applications of SerDes of 112Gbp/s PAM4 in a single channel even higher speeds, and by expanding the four-way timing interleaving concept to eight-way timing interleaving we can achieve doubling of the sampling speed from 112Gbp/s PAM4 to 224Gbp/s PAM 4.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
FIG. 1 is a schematic diagram of a four-way time interleaved high speed digital to analog converter in one embodiment of the present application.
FIG. 2 is a circuit diagram of a latch module in one embodiment of the present application.
FIG. 3 is a timing diagram of a latch module according to one embodiment of the present application.
Fig. 4 is a timing diagram of a four-way timing interleaved high-speed digital-to-analog converter in one embodiment of the present application.
Fig. 5 is a schematic diagram of an eight-way time-interleaved high-speed digital-to-analog converter in one embodiment of the present application.
Fig. 6 is a timing diagram of an eight-way timing interleaved high-speed digital-to-analog converter in one embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application discloses a four-way time sequence interleaved high-speed digital-to-analog converter, the circuit structure schematic diagram of which is shown with reference to fig. 1, the four-way time sequence interleaved high-speed digital-to-analog converter 100 comprises: a plurality of digital-to-analog conversion units 101, each digital-to-analog conversion unit 101 comprising: two differential sets of latch modules 102, and two differential sets of conversion modules 103.
Referring to fig. 2, each latch module 102 includes: first to sixth transistors M1 to M6, and first and second inverters 201 and 202. The gates of the first transistor M1 and the second transistor M2 receive an input clock signal, the source of the first transistor M1 is connected to a power supply terminal, the source of the second transistor M2 is connected to the drain of the third transistor M3, the gate of the third transistor M3 receives a bit of input data, the source of the third transistor M3 is grounded, the drains of the first transistor M1 and the second transistor M2 are both connected to the input terminal of the first inverter 201, the output terminal of the first inverter 201 is connected to the gate of the fifth transistor M5, the gates of the fourth transistor M4 and the sixth transistor M6 receive another input clock signal, the drains of the fourth transistor M4 and the fifth transistor M5 are both connected to the input terminal of the second inverter 202, the source of the fourth transistor M4 is connected to the power supply terminal, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6, and the source of the sixth transistor M6 is connected to the ground.
In one embodiment, the set of several latch modules includes four latch modules 102. In the first latch module, the gates of the first transistor M1 and the second transistor M2 receive the 90 ° input clock signal, and the gates of the fourth transistor M4 and the sixth transistor M6 receive the 0 ° input clock signal. In the second latch module, the gates of the first transistor M1 and the second transistor M2 receive a 180 ° input clock signal, and the gates of the fourth transistor M4 and the sixth transistor M6 receive a 90 ° input clock signal. In the third latch module, the gates of the first transistor M1 and the second transistor M2 receive the 270 ° input clock signal, and the gates of the fourth transistor M4 and the sixth transistor M6 receive the 180 ° input clock signal. In the fourth latch module, the gates of the first transistor M1 and the second transistor M2 receive the 0 ° input clock signal, and the gates of the fourth transistor M4 and the sixth transistor M6 receive the 270 ° input clock signal.
In the first latch module, the gate of the third transistor M3 receives the input data D <0>, in the second latch module, the gate of the third transistor M3 receives the input data D <1>, in the third latch module, the gate of the third transistor M3 receives the input data D <2>, in the fourth latch module, the gate of the third transistor M3 receives the input data D <3>.
With continued reference to fig. 1, each conversion module 103 includes: a seventh transistor M7 and a plurality of eighth transistors M8, wherein the gate of the seventh transistor M7 receives the bias voltage Vb, the source of the seventh transistor M7 is connected to the drains of the plurality of eighth transistors M8, the gate of the plurality of eighth transistors M8 is connected to the output terminal of the second inverter 202 of the corresponding latch module 102, and the source of the plurality of eighth transistors M8 is connected to the ground terminal. In one embodiment, the set of conversion modules includes four conversion modules 103.
In one embodiment, the first transistor M1 and the fourth transistor M4 are PMOS transistors, and the second transistor, the third transistor, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors.
Fig. 3 is a timing diagram of a latch module according to an embodiment of the present application, and the first latch module is taken as an example for illustration. Wherein, clk_1 received by the gates of the first transistor M1 and the second transistor M2 is a 90 ° input clock signal, clk_2 received by the gates of the fourth transistor M4 and the sixth transistor M6 is a 0 ° input clock signal, and the gate of the third transistor M3 receives input data D <0>. The rising edge of clk_1 determines one side of Data D0 and the falling edge of clk_2 determines the other side of Data D0, thereby generating Data D0 (i.e., data <0 >). The data D0 is output to the gate of the eighth transistor M8 of the first conversion module 103. It should be appreciated that the timing diagrams of other latch modules may be similarly arranged and generate Data <1:3>, respectively. Fig. 4 is a timing diagram of a four-way timing interleaved high-speed digital-to-analog converter in one embodiment of the present application.
In one embodiment, the four-way time-interleaved high-speed digital-to-analog converter 100 further comprises: the first power supply terminal is connected to the other end of the first resistor R1, the other end of the first resistor R1 is connected to a resistor R1 and a second resistor R2 of a plurality of conversion modules 103, one end of the first resistor R1 is connected to the drain electrode of the seventh transistor M7, one end of the second resistor R2 is connected to the power supply terminal, and the other end of the second resistor R2 is connected to the drain electrode of the seventh transistor M7 of another plurality of conversion modules 103.
In order to better understand the technical solutions of the present application, the following description is given with reference to a specific example, in which details are listed mainly for the sake of understanding, and are not meant to limit the scope of protection of the present application.
The present patent provides a novel 4-way and 8-way interleaved digital-to-analog converter (DAC) for use in ultra-high speed line applications. The proposed 4-way timing interleaved DAC includes 4 individual latches for generating 1UI pulses. These 4 pairs of differential 1UI pulses alternately turn on and off the DAC input switches and merge at the tailless current source, as shown in fig. 1.
Fig. 2 shows one possible implementation of a latch. The 4T data is sent to 4 different latches, clk_1 and clk_2 in each latch trigger the 1UI pulse accordingly. In order to obtain accurate 1UI data information, a 4-phase quadrature clock with phase calibration is required here. Fig. 3 depicts how the rising edge of clk_1 and the falling edge of clk_2 generate 1UI pulses. Here taking D0 and CLK0/CLK90 as examples.
Fig. 4 shows all input 1UI pulses of the DAC and their timing relationship. This figure uses single ended data as an explanation, while figure 1 is differential data.
The advantage of this architecture is that it can be extended to 8-way interleaved DACs and achieve higher sampling rates. Fig. 5 shows a variation of our design to construct an 8-way interleaved DAC by combining two 4-way timing interleaved DACs. Rather than using a 4-phase clock and 4T data at the latch input. 8-phase clocks and 8T data are required and 1UI pulses similar to DACs are generated.
Another aspect of the present application discloses an eight-way time-interleaved high-speed digital-to-analog converter, the structure of which is shown with reference to fig. 5. The eight-way time-interleaved high-speed digital-to-analog converter 500 includes: two high-speed digital-to- analog converters 501, 502 interleaved in four ways as described above. Wherein a four-way time interleaved high speed digital to analog converter 501 receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <0>, D <2>, D <4>, and D <6>, specifically: in the first latch, the rising edge of clk_1 (135 °) determines one side of Data D0, the falling edge of clk_2 (0 °) determines the other side of Data D0, thereby generating Data D0 (i.e., data <0 >), in the second latch, the rising edge of clk_1 (225 °) determines one side of Data D2, the falling edge of clk_2 (90 °) determines the other side of Data D2, thereby generating Data D2 (i.e., data <2 >), in the third latch, the rising edge of clk_1 (315 °) determines one side of Data D4, the falling edge of clk_2 (180 °) determines the other side of Data D4, thereby generating Data D4 (i.e., data <4 >), and in the fourth latch, the rising edge of clk_1 (45 °) determines one side of Data D6, the falling edge of clk_2 (270 °) determines the other side of Data D6, thereby generating Data D6 (i.e., data <6 >). Another four-way time interleaved high speed digital to analog converter 502 receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <1>, D <3>, D <5>, and D <7>, specifically: in the first latch, the rising edge of clk_1 (180 °) determines one side of Data D1, the falling edge of clk_2 (45 °) determines the other side of Data D1, thereby generating Data D1 (i.e., data <1 >), in the second latch, the rising edge of clk_1 (270 °) determines one side of Data D3, the falling edge of clk_2 (135 °) determines the other side of Data D3, thereby generating Data D3 (i.e., data <3 >), in the third latch, the rising edge of clk_1 (0 °) determines one side of Data D5, the falling edge of clk_2 (225 °) determines the other side of Data D5, thereby generating Data D5 (i.e., data <5 >), and in the fourth latch, the rising edge of clk_1 (90 °) determines one side of Data D7, the falling edge of clk_2 (315 °) determines the other side of Data D7, thereby generating Data D7 (i.e., data <7 >). The working principle of the four-way time-sequence interleaved high-speed digital-to- analog converters 501 and 502 is as described above, and will not be repeated here. Fig. 6 is a timing diagram of an eight-way timing interleaved high-speed digital-to-analog converter in one embodiment of the present application.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (7)
1. A four-way time interleaved high speed digital to analog converter comprising: the digital-to-analog conversion units comprise:
two differential sets of a plurality of latch modules, each latch module comprising: the first transistor to the sixth transistor, and the first and the second inverter, the gates of the first and the second transistors receive one input clock signal, the source of the first transistor is connected to the power supply terminal, the source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor receives one bit of input data, the sources of the third transistor are grounded, the drains of the first and the second transistors are connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the gate of the fifth transistor, the gates of the fourth and the sixth transistors receive the other input clock signal, the drains of the fourth and the fifth transistors are connected to the input terminal of the second inverter, the source of the fourth transistor is connected to the power supply terminal, the source of the fifth transistor is connected to the drain of the sixth transistor, and the source of the sixth transistor is connected to the ground terminal;
two differential sets of several conversion modules, each conversion module comprising: the grid electrodes of the seventh transistors are connected with the drains of the eighth transistors, the grid electrodes of the eighth transistors are connected with the output ends of the second inverters of the corresponding latch modules, and the source electrodes of the eighth transistors are connected with the ground.
2. The four-way time interleaved high speed digital to analog converter according to claim 1 wherein the set of several latch modules comprises four latch modules, a first latch module wherein the gates of the first and second transistors receive a 90 ° input clock signal and the gates of the fourth and sixth transistors receive a 0 ° input clock signal; in the second latch module, the gates of the first and second transistors receive a 180 ° input clock signal, and the gates of the fourth and sixth transistors receive a 90 ° input clock signal; in a third latch module, gates of the first and second transistors receive 270 ° input clock signals, and gates of the fourth and sixth transistors receive 180 ° input clock signals; in the fourth latch module, the gates of the first and second transistors receive a 0 ° input clock signal, and the gates of the fourth and sixth transistors receive a 270 ° input clock signal.
3. The four-way time interleaved high speed digital to analog converter according to claim 2 wherein in a first latch module the gate of the third transistor receives input data D <0>, in a second latch module the gate of the third transistor receives input data D <1>, in a third latch module the gate of the third transistor receives input data D <2>, and in a fourth latch module the gate of the third transistor receives input data D <3>.
4. The four-way time interleaved high speed digital to analog converter of claim 1 wherein said set of conversion modules comprises four conversion modules.
5. The four-way time interleaved high speed digital to analog converter of claim 1 further comprising: the power supply comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the power supply end, the other end of the first resistor is connected with the drain electrode of a seventh transistor of one group of a plurality of conversion modules, one end of the second resistor is connected with the power supply end, and the other end of the second resistor is connected with the drain electrode of a seventh transistor of the other group of a plurality of conversion modules.
6. The four-way time interleaved high speed digital to analog converter according to claim 1 wherein the first and fourth transistors are PMOS transistors and the second, third, fifth through eighth transistors are NMOS transistors.
7. An eight-way time-interleaved high-speed digital-to-analog converter, comprising:
the two four-way time-interleaved high-speed digital-to-analog converters as claimed in any one of claims 1 to 6, wherein one four-way time-interleaved high-speed digital-to-analog converter receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <0>, D <2>, D <4>, and D <6>, and the other four-way time-interleaved high-speed digital-to-analog converter also receives 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° input clock signals, and input data D <1>, D <3>, D <5>, and D <7>.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310109589.8A CN116054834B (en) | 2023-02-13 | 2023-02-13 | Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter |
| PCT/CN2024/076116 WO2024169748A1 (en) | 2023-02-13 | 2024-02-05 | Four-way or eight-way time-interleaved high-speed digital-to-analog converter |
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| CN202310109589.8A CN116054834B (en) | 2023-02-13 | 2023-02-13 | Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter |
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| CN117220649A (en) * | 2023-11-07 | 2023-12-12 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
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| US20070275676A1 (en) * | 2006-04-07 | 2007-11-29 | Broadcom Corporation, A California Corporation | DAC based switching power amplifier |
| CN102332922A (en) * | 2011-07-25 | 2012-01-25 | 复旦大学 | Current source and drive circuit for improving high frequency characteristic of digital analog converter |
| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN105162469A (en) * | 2015-03-24 | 2015-12-16 | 清华大学 | Synchronous latch register |
| US20170019122A1 (en) * | 2015-07-16 | 2017-01-19 | Semiconductor Components Industries, Llc | Digital-to-analog converter |
| CN115118283A (en) * | 2021-03-19 | 2022-09-27 | 晶晨半导体(上海)股份有限公司 | Current source drive circuit, analog-to-digital converter and receiver |
| CN113872574A (en) * | 2021-09-29 | 2021-12-31 | 南京邮电大学 | High-speed comparator applied to high-speed analog-to-digital converter |
| CN114710155A (en) * | 2022-04-13 | 2022-07-05 | 苏州迅芯微电子有限公司 | Logic control circuit for SAR analog-digital converter and SAR analog-digital converter |
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| CN117220649A (en) * | 2023-11-07 | 2023-12-12 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
| CN117220649B (en) * | 2023-11-07 | 2024-04-16 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
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| WO2024169748A1 (en) | 2024-08-22 |
| CN116054834B (en) | 2023-07-04 |
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