CN109921797B - Multi-channel digital-to-analog converter - Google Patents
Multi-channel digital-to-analog converter Download PDFInfo
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- CN109921797B CN109921797B CN201910055390.5A CN201910055390A CN109921797B CN 109921797 B CN109921797 B CN 109921797B CN 201910055390 A CN201910055390 A CN 201910055390A CN 109921797 B CN109921797 B CN 109921797B
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Abstract
The invention belongs to the technical field of electronics, and particularly relates to a multi-channel digital-to-analog converter which comprises m DAC conversion units, wherein each DAC conversion unit comprises: a signal input end for inputting an Nth input signal, wherein N belongs to [1, m ]; a clock input terminal for inputting an Nth clock signal; the logic operation module is used for obtaining a first logic signal according to the input signal and the clock signal and obtaining a second logic signal according to the input signal and the clock signal; the switch module is used for obtaining a first output signal according to the first logic signal and the current source and obtaining a second output signal according to a second logic signal and the current source; a first signal output terminal for outputting the first output signal; and the second signal output end is used for outputting the second output signal. The invention has the advantages of simple structure and capability of simultaneously processing a large amount of data.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a multi-channel digital-to-analog converter.
Background
In recent years, with the development of technologies such as software radio and cognitive radio, the demands for arbitrary synthesized waveforms in the industry and academia are increasing. Not only is a high sampling rate required, but also a need exists to provide multiple outputs. In response to these needs, signal sources based on a multi-DAC parallel structure are widely used, and the signal sources adopt a multi-DAC parallel structure to finally realize the output of multiple high-frequency signals. However, the increased number of DACs results in the synchronization of the multi-DAC parallel structure becoming more complicated. Therefore, it is urgent to find a synchronization method for realizing a multi-DAC parallel structure under the existing device conditions.
Digital-to-analog converters (DACs) are widely used in many fields such as audio and image signal processing, communication systems and industrial control as important interface circuits. With the rapid development of communication technology and microelectronic technology, designing a DAC with high speed, high precision and low power consumption has significant practical requirements and research values for improving data transmission quality and system performance.
Conventional DAC architectures typically implement multiple inputs using a multiplexer block MUX (MUX-DAC), or interpolate multiple differential signals by multi-channel data interpolation techniques to increase the rate for high speed applications. The prior art has the disadvantages of complex structure, high debugging difficulty, high cost and large error when forming multiple clocks.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a multi-channel digital-to-analog converter. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a multi-channel digital-to-analog converter, which comprises m DAC conversion units, wherein each DAC conversion unit comprises:
the DAC conversion unit includes: the circuit comprises a signal input end, a clock input end, a logic operation module, a switch module, a first signal output end and a second signal output end, wherein the signal input end and the clock input end are respectively connected with the input end connected with the logic operation module;
a signal input end for inputting an Nth input signal, wherein N belongs to [1, m ];
a clock input terminal for inputting an Nth clock signal;
the logic operation module is used for obtaining a first logic signal according to the input signal and the clock signal and obtaining a second logic signal according to the input signal and the clock signal;
the switch module is used for obtaining a first output signal according to the first logic signal and the current source and obtaining a second output signal according to a second logic signal and the current source respectively;
a first signal output terminal for outputting the first output signal;
and the second signal output end is used for outputting the second output signal.
In one embodiment of the present invention, the logical operation module includes:
the first logic conversion unit is used for obtaining a first logic signal according to the input signal and the clock signal;
and the second logic conversion unit is used for obtaining a second logic signal according to the input signal and the clock signal.
In one embodiment of the present invention, the first logic conversion unit includes: and the first input end of the first NAND gate is connected with the signal input end, the second input end of the first NAND gate is connected with the clock input end, and the output end of the first NAND gate is used for outputting the first logic signal.
In an embodiment of the present invention, the second logic converting unit includes a second nand gate and a not gate, the signal input terminal is connected to the first input terminal of the second nand gate through the not gate, the second input terminal of the second nand gate is connected to the clock input terminal, and the output terminal of the second nand gate is configured to output the second logic signal.
In one embodiment of the invention, the switch module comprises:
the first differential switch is used for receiving the first logic signal and the current source to obtain a first output signal;
and the second differential switch is used for receiving the second logic signal and the current source to obtain a second output signal.
In an embodiment of the present invention, the first differential switch and the second differential switch both use PMOS transistors.
In an embodiment of the present invention, a gate of the first differential switch is connected to an output terminal of the first logic converting unit, for receiving a first logic signal; the source electrode of the first differential switch is connected with the current source and used for providing a power supply for the circuit; the drain electrode of the first differential switch and the first signal output end are used for outputting a first output signal;
the grid electrode of the second differential switch is connected with the output end of the second logic conversion unit and used for receiving a second logic signal; the source electrode of the second differential switch is connected with the current source and used for providing a power supply for the circuit; and the drain electrode of the second differential switch and the second signal output end are used for outputting a second output signal.
In one embodiment of the present invention, further comprising: the input end of the buffer module is connected with the logic operation module, and the output end of the buffer module is connected with the switch module;
the buffer module is used for obtaining a first correction output signal according to the first logic signal and obtaining a second correction output signal according to the second logic signal.
In one embodiment of the present invention, the buffer module includes a first buffer unit and a second buffer unit;
the input end of the first buffer unit is connected with the output end of the first differential switch, and the output end of the first buffer unit is connected with the first signal output end and used for outputting the first correction output signal;
the input end of the second buffer unit is connected with the output end of the second differential switch, and the output end of the second buffer unit is connected with the second signal output end and used for outputting the second correction output signal.
In one embodiment of the present invention, the first buffer unit and the second buffer unit are both a plurality of inverters connected in series.
Compared with the prior art, the invention has the beneficial effects that:
the invention uses the multiphase clock and the two-stage circuit to process the multichannel input data, carries out small-scale logic operation through the multiphase clock and the multichannel input signal through the logic operation module, and controls the switch module through the logic signal output by the logic operation module.
Drawings
Fig. 1 is a schematic diagram of an apparatus structure of a multi-channel digital-to-analog converter according to an embodiment of the present invention;
fig. 2 is a functional schematic diagram of a multi-channel digital-to-analog converter according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a multi-channel digital-to-analog converter according to an embodiment of the present invention;
wherein: a logic operation module-1; a switch module-2; a buffer module-3; signal input terminal-4; clock input-5; a first signal output terminal-6; a second signal output terminal-7; a current source-Is.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
As shown in fig. 1, an embodiment of the present invention provides a multi-channel digital-to-analog converter, including m DAC conversion units,
the DAC conversion unit includes: the circuit comprises a signal input end 4, a clock input end 5, a logic operation module 1, a switch module 2, a first signal output end 6 and a second signal output end 7, wherein the signal input end and the clock input end are respectively connected with the input end connected with the logic operation module, the output end of the logic operation module is connected with the input end of the switch module, and the output end of the switch module circuit is connected with the first signal output end 6 and the second signal output end 7;
a signal input terminal 4 for inputting an nth input signal, N being [1, m ];
a clock input terminal 5 for inputting an nth clock signal;
the logic operation module 1 is used for obtaining a first logic signal according to the input signal and the clock signal and obtaining a second logic signal according to the input signal and the clock signal;
the switch module 2 Is used for obtaining a first output signal according to the first logic signal and the current source Is and obtaining a second output signal according to a second logic signal and the current source Is respectively;
a first signal output terminal 6 for outputting the first output signal;
a second signal output terminal 7 for outputting said second output signal.
Specifically, the multi-phase clock and the two-stage circuit are used for processing the multi-channel input data, the multi-phase clock and the multi-channel input signals are subjected to small-scale logic operation through the logic operation module, and the switch module is controlled through the logic signals output by the logic operation module.
In one embodiment of the present invention, the logical operation module 1 includes:
the first logic conversion unit is used for obtaining a first logic signal according to the input signal and the clock signal;
and the second logic conversion unit is used for obtaining a second logic signal according to the input signal and the clock signal.
In one embodiment of the present invention, the first logic conversion unit includes: and a first input end of the first nand gate is connected with the signal input end 4, a second input end of the first nand gate is connected with the clock input end 5, and an output end of the first nand gate is used for outputting the first logic signal.
In an embodiment of the present invention, the second logic converting unit includes a second nand gate and a not gate, the signal input terminal 4 is connected to a first input terminal of the second nand gate through the not gate, a second input terminal of the second nand gate is connected to the clock input terminal 5, and an output terminal of the second nand gate is configured to output the second logic signal.
In one embodiment of the invention, the switch module 2 comprises:
the first differential switch Is used for receiving the first logic signal and the current source Is to obtain a first output signal;
and the second differential switch Is used for receiving the second logic signal and the current source Is to obtain a second output signal.
In an embodiment of the present invention, the first differential switch and the second differential switch both use PMOS transistors.
In an embodiment of the present invention, a gate of the first differential switch is connected to an output terminal of the first logic converting unit, for receiving a first logic signal; the source electrode of the first differential switch Is connected with the current source Is and used for providing a power supply for the circuit; the drain of the first differential switch and the first signal output terminal 6 are used for outputting a first output signal;
the grid electrode of the second differential switch is connected with the output end of the second logic conversion unit and used for receiving a second logic signal; the source electrode of the second differential switch Is connected with the current source Is and used for providing a power supply for the circuit; and the drain of the second differential switch and the second signal output end 7 are used for outputting a second output signal.
As shown in fig. 2, in an embodiment of the present invention, the method further includes: the input end of the buffer module 3 is connected with the logic operation module, and the output end of the buffer module 3 is connected with the switch module 2;
the buffer module 3 is configured to obtain a first modified output signal according to the first logic signal, and obtain a second modified output signal according to the second logic signal.
In one embodiment of the present invention, the buffer module 3 includes a first buffer unit and a second buffer unit;
the input end of the first buffer unit is connected with the output end of the first differential switch, and the output end of the first buffer unit is connected with the first signal output end 6 and used for outputting the first correction output signal;
the input end of the second buffer unit is connected with the output end of the second differential switch, and the output end of the second buffer unit is connected with the second signal output end 7 and used for outputting the second correction output signal.
In one embodiment of the present invention, the first buffer unit and the second buffer unit are both a plurality of inverters connected in series.
Specifically, the buffer module 3 in the logic operation unit 1 can prevent the distortion of waveform transmission, and does not affect the logic while transmitting signals, and can also improve the driving capability and ensure the quality of signals and waveforms.
Specifically, in this embodiment, the first buffer and the second buffer each include two inverters connected in series, and the first buffer receives the first logic signal and outputs a first modified output signal; the second buffer receives the second logic signal and outputs a second modified output signal. The first buffer sends the first correction output signal to the first differential switch, and the first differential switch obtains a first output signal according to the first correction output signal and sends the first output signal to the first signal output end; the second buffer sends the second correction output signal to the second differential switch, and the second differential switch obtains a second output signal according to the second correction output signal and sends the second output signal to the second signal output end.
Specifically, each output of the logic operation module 1 of the DAC conversion unit is provided with a buffer module 3, the buffer module 3 can prevent waveform transmission distortion, and does not affect logic when transmitting signals, so that driving capability can be improved, and quality of signals and waveforms can be guaranteed.
Specifically, m is 4, the system has four DAC conversion units, the four clock signals CLK _ IN are CLK0_ IN, CLK1_ IN, CLK2_ IN, and CLK3_ IN, respectively, and are composed of a four-phase clock divider and a corresponding decoding circuit (IN other embodiments, a ring counter may be used), four sequential pulse signals are generated by frequency-dividing the input clock pulses CP by four, and only one pulse signal is at a high level IN any duty cycle of the clock pulses CP, as shown IN fig. 3. The input signals DATA _ IN inputted from the four signal input terminals 4 are DATA0_ IN, DATA1_ IN, DATA2_ IN, and DATA3_ IN, respectively. The four DAC conversion units have the same structure, and take one DAC conversion unit as an example: the input signal DATA _ IN is connected with the NOT gate to generate an inverted signal
The clock signal CLK _ IN is respectively connected to the second input terminal of the first NAND gate, DATA _ IN and
the first input end of the first NAND gate and the first input end of the second NAND gate are respectively connected, the output ends of the two NAND gates respectively output a first output signal PN and a second output signal NN, and the logic expression is as follows:
from the above logic expressions, when the clock signal CLK _ IN is 0, both the first output signal OUT _ P and the second output signal OUT _ N are 1; when the clock signal CLK _ IN is 1,
OUT _ N is DATA _ IN, producing a complementary output. That is, the arithmetic circuit of the clock signal CLK _ IN realizes the function of controlling the channel data transmission, which is represented by a clock high level transmission signal and a clock low level transmission 1. In any working period of the clock pulse CP, the input of one DAC conversion unit and the complementary signal thereof reach the output end, and the outputs of the other three channels are all 1. Since in any duty cycle of the clock pulse CP, there is and only one input and its complement to the output, the outputs of the remaining three channels are all 1. CLK0_ IN, CLK1_ IN, CLK2_ IN, and CLK3_ IN turn go high, so that the four channels sequentially transfer data.
Specifically, the four DAC conversion units have 4 pairs, 8 PMOS transistor switches M1 to M8, M1 and M2, M3 and M4, M5 and M6, and M7 and M8 are respectively 4 pairs of differential switches, and 4 groups of outputs of the logic operation module 1 correspond to 4 pairs of differential switches of the switch module 2 (4 groups of the logic operation module 1, 8 outputs respectively correspond to P0 and N0, P1 and N1, P2 and N2, P3 and N3, P4 and N4). At the same moment, the input signals of three pairs of switches in the four pairs of differential switches are 1, the PMOS tube Is turned off by high level, only one pair of differential switches are normally turned over depending on the signal change of the input channel, the current source Is controlled to generate complementary output, and the DAC function Is realized through the output of the first signal output end 6 and the second signal output end 7.
Specifically, four pairs of differential switches work periodically and sequentially, so that the function of processing multi-channel input data by the DAC is realized.
Specifically, each output of the logic operation module 1 of the DAC conversion unit is provided with a buffer module 3, the buffer module 3 can prevent waveform transmission distortion, and does not affect logic when transmitting signals, so that driving capability can be improved, and quality of signals and waveforms can be guaranteed.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A multi-channel digital-to-analog converter, characterized by: comprises m DAC conversion units, wherein the DAC conversion units,
the DAC conversion unit includes: the circuit comprises a signal input end (4), a clock input end (5), a logic operation module (1), a switch module (2), a first signal output end (6) and a second signal output end (7), wherein the signal input end and the clock input end are connected with the input end of the logic operation module, the output end of the logic operation module is connected with the input end of the switch module, and the output end of the switch module circuit is connected with the first signal output end (6) and the second signal output end (7); wherein the content of the first and second substances,
the signal input end (4) is used for receiving an Nth input signal, and N belongs to [1, m ]; input signals received by the signal input ends (4) of the m DAC conversion units form multi-channel input signals of the digital-to-analog converter;
the clock input end (5) is used for receiving an Nth clock signal; clock signals received by the clock input ends (5) of the m DAC conversion units form a multi-phase clock signal;
the logic operation module (1) is used for obtaining a first logic signal according to the input signal and the clock signal and obtaining a second logic signal according to the input signal and the clock signal; the logical operation module (1) comprises: the first logic conversion unit is used for obtaining a first logic signal according to the input signal and the clock signal; the second logic conversion unit is used for obtaining a second logic signal according to the input signal and the clock signal;
the switch module (2) Is used for obtaining a first output signal according to the first logic signal and the current source (Is) and obtaining a second output signal according to a second logic signal and the current source (Is); the switch module (2) comprises: a first differential switch and a second differential switch; the grid electrode of the first differential switch Is connected with the output end of the first logic conversion unit and used for receiving the first logic signal, the source electrode of the first differential switch Is connected with a current source (Is), and the drain electrode of the first differential switch forms the first signal output end (6); the grid electrode of the second differential switch Is connected with the output end of the second logic conversion unit and used for receiving the second logic signal, the source electrode of the second differential switch Is connected with the current source (Is), and the drain electrode of the second differential switch forms the second signal output end (7);
the first signal output terminal (6) is used for outputting the first output signal;
the second signal output terminal (7) is used for outputting the second output signal;
the first signal output ends (6) of the m DAC conversion units are connected together to form one output path of the digital-to-analog converter; and second signal output ends (7) of the m DAC conversion units are connected together to form the other path of output of the digital-to-analog converter.
2. A multi-channel digital-to-analog converter as claimed in claim 1, characterized in that: the first logic conversion unit includes: and a first input end of the first NAND gate is connected with the signal input end (4), a second input end of the first NAND gate is connected with the clock input end (5), and an output end of the first NAND gate is used for outputting the first logic signal.
3. A multi-channel digital-to-analog converter as claimed in claim 1, characterized in that: the second logic conversion unit comprises a second NAND gate and a NOT gate, the signal input end (4) is connected with the first input end of the second NAND gate through the NOT gate, the second input end of the second NAND gate is connected with the clock input end (5), and the output end of the second NAND gate is used for outputting the second logic signal.
4. A multi-channel digital-to-analog converter as claimed in claim 1, characterized in that: the first differential switch and the second differential switch both adopt PMOS tubes.
5. A multi-channel digital-to-analog converter as claimed in claim 1, characterized in that: further comprising: the input end of the buffer module (3) is connected with the logic operation module, and the output end of the buffer module (3) is connected with the switch module (2);
the buffer module (3) is used for obtaining a first correction output signal according to the first logic signal and obtaining a second correction output signal according to the second logic signal.
6. A multi-channel digital-to-analog converter as claimed in claim 5, characterized in that: the buffer module (3) comprises a first buffer unit and a second buffer unit;
the input end of the first buffer unit is connected with the output end of the first nand gate, and the output end of the first buffer unit is connected with the input end of the first differential switch and used for outputting the first correction output signal;
the input end of the second buffer unit is connected with the output end of the second nand gate, and the output end of the second buffer unit is connected with the input end of the second differential switch and used for outputting the second correction output signal.
7. A multi-channel digital-to-analog converter as claimed in claim 6, characterized in that: the first buffer unit and the second buffer unit are both a plurality of inverters connected in series.
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| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
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| CN108696278A (en) * | 2017-04-12 | 2018-10-23 | 华为技术有限公司 | A kind of digital analog converter |
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| JP4389981B2 (en) * | 2007-08-06 | 2009-12-24 | ソニー株式会社 | Solid-state imaging device, analog-digital conversion method of solid-state imaging device, and imaging device |
| US9203420B2 (en) * | 2014-02-05 | 2015-12-01 | Innophase Inc. | Apparatus and method for digital to analog conversion with current mirror amplification |
| CN105356884B (en) * | 2015-11-03 | 2018-08-17 | 南京天易合芯电子有限公司 | Sensor readout circuit based on quadrature Sigma-Delta analog-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
| CN108696278A (en) * | 2017-04-12 | 2018-10-23 | 华为技术有限公司 | A kind of digital analog converter |
| CN107947784A (en) * | 2017-10-20 | 2018-04-20 | 上海华力微电子有限公司 | A kind of high-performance output driving circuit |
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