CN111105746B - GOA unit, GOA circuit, display device and gate driving circuit - Google Patents
GOA unit, GOA circuit, display device and gate driving circuit Download PDFInfo
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- CN111105746B CN111105746B CN202010065678.3A CN202010065678A CN111105746B CN 111105746 B CN111105746 B CN 111105746B CN 202010065678 A CN202010065678 A CN 202010065678A CN 111105746 B CN111105746 B CN 111105746B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a GOA unit, a GOA circuit, a display device and a grid driving circuit, wherein the GOA unit comprises a first node control module, a second node control module, a third node control module, a fourth node control module and an output control module; the first node control module is used for controlling the potential of the first node, the second node control module is used for controlling the potential of the second node, the third node control module is used for controlling the potential of the third node, and the fourth node control module is used for controlling the potential of the fourth node; the output control module is used for outputting an output signal. The invention introduces a single clock signal, has simple time sequence control, does not occupy excessive signal output ends of ICs, controls output signals output by the output control unit through the third node and the fourth node, and realizes a narrow frame while ensuring GOA performance, thereby reducing production cost.
Description
Technical Field
The present invention relates generally to the field of display technologies, and in particular, to a GOA unit, a GOA circuit, a display device, and a gate driving circuit.
Background
With the development of display technology, GOA (Gate Driver on Array, array substrate row driving) technology is widely used. The gate switching circuit is integrated on the array substrate of the display device by using the GOA technology, so that a gate driving integrated circuit part can be omitted, and the high integration level and low cost of the display device are realized. Such a gate switching circuit integrated on the array substrate using the GOA technology is called a GOA circuit or a shift register circuit.
The GOA circuit comprises a plurality of GOA units, each GOA unit comprises a plurality of thin film transistors (Thin Film Transistor, abbreviated as TFTs), wherein the output end of each GOA unit is connected with a gate line. However, the number of clock signals adopted by the existing GOA circuit is large, and the time sequence control is complex; since the GOA circuit needs a large-scale integrated circuit (Integrated circuit, abbreviated as IC) to be implemented, each clock signal occupies one signal output terminal of the IC, so that the IC is larger, which is not beneficial to implementing a narrow frame.
Disclosure of Invention
In view of the foregoing drawbacks or shortcomings of the prior art, it is desirable to provide a GOA unit, a GOA circuit, a display device, and a gate driving circuit.
In a first aspect, the present invention provides a GOA unit comprising: the system comprises a first node control module, a second node control module, a third node control module, a fourth node control module and an output control module;
the first node control module is used for controlling the potential of the first node according to the single clock signal, the first scanning signal and the first level signal;
the second node control module is used for controlling the potential of a second node according to the first scanning signal, the second scanning signal, the first level signal and the second level signal;
the third node control module is used for controlling the potential of the third node according to the second scanning signal, the first level signal, the potential of the first node and the potential of the second node;
the fourth node control module is used for controlling the potential of a fourth node according to the potential of the second node, the potential of the third node, the first level signal and the second level signal;
the output control module is used for outputting an output signal according to the potential of the third node, the potential of the fourth node, the first level signal and the second level signal;
the polarity of the first level signal is the same as the polarity of the working level, and the polarity of the second level signal is opposite to the polarity of the working level.
Further, the first node control module comprises a first transistor, a second transistor and a first storage capacitor;
the control electrode of the first transistor is connected with the first scanning signal, the first electrode is connected with the single clock signal, and the second electrode is connected with the first node;
the control electrode of the second transistor is connected with the single clock signal, the first electrode is connected with the first node, and the second electrode is connected with the first level signal;
and a first end of the first storage capacitor is connected with the first node, and a second end of the first storage capacitor is connected with the first level signal.
Further, the second node control module comprises a third transistor, a fourth transistor and a second storage capacitor;
the control electrode of the third transistor is connected with the second scanning signal, the first electrode is connected with the second level signal, and the second electrode is connected with the second node;
the control electrode of the fourth transistor is connected with the first scanning signal, the first electrode is connected with the second node, and the second electrode is connected with the first level signal;
and a first end of the second storage capacitor is connected with the second node, and a second end of the second storage capacitor is connected with the first level signal.
Further, the third node control module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a third storage capacitor;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the single clock signal, and the second electrode is connected with the first electrode of the sixth transistor;
a control electrode of the sixth transistor is connected with the first node, and a second electrode of the sixth transistor is connected with the third node;
the control electrode of the seventh transistor is connected with the single clock signal, the first electrode is connected with the third node, and the second electrode is connected with the first level signal;
the control electrode of the eighth transistor is connected with the second scanning signal, the first electrode is connected with the first level signal, and the second electrode is connected with the third node;
and a first end of the third storage capacitor is connected with the third node, and a second end of the third storage capacitor is connected with the first level signal.
Further, the fourth node control module includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a fourth storage capacitor;
a first electrode of the ninth transistor is connected with a first end of the fourth storage capacitor, and a control electrode and a second electrode of the ninth transistor are connected with the first level signal;
the control electrode of the tenth transistor is connected with the third node, the first electrode is connected with the second level signal, and the second electrode is connected with the fourth node;
the control electrode of the eleventh transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with the second end of the fourth storage capacitor;
the control electrode of the twelfth transistor is connected with the first end of the fourth storage capacitor, the first electrode of the twelfth transistor is connected with the second end of the fourth storage capacitor, and the second electrode of the twelfth transistor is connected with the first level signal.
Further, the output control module includes a thirteenth transistor, a fourteenth transistor, and a fifth storage capacitor;
a control electrode of the thirteenth transistor is connected with the third node, a first electrode of the thirteenth transistor is connected with the first level signal, and a second electrode of the thirteenth transistor is connected with a first electrode of the fourteenth transistor;
the control electrode of the fourteenth transistor is connected with the fourth node, and the second electrode is connected with the first level signal;
the first end of the fifth storage capacitor is connected with the fourth node, the second end of the fifth storage capacitor is connected with the second pole of the thirteenth transistor, and the second end of the fifth storage capacitor is used for outputting the output signal.
Further, each transistor is a P-type transistor, and the working level is a low level signal; or alternatively, the process may be performed,
each transistor is an N-type transistor, and the working level is a high level signal.
In a second aspect, the present invention provides a GOA circuit comprising a plurality of cascaded GOA units as described above;
the first scanning signal input end of each stage of GOA unit is connected with the output signal output by the previous stage of GOA unit except the first stage of GOA unit;
the second scanning signal input end of each stage of GOA unit is connected with the output signal output by the next stage of GOA unit except the last stage of GOA unit.
In a third aspect, the present invention provides a display device comprising a GOA circuit as described above.
In a fourth aspect, the present invention provides a gate driving method for driving a GOA unit as described in any one of the above, comprising:
the first node control module controls the potential of the first node according to the single clock signal, the first scanning signal and the first level signal;
the second node control module controls the potential of the second node according to the first scanning signal, the second scanning signal, the first level signal and the second level signal;
the third node control module controls the potential of the third node according to the second scanning signal, the first level signal, the potential of the first node and the potential of the second node;
the fourth node control module controls the potential of the fourth node according to the potential of the second node, the potential of the third node, the first level signal and the second level signal;
the output control module outputs an output signal according to the potential of the third node, the potential of the fourth node, the first level signal and the second level signal;
the polarity of the first level signal is the same as the polarity of the working level, and the polarity of the second level signal is opposite to the polarity of the working level.
Further, in the first period, the polarity of the single clock signal is opposite to the polarity of the operation level, the polarity of the first scan signal is identical to the polarity of the operation level, the polarity of the second scan signal is opposite to the polarity of the operation level, the potential of the first node is opposite to the polarity of the operation level, the potential of the second node and the potential of the third node are both identical to the polarity of the operation level, the potential of the fourth node is opposite to the polarity of the operation level, and the polarity of the output signal is opposite to the polarity of the operation level;
in a second period, the polarity of the single clock signal is the same as the polarity of the working level, the polarity of the first scanning signal and the polarity of the second scanning signal are opposite to the polarity of the working level, the potential of the first node, the potential of the second node and the potential of the third node are the same as the polarity of the working level, the potential of the fourth node is opposite to the polarity of the working level, and the polarity of the output signal is opposite to the polarity of the working level;
in a third period, the polarity of the single clock signal is opposite to the polarity of the working level, the polarity of the first scanning signal and the polarity of the second scanning signal are opposite to the polarity of the working level, the potential of the first node and the potential of the second node are identical to the polarity of the working level, the potential of the third node is opposite to the polarity of the working level, the potential of the fourth node is identical to the polarity of the working level, and the polarity of the output signal is identical to the polarity of the working level;
in a fourth period, the polarity of the single clock signal is the same as the polarity of the operation level, the polarity of the first scan signal and the polarity of the second scan signal are opposite to the polarity of the operation level, the potential of the first node, the potential of the second node and the potential of the third node are the same as the polarity of the operation level, the potential of the fourth node is the same as the polarity of the operation level, and the polarity of the output signal is opposite to the polarity of the operation level;
in a fifth period, the polarity of the single clock signal is opposite to the polarity of the operation level, the polarity of the first scan signal is opposite to the polarity of the operation level, the polarity of the second scan signal is identical to the polarity of the operation level, the potential of the first node is identical to the polarity of the operation level, the potential of the second node is identical to the polarity of the operation level, the potential of the third node is identical to the polarity of the operation level, the potential of the fourth node is opposite to the polarity of the operation level, and the polarity of the output signal is opposite to the polarity of the operation level.
In the scheme, a single clock signal is introduced, the voltage of the first node, the second node, the third node and the fourth node is respectively controlled by the first node control module, the second node control module, the third node control module and the fourth node control module, the output signal output by the output control unit is controlled by the third node and the fourth node, the time sequence control is simple, the signal output end of excessive ICs is not occupied, the narrow frame is realized while the GOA performance is ensured, and the production cost is reduced.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a GOA unit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a GOA unit according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a gate driving method according to the present invention;
FIG. 4 is a timing diagram of the GOA unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole. In actual operation, the control electrode is a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The transistors adopted in the embodiment of the invention comprise a P-type transistor and an N-type transistor, wherein the P-type transistor is turned on when the grid is at a low level, and turned off when the grid is at a high level, and the working level of the P-type transistor is at a low level; the N-type transistor is turned on when the gate is at a high level, and turned off when the gate is at a low level, and the N-type transistor is operated at a high level.
As shown IN fig. 1, an embodiment of the present invention provides a GOA unit, which includes a single clock signal terminal CK, a first scanning signal input terminal IN1, a second scanning signal input terminal IN2, a first level signal terminal VG1, and a second level signal terminal VG2;
the single clock signal terminal CK provides a single clock signal;
the first scanning signal input end IN1 provides a gate driving signal of a previous stage GOA unit, and takes the gate driving signal of the previous stage GOA unit as a first scanning signal;
the second scanning signal input end IN2 provides a gate driving signal of the next-stage GOA unit, and the gate driving signal of the next-stage GOA unit is used as a second scanning signal;
the first level signal terminal VG1 inputs a first level signal;
the second level signal terminal VG2 inputs the second level signal.
As shown in fig. 1, a GOA unit provided by an embodiment of the present invention includes: a first node control module 101, a second node control module 102, a third node control module 103, a fourth node control module 104, and an output control module 105;
a first node control module 101 for controlling the potential of the first node N1 according to the single clock signal, the first scan signal, and the first level signal; optionally, as shown IN fig. 1, the first node control module 101 is connected to the single clock signal terminal CK, the first scanning signal input terminal IN1, the first level signal terminal VG1, and the first node N1, and is configured to control the potential of the first node N1 according to the first level signal and the single clock signal under the control of the single clock signal and the first scanning signal;
a second node control module 102, configured to control the potential of the second node N2 according to the first scan signal, the second scan signal, the first level signal, and the second level signal; optionally, as shown IN fig. 1, the second node control module 102 is connected to the first scan signal input terminal IN1, the second scan signal input terminal IN2, the first level signal terminal VG1 and the second level signal terminal VG2, and is configured to control the potential of the second node N2 according to the first level signal and the second level signal under the control of the first scan signal and the second scan signal;
a third node control module 103 for controlling the potential of the third node N3 according to the second scan signal, the first level signal, the potential of the first node, and the potential of the second node; optionally, as shown IN fig. 1, the third node control module 103 is connected to the second node N2, the third node N3, the single clock signal terminal CK, the second scan signal input terminal IN2, the first level signal terminal VG1, and is configured to control the potential of the third node N3 according to the single clock signal and the first level signal under the control of the potential of the first node N1, the potential of the second node N2, and the single clock signal;
a fourth node control module 104, configured to control the potential of the fourth node N4 according to the potential of the second node N2, the potential of the third node N3, the first level signal, and the second level signal; optionally, as shown in fig. 1, the fourth node control module 104 is connected to the second node N2, the third potential N3, the first level signal end VG1 and the second level signal VG2, and is configured to control the potential of the fourth node N4 according to the first level signal and the second level signal under the control of the potential of the second node N2, the potential of the third node N3 and the first level signal;
an output control module 105 for outputting an output signal according to the potential of the third node N3, the potential of the fourth node N4, the first level signal, and the second level signal; optionally, as shown in fig. 1, the output control module 105 is connected to the third node N3, the fourth node N4, the first level signal end VG1, and the second level signal end VG2, and is configured to control the potential of the signal output end Out under the control of the potential of the third node N3 and the potential of the fourth node N4, where the output signal output by the signal output end Out is the gate driving signal of the present-stage GOA unit;
the polarity of the signal input by the first level signal terminal VG1 is the same as the polarity of the operating level, and the polarity of the signal input by the second level signal terminal VG2 is opposite to the polarity of the operating level.
The GOA unit provided by the embodiment only comprises one clock signal, so that the time sequence control is simple, the number of occupied IC signal output ends can be reduced, and the implementation of a narrow frame is facilitated.
In some alternative embodiments, as shown in fig. 2, the first node control module 101 includes a first transistor T1, a second transistor T2, and a first storage capacitor C1; the control electrode of the first transistor T1 is connected with a first scanning signal, the first electrode is connected with a single clock signal, and the second electrode is connected with a first node N1; the control electrode of the second transistor T2 is connected with a single clock signal, the first electrode is connected with the first node N1, and the second electrode is connected with a first level signal; the first end of the first storage capacitor C1 is connected with the first node N1, and the second end is connected with a first level signal.
In some alternative embodiments, as shown in fig. 2, the second node control module 102 includes a third transistor T3, a fourth transistor T4, and a second storage capacitor C2; the control electrode of the third transistor T3 is connected with a second scanning signal, the first electrode is connected with a second level signal, and the second electrode is connected with a second node N2; the control electrode of the fourth transistor T4 is connected with a first scanning signal, the first electrode is connected with a second node N2, and the second electrode is connected with a first level signal; the first end of the second storage capacitor C2 is connected with the second node N2, and the second end is connected with the first level signal.
In some alternative embodiments, as shown in fig. 2, the third node control module 103 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third storage capacitor C3; the control electrode of the fifth transistor T5 is connected with the second node, the first electrode is connected with a single clock signal, and the second electrode is connected with the first electrode of the sixth transistor T6; the control electrode of the sixth transistor T6 is connected with the first node, and the second electrode is connected with the third node N3; the control electrode of the seventh transistor T7 is connected with a single clock signal, the first electrode is connected with the third node N3, and the second electrode is connected with a first level signal; the control electrode of the eighth transistor T8 is connected with a second scanning signal, the first electrode is connected with a first level signal, and the second electrode is connected with a third node N3; the first end of the third storage capacitor C3 is connected with the third node, and the second end is connected with the first level signal.
In some alternative embodiments, as shown in fig. 2, the fourth node control module 104 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a fourth storage capacitor C4; a first pole of the ninth transistor T9 is connected with a first end of the fourth storage capacitor C4, and a control pole and a second pole are connected with a first level signal; the control electrode of the tenth transistor T10 is connected with the third node, the first electrode is connected with a second level signal, and the second electrode is connected with the fourth node N4; the control electrode of the eleventh transistor T11 is connected with the second node N2, the first electrode is connected with the fourth node N4, and the second electrode is connected with the second end of the fourth storage capacitor C4; the control electrode of the twelfth transistor T12 is connected to the first end of the fourth storage capacitor C4, the first electrode is connected to the second end of the fourth storage capacitor C4, and the second electrode is connected to the first level signal.
In some alternative embodiments, as shown in fig. 2, the output control module 105 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifth storage capacitor C5; the control electrode of the thirteenth transistor T13 is connected with the third node N3, the first electrode is connected with the first level signal, and the second electrode is connected with the first electrode of the fourteenth transistor T14; the control electrode of the fourteenth transistor T14 is connected with the fourth node N4, and the second electrode is connected with a first level signal; the first end of the fifth storage capacitor C5 is connected to the fourth node N4, the second end is connected to the second pole of the thirteenth transistor T13, and the second end of the fifth storage capacitor C5 is used for outputting an output signal.
In this embodiment, each of the transistors is a P-type transistor, and the operation level is a low level signal. At this time, the first level signal terminal VG1 inputs the low level signal of the first level signal, i.e. the first level signal terminal VG1 is the low level signal terminal VGL; correspondingly, the second level signal input by the second level signal terminal VG2 is a high level signal, i.e. the second level signal terminal VG2 is a high level signal terminal VGH. The working principle of the GOA unit is described with specific reference to the following working process.
As shown in fig. 3, an embodiment of the present invention further provides a gate driving method for driving the GOA unit in the foregoing embodiment, where the method includes:
step 201, a first node control module controls the potential of a first node according to a single clock signal, a first scanning signal and a first level signal;
step 202, a second node control module controls the potential of a second node according to a first scanning signal, a second scanning signal, a first level signal and a second level signal;
step 203, the third node control module controls the potential of the third node according to the second scan signal, the first level signal, the potential of the first node, and the potential of the second node;
step 204, the fourth node control module controls the potential of the fourth node according to the potential of the second node, the potential of the third node, the first level signal and the second level signal;
in step 205, the output control module outputs an output signal according to the potential of the third node, the potential of the fourth node, the first level signal and the second level signal.
The method specifically includes, in combination with fig. 4, that the first level signal terminal VGL continuously inputs a low level signal and the second level signal terminal VGH continuously inputs a high level signal:
IN the first period P1, the single clock signal input by the single clock signal terminal CK is a high level signal, the first scan signal input by the first scan signal input terminal IN1 is a low level signal, the second scan signal input by the second scan signal input terminal IN2 is a high level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first node N1 is at a high potential; the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the second node N2 is at a low potential; the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, the seventh transistor T7 is turned off, the eighth transistor T8 is turned off, the third node N3 is at a low potential, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the ninth transistor T9 is turned on, the twelfth transistor T12 is turned off, and the fourth node N4 is at a high potential; the thirteenth transistor T13 is turned on, and the signal output terminal Out outputs the same high level signal as the second level signal through the thirteenth transistor T13.
IN the second period P2, the single clock signal terminal CK inputs a low level signal, the first scan signal input terminal IN1 and the second scan signal input terminal IN2 both input a high level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first node N1 becomes a low potential; the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the second node N2 maintains a low potential; the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, the third node N3 maintains a low potential, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, and the fourth node N4 is a high potential; the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and the signal output terminal Out outputs the same high level signal as the second level signal through the thirteenth transistor T13.
IN the third period P3, the single clock signal terminal CK, the first scan signal input terminal IN1, and the second scan signal input terminal IN2 all input high level signals, the first transistor T1 is turned off, the second transistor T2 is turned off, and the first node N1 maintains a low potential; the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the second node N2 maintains a low potential; the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned off, and the third node N3 becomes a high potential; the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, the ninth transistor T9 is turned on, the twelfth transistor T12 is turned on, and the fourth node becomes a low potential; the thirteenth transistor T13 is turned off and the fourteenth transistor T14 is turned on, and the signal output terminal Out outputs the same low level signal as the first level signal through the fourteenth transistor T14.
IN the fourth period P4, the single clock signal terminal CK inputs a low level signal, the first scan signal input terminal IN1 and the second scan signal input terminal IN2 all input a high level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first node N1 maintains a low potential; the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the second node N2 maintains a low potential; the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, and the third node N3 becomes a low potential; the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the ninth transistor T9 is turned on, the twelfth transistor T12 is turned off, and the fourth node becomes a high potential; the thirteenth transistor T13 is turned on and the fourteenth transistor T14 is turned off, and the signal output terminal Out outputs the same high level signal as the second level signal through the thirteenth transistor T13.
IN the fifth period P5, the single clock signal terminal CK inputs a high level signal, the first scan signal input terminal IN1 inputs a high level signal, the second scan signal input terminal IN2 inputs a low level signal, the first transistor T1 is turned off, the second transistor T2 is turned off, and the first node N1 maintains a low potential; the third transistor T3 is turned on and the fourth transistor T4 is turned off, and the second node N2 becomes a high potential; the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, and the third node N3 maintains a low potential; the tenth transistor T10 is turned on, the eleventh transistor T11 is turned off, and the fourth node becomes a high potential; the signal output terminal Out outputs the same high level signal as the second level signal through the thirteenth transistor T13.
In this embodiment, the clock period of the single clock signal output by the single clock signal terminal CK is used as the period of the GOA unit, which only includes one clock signal, so that the time sequence control difficulty is simplified, the signal output terminal of the IC is not occupied, the IC is reduced, and the effect of a narrow frame is achieved.
The embodiment of the invention also provides a GOA circuit, as shown in fig. 5, which comprises a plurality of cascaded GOA units;
the first scanning signal input end IN1 of each stage of GOA unit is connected with an output signal output by a previous stage of GOA unit except for the first stage of GOA unit;
the second scanning signal input terminal IN2 of each stage of GOA unit is connected to the output signal of the next stage of GOA unit except the last stage of GOA unit.
The reference numeral G (n) denotes an n-th stage GOA unit of the GOA circuit, the reference numeral G (n-1) denotes an n-1-th stage GOA unit of the GOA circuit, the reference numeral G (n+1) denotes an n+1-th stage GOA unit of the GOA circuit, and n is an integer greater than 1. The input IN1 of G (n) is coupled to the output Out (n-1) of the n-1 th GOA unit, and the input IN2 of G (n) is coupled to the output Out (n+1) of the n+1 th GOA unit.
The embodiment of the invention also provides a display device which comprises the GOA circuit, has simple time sequence control and can realize a narrow frame.
The display device may be: electronic paper, organic Light-Emitting Diode (OLED) display device, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, and any other product or component with display function.
The above description is only illustrative of the preferred embodiments of the present invention and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.
Claims (10)
1. A GOA unit, comprising: the system comprises a first node control module, a second node control module, a third node control module, a fourth node control module and an output control module;
the first node control module is used for controlling the potential of the first node according to the single clock signal, the first scanning signal and the first level signal;
the second node control module is used for controlling the potential of a second node according to the first scanning signal, the second scanning signal, the first level signal and the second level signal;
the third node control module is used for controlling the potential of the third node according to the second scanning signal, the first level signal, the potential of the first node and the potential of the second node;
the fourth node control module is used for controlling the potential of a fourth node according to the potential of the second node, the potential of the third node, the first level signal and the second level signal;
the output control module is used for outputting an output signal according to the potential of the third node, the potential of the fourth node, the first level signal and the second level signal;
the polarity of the first level signal is the same as the polarity of the working level, and the polarity of the second level signal is opposite to the polarity of the working level.
2. The GOA unit of claim 1, wherein the first node control module comprises a first transistor, a second transistor, and a first storage capacitor;
the control electrode of the first transistor is connected with the first scanning signal, the first electrode is connected with the single clock signal, and the second electrode is connected with the first node;
the control electrode of the second transistor is connected with the single clock signal, the first electrode is connected with the first node, and the second electrode is connected with the first level signal;
and a first end of the first storage capacitor is connected with the first node, and a second end of the first storage capacitor is connected with the first level signal.
3. The GOA unit of claim 1, wherein the second node control module comprises a third transistor, a fourth transistor, and a second storage capacitor;
the control electrode of the third transistor is connected with the second scanning signal, the first electrode is connected with the second level signal, and the second electrode is connected with the second node;
the control electrode of the fourth transistor is connected with the first scanning signal, the first electrode is connected with the second node, and the second electrode is connected with the first level signal;
and a first end of the second storage capacitor is connected with the second node, and a second end of the second storage capacitor is connected with the first level signal.
4. The GOA unit of claim 1, wherein the third node control module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a third storage capacitor;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the single clock signal, and the second electrode is connected with the first electrode of the sixth transistor;
a control electrode of the sixth transistor is connected with the first node, and a second electrode of the sixth transistor is connected with the third node;
the control electrode of the seventh transistor is connected with the single clock signal, the first electrode is connected with the third node, and the second electrode is connected with the first level signal;
the control electrode of the eighth transistor is connected with the second scanning signal, the first electrode is connected with the first level signal, and the second electrode is connected with the third node;
and a first end of the third storage capacitor is connected with the third node, and a second end of the third storage capacitor is connected with the first level signal.
5. The GOA unit of claim 1, wherein the fourth node control module comprises a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a fourth storage capacitor;
a first electrode of the ninth transistor is connected with a first end of the fourth storage capacitor, and a control electrode and a second electrode of the ninth transistor are connected with the first level signal;
the control electrode of the tenth transistor is connected with the third node, the first electrode is connected with the second level signal, and the second electrode is connected with the fourth node;
the control electrode of the eleventh transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with the second end of the fourth storage capacitor;
the control electrode of the twelfth transistor is connected with the first end of the fourth storage capacitor, the first electrode of the twelfth transistor is connected with the second end of the fourth storage capacitor, and the second electrode of the twelfth transistor is connected with the first level signal.
6. The GOA unit of claim 1, wherein the output control module comprises a thirteenth transistor, a fourteenth transistor, and a fifth storage capacitor;
a control electrode of the thirteenth transistor is connected with the third node, a first electrode of the thirteenth transistor is connected with the first level signal, and a second electrode of the thirteenth transistor is connected with a first electrode of the fourteenth transistor;
the control electrode of the fourteenth transistor is connected with the fourth node, and the second electrode is connected with the first level signal;
the first end of the fifth storage capacitor is connected with the fourth node, the second end of the fifth storage capacitor is connected with the second pole of the thirteenth transistor, and the second end of the fifth storage capacitor is used for outputting the output signal.
7. GOA circuit comprising a plurality of cascaded GOA units as claimed in any one of claims 1 to 6;
the first scanning signal input end of each stage of GOA unit is connected with the output signal output by the previous stage of GOA unit except the first stage of GOA unit;
the second scanning signal input end of each stage of GOA unit is connected with the output signal output by the next stage of GOA unit except the last stage of GOA unit.
8. A display device comprising the GOA circuit of claim 7.
9. A gate driving method for driving the GOA unit of any one of claims 1-6, comprising:
the first node control module controls the potential of the first node according to the single clock signal, the first scanning signal and the first level signal;
the second node control module controls the potential of the second node according to the first scanning signal, the second scanning signal, the first level signal and the second level signal;
the third node control module controls the potential of the third node according to the second scanning signal, the first level signal, the potential of the first node and the potential of the second node;
the fourth node control module controls the potential of the fourth node according to the potential of the second node, the potential of the third node, the first level signal and the second level signal;
the output control module outputs an output signal according to the potential of the third node, the potential of the fourth node, the first level signal and the second level signal;
the polarity of the first level signal is the same as the polarity of the working level, and the polarity of the second level signal is opposite to the polarity of the working level.
10. The gate driving method according to claim 9, comprising:
in a first period, the polarity of the single clock signal is opposite to the polarity of the working level, the polarity of the first scanning signal is the same as the polarity of the working level, the polarity of the second scanning signal is opposite to the polarity of the working level, the potential of the first node is opposite to the polarity of the working level, the potential of the second node and the potential of the third node are both the same as the polarity of the working level, the potential of the fourth node is opposite to the polarity of the working level, and the polarity of the output signal is opposite to the polarity of the working level;
in a second period, the polarity of the single clock signal is the same as the polarity of the working level, the polarity of the first scanning signal and the polarity of the second scanning signal are opposite to the polarity of the working level, the potential of the first node, the potential of the second node and the potential of the third node are the same as the polarity of the working level, the potential of the fourth node is opposite to the polarity of the working level, and the polarity of the output signal is opposite to the polarity of the working level;
in a third period, the polarity of the single clock signal is opposite to the polarity of the working level, the polarity of the first scanning signal and the polarity of the second scanning signal are opposite to the polarity of the working level, the potential of the first node and the potential of the second node are identical to the polarity of the working level, the potential of the third node is opposite to the polarity of the working level, the potential of the fourth node is identical to the polarity of the working level, and the polarity of the output signal is identical to the polarity of the working level;
in a fourth period, the polarity of the single clock signal is the same as the polarity of the operation level, the polarity of the first scan signal and the polarity of the second scan signal are opposite to the polarity of the operation level, the potential of the first node, the potential of the second node and the potential of the third node are the same as the polarity of the operation level, the potential of the fourth node is the same as the polarity of the operation level, and the polarity of the output signal is opposite to the polarity of the operation level;
in a fifth period, the polarity of the single clock signal is opposite to the polarity of the operation level, the polarity of the first scan signal is opposite to the polarity of the operation level, the polarity of the second scan signal is identical to the polarity of the operation level, the potential of the first node is identical to the polarity of the operation level, the potential of the second node is identical to the polarity of the operation level, the potential of the third node is identical to the polarity of the operation level, the potential of the fourth node is opposite to the polarity of the operation level, and the polarity of the output signal is opposite to the polarity of the operation level.
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| CN105702295B (en) * | 2016-01-15 | 2019-06-14 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display panel and display device |
| CN105741741B (en) * | 2016-04-29 | 2018-10-23 | 北京京东方显示技术有限公司 | Gate driving circuit and its driving method, display base plate and display device |
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| CN110322843B (en) * | 2019-07-23 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | GOA unit, GOA circuit and display panel |
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