CN115361017B - Clock skew calibration circuit based on phase interpolator - Google Patents

Clock skew calibration circuit based on phase interpolator Download PDF

Info

Publication number
CN115361017B
CN115361017B CN202211065860.4A CN202211065860A CN115361017B CN 115361017 B CN115361017 B CN 115361017B CN 202211065860 A CN202211065860 A CN 202211065860A CN 115361017 B CN115361017 B CN 115361017B
Authority
CN
China
Prior art keywords
phase
unit
delay
clock signal
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202211065860.4A
Other languages
Chinese (zh)
Other versions
CN115361017A (en
Inventor
罗鲍
蔡敏卿
李承哲
钟英权
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiyiwei Semiconductor Shanghai Co ltd
Original Assignee
Jiyiwei Semiconductor Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiyiwei Semiconductor Shanghai Co ltd filed Critical Jiyiwei Semiconductor Shanghai Co ltd
Priority to CN202211065860.4A priority Critical patent/CN115361017B/en
Publication of CN115361017A publication Critical patent/CN115361017A/en
Application granted granted Critical
Publication of CN115361017B publication Critical patent/CN115361017B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error

Abstract

The application discloses a clock skew calibration circuit based on phase interpolator, it includes: a bias voltage generating circuit for generating a leading phase and a lagging phase control signal according to the output of the digital-to-analog conversion circuit; at least one stage of delay control circuit, each stage includes a phase lead unit, a first delay unit, a phase lag unit, a second delay unit, and a connection unit. The phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the advancing phase and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connection unit, and the connection unit outputs to the second delay unit, the subordinate phase advancing unit and the first delay unit. The second delay unit receives the connection unit output and outputs a second delayed clock signal to the phase lag unit, receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase and lag phase control signals.

Description

Clock skew calibration circuit based on phase interpolator
Technical Field
The present invention relates generally to the field of integrated circuits, and more particularly, to a clock skew calibration circuit based on a phase interpolator.
Background
Analog-to-digital converters (ADCs) for Time Interleaving (TI) have been widely employed in high-speed communication systems to achieve accurate data recovery with reasonable power consumption. The TI architecture takes advantage of the power efficient sub-ADC by relaxing the operating speed of each channel, while its inherent channel mismatch (offset), gain and skew errors limit the overall ADC performance. In addition, as the ADC conversion speed reaches 50GHz or more, even in the most advanced process technology, a single-phase high-frequency clock source cannot be driven as a sampling clock for each channel ADC. Thus, recent ultra-high speed ADCs generate sampling phases from multiple master clock sources (i.e., differential phase or quadrature phase clock sources) having different phases, which introduces significant skew errors in the TI ADC.
Disclosure of Invention
The invention aims to provide a clock skew calibration circuit based on a phase interpolator, which is used for calibrating skew errors among a plurality of sampling clocks, and the clock skew calibration circuit is easy to design, has small area cost and has small power due to small parasitic.
The application discloses clock skew calibration circuit based on phase interpolator includes:
a bias voltage generation circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog conversion circuit;
at least one stage of delay control circuit, each stage of delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then is connected with the phase lead unit and the first delay unit in parallel; the phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connection unit, and the connection unit outputs to the second delay unit and the phase advancing unit and the first delay unit of a next stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the phase lag unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
In a preferred embodiment, the phase advancing unit and the phase retarding unit each include: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the grid electrode of the first PMOS transistor is connected to the advanced phase control signal, the source electrode of the first PMOS transistor is connected to the power supply end, and the drain electrode of the first PMOS transistor is connected to the source electrode of the second PMOS transistor; the grid electrode of the first NMOS transistor is connected to the hysteresis phase control signal, the source electrode of the first NMOS transistor is connected to the ground terminal, and the drain electrode of the first NMOS transistor is connected to the source electrode of the second NMOS transistor; the gates of the second PMOS transistor and the second NMOS transistor are connected as a clock signal input end, and the drains of the second PMOS transistor and the second NMOS transistor are connected as a clock signal output end.
In a preferred embodiment, parameters between the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor in the delay control circuit of each stage are different to obtain different phase-advanced or phase-retarded clock signals.
In a preferred embodiment, the parameters include channel width and length of the transistor.
In a preferred embodiment, the bias voltage generating circuit includes third to fifth PMOS transistors, third to fourth NMOS transistors, and first and second resistors, sources of the third to fifth PMOS transistors being connected to a power supply terminal, gates of the third and fourth PMOS transistors being connected and connected to the digital-to-analog conversion circuit, drains of the fourth PMOS transistors outputting the retard phase control signal and being connected to one end of the first resistor, and gates of the third and fourth NMOS transistors, another end of the first resistor being connected to a drain of the third NMOS transistor, a drain of the fifth PMOS transistor being connected to one end of the second resistor, a gate of the fifth NMOS transistor being connected to another end of the second resistor and a drain of the fourth NMOS transistor and outputting the advance phase control signal.
In a preferred embodiment, the first delay unit includes an inverter having an input connected to the input clock signal and an output connected to the connection unit.
In a preferred embodiment, the second delay unit comprises an inverter, an input of which is connected to the connection unit and an output of which is connected to an input of the phase lag unit.
The application also discloses a clock skew calibration circuit based on phase interpolator, including:
a bias voltage generation circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog conversion circuit;
a plurality of clock delay control branches, each clock delay control branch having at least one stage of delay control circuit, each stage of delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then is connected with the phase lead unit and the first delay unit in parallel; the phase advancing unit receives one input clock signal in the multipath input clock signals and outputs a phase advancing clock signal to the connecting unit according to the advancing phase control signal and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connecting unit, and the connecting unit outputs the first delay clock signal to the second delay unit and the phase advancing unit and the first delay unit of a next-stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the lag phase unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
In a preferred embodiment, the clock skew calibration circuit includes 12 clock delay control branches.
Compared with the prior art, the clock skew calibration circuit based on the connection unit has at least the following beneficial effects:
the application provides a novel delay control circuit based on phase interpolation. In the conventional delay unit, the delay is controlled by changing the driving capability (gm) or the load (capacitance) of the delay unit. The circuit proposed in the present application is composed of an N-bit current digital-to-analog conversion circuit (IDAC), a bias voltage generation circuit, and a delay control circuit. IDAC can adjust the earlier phase (phase lead) path and the later phase (phase lag) path output impedance by the bias voltage generation circuit changing the bias voltage so that the output clock edges can be sharper or slower. Compared with other structures such as a trimming capacitor, the structure is easy to design, has small area cost and small power due to small parasitic. And the jitter contribution and power consumption of the calibration circuit module are dynamically adjusted according to the specific clock skew error magnitude, i.e. the circuit proposed in the present application produces minimum jitter and consumes minimum current when there is minimum mismatch.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a schematic diagram of phase interpolator based delay control in one embodiment of the present application.
Fig. 2 is a circuit diagram of clock skew calibration based on a phase interpolator in one embodiment of the present application.
Fig. 3 is a circuit diagram of a phase lead unit and a phase lag unit in one embodiment of the present application.
Fig. 4 is a circuit diagram of a bias voltage generating circuit in one embodiment of the present application.
FIG. 5 is a schematic diagram of clock skew calibration circuit output as a function of digital to analog conversion circuit output current in one embodiment of the present application.
Fig. 6 is a schematic diagram of mismatch and jitter of several clock delay control branches in one embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a phase interpolator based delay control circuit in one embodiment, comprising: the phase advancing unit 101, the first delay unit 102, the phase retarding unit 103, the second delay unit 104, and the connection unit 105 constitute a phase interpolator, and the phase advancing unit 101, the first delay unit 102, the phase retarding unit 103, the second delay unit 104, and the connection unit 105. The phase lag unit 103 is connected in series with the second delay unit 104 and then connected in parallel with the phase lead unit 101 and the first delay unit 102. The phase advancing unit 101 outputs a phase advancing clock signal to the connection unit 105, the first delay unit 102 receives the input clock signal and outputs a first delay clock signal to the connection unit 105, and the connection unit 105 outputs to the second delay unit 104. The second delay unit 104 receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit 103, and the phase lag unit 103 receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit 105. The connection unit 105 receives signals input from the phase advancing unit 101, the first delaying unit 102 and the phase retarding unit 103, and mixes and connects the different input signals together to generate a new output. The connection unit 105 may be physically implemented by a metal connection line.
IN one embodiment, the first delay unit 102 includes an inverter having an input connected to the input clock signal IN and an output connected to the connection unit 105.
In one embodiment, the second delay unit 104 comprises an inverter, the input of which is connected to the connection unit 105 and the output of which is connected to the input of the phase lag unit 103.
Fig. 2 shows a circuit diagram of a phase interpolator based clock skew calibration circuit in one embodiment. The clock skew calibration circuit includes a bias voltage generation circuit 206, at least one stage of delay control circuit. The delay control circuit may be the circuit of fig. 1, with two stages of delay control circuits 208, 208' shown in fig. 2. The bias voltage generating circuit 206 generates a leading phase control signal BSP and a lagging phase control signal BSN from an output BSIN of a digital-to-analog conversion circuit (not shown). The delay control circuit 208, 208' of each stage includes: phase lead units 201,201', first delay units 202,202', phase lag units 203,203', second delay units 204,204', and connection units. The phase lag units 203,203 are connected in series with the second delay units 204,204' and then connected in parallel with the phase lead units 201,201' and the first delay units 202,202 '. The phase advancing unit 201 receives an input clock signal IN and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal BSP and the retarding phase control signal BSN, and the first delay unit 202 receives the input clock signal and outputs a first delay clock signal to the connection unit, which outputs to the second delay unit 203 and the phase advancing unit 201' and the first delay unit 202' of the next-stage delay control circuit 208'. The second delay unit 203 receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit 204, and the phase lag unit 204 receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal BSP and the lag phase control signal BSN.
Fig. 3 shows a circuit diagram of a phase lead unit and a phase lag unit in one embodiment. The phase advancing unit and the phase retarding unit each include: a first PMOS transistor P1, a first NMOS transistor N1, a second PMOS transistor P2, and a second NMOS transistor N2. The gate of the first PMOS transistor P1 is connected to the advanced phase control signal BSP, the source is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor N2. The gate of the first NMOS transistor N1 is connected to the retard phase control signal BSN, the source is connected to the ground, and the drain is connected to the source of the second NMOS transistor N2. The gates of the second PMOS transistor P2 and the second NMOS transistor N2 are connected as a clock signal input terminal IN, and the drains of the second PMOS transistor P2 and the second NMOS transistor N2 are connected as a clock signal output terminal OUT.
In one embodiment, parameters between the first PMOS transistor P1, the first NMOS transistor N1, the second PMOS transistor P2, and the second NMOS transistor N2 in the delay control circuit of each stage are different to obtain different phase-advanced or phase-retarded clock signals. In one embodiment, the parameters include channel width and length of the transistor.
Fig. 4 shows a circuit diagram of a bias voltage generating circuit in one embodiment. The bias voltage generating circuit comprises a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, a first resistor R1 and a second resistor R2, wherein the sources of the third PMOS transistor P3, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected to a power supply end, the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the digital-to-analog conversion circuit, the drain of the fourth PMOS transistor P4 outputs the hysteresis phase control signal BSN and is connected to one end of the first resistor R1, the gates of the third NMOS transistor N3 and the gates of the fourth NMOS transistor N4, the other end of the first resistor R1 is connected to the drain of the third NMOS transistor N3, the drain of the fifth PMOS transistor N5 is connected to one end of the second resistor R2, and the drain of the fifth NMOS transistor N5 is connected to the other end of the second NMOS transistor N2 and the lead phase control signal BSN is connected to the other end of the fourth NMOS transistor N2.
The IDAC in this embodiment adjusts the output impedance of the earlier phase (phase lead) path and the later phase (phase lag) path by changing the bias voltage by the bias voltage generation circuit, so that the output clock edge can be sharper or slower. Fig. 5 shows the variation of the clock skew calibration circuit output OUT shown In fig. 2 with the digital-to-analog conversion circuit output current BSIN, where Ip is the phase lag control current and In is the phase lead control current, in one embodiment.
Still another embodiment of the present application discloses a clock skew calibration circuit based on a phase interpolator, including: the bias voltage generating circuit and a plurality of clock delay control branches. In one embodiment, the clock skew calibration circuit includes 12 clock delay control branches. The bias voltage generating circuit generates a leading phase control signal and a lagging phase control signal according to the output of the digital-to-analog conversion circuit. Each clock delay control branch has at least one stage of delay control circuitry, each stage of delay control circuitry comprising: the phase delay unit is connected with the second delay unit in series and then is connected with the phase lead unit and the first delay unit in parallel; the phase advancing unit receives one input clock signal in the multipath input clock signals and outputs a phase advancing clock signal to the connecting unit according to the advancing phase control signal and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connecting unit, and the connecting unit outputs the first delay clock signal to the second delay unit and the phase advancing unit and the first delay unit of a next-stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the lag phase unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
One clock delay control branch in this embodiment may include a multi-stage delay control circuit as shown in fig. 2, and several clock delay control branches share one bias voltage generating circuit 206 in fig. 2. It should be appreciated that several clock delay control branches may also employ separate bias voltage generation circuits. Fig. 6 shows a schematic diagram of mismatch (mismatch) and jitter (jitter) of several clock delay control branches in one embodiment. The jitter contribution and power consumption of the calibration circuit module are dynamically adjusted according to specific clock skew error magnitudes, and when there is a small mismatch, the proposed circuit has minimal jitter and minimal power.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2,2 times, 2, and 2 or more, 2 or more times, 2 or more.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims (9)

1. A phase interpolator based clock skew calibration circuit, comprising:
a bias voltage generation circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog conversion circuit;
at least one stage of delay control circuit, each stage of delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then is connected with the phase lead unit and the first delay unit in parallel; the phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connection unit, and the connection unit outputs to the second delay unit and the phase advancing unit and the first delay unit of a next stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the phase lag unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
2. The clock skew calibration circuit of claim 1, wherein the phase lead unit and the phase lag unit each comprise: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the grid electrode of the first PMOS transistor is connected to the advanced phase control signal, the source electrode of the first PMOS transistor is connected to the power supply end, and the drain electrode of the first PMOS transistor is connected to the source electrode of the second PMOS transistor; the grid electrode of the first NMOS transistor is connected to the hysteresis phase control signal, the source electrode of the first NMOS transistor is connected to the ground terminal, and the drain electrode of the first NMOS transistor is connected to the source electrode of the second NMOS transistor; the gates of the second PMOS transistor and the second NMOS transistor are connected as a clock signal input end, and the drains of the second PMOS transistor and the second NMOS transistor are connected as a clock signal output end.
3. The clock skew calibration circuit of claim 2, wherein parameters between the first PMOS transistor, first NMOS transistor, second PMOS transistor, and second NMOS transistor in each stage of the delay control circuit are different to obtain different phase-advanced or phase-retarded clock signals.
4. The clock skew calibration circuit of claim 3, wherein the parameters include a channel width and a length of the transistor.
5. The clock skew calibration circuit of claim 1, wherein the bias voltage generation circuit includes third to fifth PMOS transistors, third to fourth NMOS transistors, and first and second resistors, sources of the third to fifth PMOS transistors being connected to a power supply terminal, gates of the third and fourth PMOS transistors being connected to the digital-to-analog conversion circuit, drains of the fourth PMOS transistor outputting the retard phase control signal and being connected to one end of the first resistor, and gates of the third and fourth NMOS transistors, another end of the first resistor being connected to a drain of the third NMOS transistor, a drain of the fifth PMOS transistor being connected to one end of the second resistor, a gate of the fifth PMOS transistor being connected to another end of the second resistor and to a drain of the fourth NMOS transistor and outputting a lead phase control signal.
6. The clock skew calibration circuit of claim 1, wherein the first delay unit includes an inverter having an input connected to the input clock signal and an output connected to the connection unit.
7. The clock skew calibration circuit of claim 1, wherein the second delay unit includes an inverter having an input connected to the connection unit and an output connected to an input of the phase lag unit.
8. A phase interpolator based clock skew calibration circuit, comprising:
a bias voltage generation circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog conversion circuit;
a plurality of clock delay control branches, each clock delay control branch having at least one stage of delay control circuit, each stage of delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then is connected with the phase lead unit and the first delay unit in parallel; the phase advancing unit receives one input clock signal in the multipath input clock signals and outputs a phase advancing clock signal to the connecting unit according to the advancing phase control signal and the retarding phase control signal, the first delay unit receives the input clock signal and outputs a first delay clock signal to the connecting unit, and the connecting unit outputs the first delay clock signal to the second delay unit and the phase advancing unit and the first delay unit of a next-stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the phase lag unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
9. The clock skew calibration circuit of claim 8, wherein the clock skew calibration circuit comprises 12 clock delay control branches.
CN202211065860.4A 2022-08-31 2022-08-31 Clock skew calibration circuit based on phase interpolator Active CN115361017B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211065860.4A CN115361017B (en) 2022-08-31 2022-08-31 Clock skew calibration circuit based on phase interpolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211065860.4A CN115361017B (en) 2022-08-31 2022-08-31 Clock skew calibration circuit based on phase interpolator

Publications (2)

Publication Number Publication Date
CN115361017A CN115361017A (en) 2022-11-18
CN115361017B true CN115361017B (en) 2023-05-23

Family

ID=84004939

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211065860.4A Active CN115361017B (en) 2022-08-31 2022-08-31 Clock skew calibration circuit based on phase interpolator

Country Status (1)

Country Link
CN (1) CN115361017B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804919B1 (en) * 2019-09-24 2020-10-13 Microsoft Technology Licensing, Llc Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods
CN113890533A (en) * 2020-07-02 2022-01-04 三星电子株式会社 Delay circuit of delay locked loop circuit and delay locked loop circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US20080054957A1 (en) * 2004-05-26 2008-03-06 Noriaki Takeda Skew Correction Apparatus
CN103986461B (en) * 2014-05-30 2017-04-19 华为技术有限公司 Time digital conversion method and time digital converter
CN106849942B (en) * 2016-12-29 2020-10-16 北京时代民芯科技有限公司 Ultra-high-speed low-jitter multiphase clock circuit
US10218343B1 (en) * 2017-10-31 2019-02-26 Sandisk Technologies Llc Duty cycle correction scheme

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804919B1 (en) * 2019-09-24 2020-10-13 Microsoft Technology Licensing, Llc Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods
CN113890533A (en) * 2020-07-02 2022-01-04 三星电子株式会社 Delay circuit of delay locked loop circuit and delay locked loop circuit

Also Published As

Publication number Publication date
CN115361017A (en) 2022-11-18

Similar Documents

Publication Publication Date Title
US9013339B2 (en) Track and hold architecture with tunable bandwidth
US6542017B2 (en) Feed-forward approach for timing skew in interleaved and double-sampled circuits
Razavi Problem of timing mismatch in interleaved ADCs
US10742226B1 (en) Multi-channel high-precision ADC circuit with self-calibration of mismatch error
US9503115B1 (en) Circuit for and method of implementing a time-interleaved analog-to-digital converter
US7705649B1 (en) Duty cycle correction circuit with small duty error and wide frequency range
US7649957B2 (en) Non-overlapping multi-stage clock generator system
US10727852B2 (en) Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
WO2004034404A2 (en) Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined
US7821316B2 (en) Multiphase clock generator with enhanced phase control
US9041573B2 (en) Sampling device with buffer circuit for high-speed ADCs
US7548104B2 (en) Delay line with delay cells having improved gain and in built duty cycle control and method thereof
EP3216128B1 (en) Digital-to-phase converter
CN115425972B (en) Error calibration circuit of high-speed cascade analog-to-digital converter circuit
CN108768396B (en) Clock phase mismatch calibration circuit for multichannel ADC
Chung et al. A 38-mW 7-bit 5-GS/s time-interleaved SAR ADC with background skew calibration
CN108809306B (en) Multi-channel high-precision ADC circuit with mismatch error self-calibration function
CN115361017B (en) Clock skew calibration circuit based on phase interpolator
EP2323256B1 (en) Method and system for improving limiting amplifier phase noise for low slew-rate input signals
JP2010130293A (en) Duty correction circuit and duty correction method
US10211820B2 (en) Clock generator for multi-channel analog to digital converter
Duan et al. A 12.8 GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6 b ENOB
Wang et al. An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS
JP2004282360A (en) Phase control circuit
Zhang et al. A 10-GS/s Sample and Hold System for High-Speed Time-Interleaved ADC

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant