JP2004282360A - Phase control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase control circuit for generating a polyphase clock signal having less deviation in timing. <P>SOLUTION: The phase control circuit includes a phase interpolator circuit (30) for outputting a second clock signal having a phase relation corresponding to an input digital signal for a first clock signal, and a DLL circuit (35) for delaying the second clock signal on the basis of feedback control by a delay element sequence consisting of a plurality of delay elements. The phase control circuit outputs some of the second clock signal and the output signals of the respective delay elements as polyphase signals. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a phase control circuit that controls the phase of a clock signal, and more particularly, to a phase control circuit that controls the phase of a clock signal using a phase interpolation circuit.
[Prior art]
A phase interpolation circuit (Phase Interpolator circuit) generates a sine wave of a desired phase by weighting and superimposing a plurality of sine waves by a mixer circuit, and freely adjusts the phase of a clock signal based on the sine wave. It is.
[0002]
FIG. 1 is a diagram illustrating an example of a configuration of a mixer circuit 10 used in a phase interpolation circuit. The mixer circuit 10 of FIG. 1 generates a sine wave signal having a desired phase by weighting and superimposing two sine wave signals having phases different from each other by 90 °.
[0003]
The mixer circuit 10 of FIG. 1 includes NMOS transistors 11 to 14, current sources 15 and 16, and a resistor R.
[0004]
The sine wave signal Φ1 is supplied to the gate terminal of the NMOS transistor 11, and the sine wave signal Φ1x is supplied to the gate terminal of the NMOS transistor 12. The sine wave signal Φ2 is supplied to the gate terminal of the NMOS transistor 13, and the sine wave signal Φ2x is supplied to the gate terminal of the NMOS transistor 14. The signal Φ1 is a clock signal having a phase of 0 ° as a reference phase, and the signal Φ1x is a complementary signal of the signal Φ1 and has a phase of 180 °. The signal Φ2 is a clock signal having a phase of 90 °, and the signal Φ2x is a complementary signal of the signal Φ2 and has a phase of 270 °.
[0005]
The output signal OUT is generated by weighting and adding the 0 ° phase signal Φ1 and the 90 ° phase signal Φ2. In addition, an output signal OUTX which is a complementary signal of the output signal OUT is generated by weighting and adding the 0 ° phase signal Φ1x and the 90 ° phase signal Φ2x.
[0006]
The weight of the 0 ° phase signal φ1 is substantially proportional to the current value flowing through the current source (NMOS transistor) 15, and the weight of the 90 ° phase signal φ2 is substantially proportional to the current value flowing through the current source 16. Therefore, the output signal OUT is output as a sine wave having a phase corresponding to the ratio of these current values. Similarly, an output signal OUTX which is a complementary signal of the output signal OUT is output. Here, the current value I1 flowing to the current source 15 is controlled by the analog signal VB1, and the current value I2 flowing to the current source 16 is controlled by the analog signal VB2.
[0007]
FIG. 2 is a diagram showing an example of the configuration of the phase interpolation circuit 20 including the mixer circuit 10 of FIG.
[0008]
2 includes the mixer circuit 10, the amplitude adjusters 21 and 22, the amplifier 23, and the D / A conversion circuit 24 shown in FIG.
[0009]
The D / A conversion circuit 24 generates analog signals VB1 and VB2 shown in FIG. 1 and supplies the analog signals VB1 and VB2 to the mixer circuit 10 by DA-converting a digital code supplied from the outside into an analog signal. Thus, phase control can be performed with a resolution determined by the number of bits of the digital signal. The amplitude adjusters 21 and 22 attenuate the amplitudes of the input clock signals INCLK0, INCLK180, INCLK90, and INCLK270 in the form of a rectangular wave, and convert them into clock signals having a shape close to a sine wave. The converted sine wave clock signals are Φ1, Φ1x, Φ2, and Φ2x in FIG.
[0010]
The amplifier 23 amplifies and amplitude-saturates the output signals OUT and OUTX of the mixer circuit 10 to generate a rectangular-wave-shaped clock signal having a phase specified by the digital code.
[0011]
[Patent Document 1]
JP-A-11-261408
[Patent Document 2]
JP 2001-56723 A [Problems to be solved by the invention]
In the phase interpolation circuit 20 having the above configuration, only clock signals of 0 ° and 180 ° which are complementary to each other are generated. For example, when a clock signal having a phase relationship of 90 ° is required, another phase interpolation circuit similar to the phase interpolation circuit 20 is provided, and the digital code set in the phase interpolation circuit 20 is 90 °. A configuration such as setting the shifted digital code in the phase interpolation circuit is required. However, since the phase interpolation circuit has a relatively large circuit scale, it is easily affected by process variations and the like, and it is difficult to completely guarantee the timing of the clock signal in a configuration having two phase interpolation circuits.
[0013]
Furthermore, if a clock signal having a multiple of 45 ° is required separately, it is necessary to provide a phase interpolation circuit as many as the number of clock signals, thereby increasing the factor of jitter generation. When such jitter occurs, there is a problem that the phase of the output clock is distorted. If the operating frequency can be reduced, a multi-phase clock signal can be generated by providing the required number of frequency dividers, but these frequency dividers become digital noise sources and cause malfunction. May cause.
[0014]
In view of the above, an object of the present invention is to provide a phase control circuit that generates a multi-phase clock signal with a small timing shift.
[Means for Solving the Problems]
A phase control circuit according to the present invention includes a phase interpolation circuit that outputs a second clock signal having a phase relationship with a first clock signal according to an input digital signal, and a delay element array including a plurality of delay elements. A DLL circuit for delaying the second clock signal based on the feedback control, and outputting some of the second clock signal and output signals of the plurality of delay elements as a multi-phase clock signal. Features.
[0015]
In the above-mentioned phase control circuit, by connecting a DLL circuit to the output of the phase interpolation circuit, the phase control circuit has an equidistant phase corresponding to the resolution of the DLL circuit based on a signal whose phase is adjusted with the resolution of the phase interpolation circuit. A plurality of multi-phase clock signals can be generated. Since the DLL is used, it is easier to secure the timing than a configuration in which a plurality of phase interpolation circuits and a plurality of frequency dividers are prepared, and it is possible to generate a multi-phase clock signal with less timing deviation. Further, since a flip-flop is not required as a circuit element, digital switching noise can be reduced.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0016]
FIG. 3 is a diagram showing the configuration of the first embodiment of the phase control circuit according to the present invention.
[0017]
The phase control circuit of FIG. 3 includes phase interpolation circuits (P / I) 30 and 31, a phase comparator 32, a charge pump 33, and a plurality of delay elements 34-1 to 34-n forming a delay element array. . The phase interpolation circuits 30 and 31 receive reference clock signals REFCLK and REFCLK90 having phases different from each other by 90 °, and generate clock signals PICLK1 and PICLK2 having phases corresponding to the digital codes input thereto. The phase interpolation circuits 30 and 31 may have the same configuration as that of the phase interpolation circuit 20 shown in FIG. 2, and each clock signal may actually be composed of complementary signals having a 180 ° phase difference from each other. If a complementary signal is not required, each clock signal may be a single-phase signal.
[0018]
The signal output from the phase interpolation circuit 30 is supplied to one input of the phase comparator 32 via the delay elements 34-1 to 34-n. The signal output from the other phase interpolation circuit 31 is supplied to the other input of the phase comparator 32 as it is. The phase comparator 32 compares the phases of these two input signals, and supplies the signal UP or the signal DN to the charge pump 33 according to the comparison result. In response to the signal UP or the signal DN, the charge pump 33 changes the potential of the output signal. The signal delay time of each of the delay elements 34-1 to 34-n is adjusted according to this potential change. The signal delay time of each of the delay elements 34-1 to 34-n is the same.
[0019]
By the above operation, the phase of the signal supplied from the delay elements 34-1 to 34-n to the phase comparator 32 is adjusted, and the two inputs of the phase comparator 32 are locked to be in the same phase by feedback control. You. In this state, the output signal PICLK1 of the phase interpolation circuit 30 has a phase corresponding to the digital code input to the phase interpolation circuit 30, and the signal output from each of the delay elements 34-1 to 34-n. DCLK1 to DCLKn are signals having phases obtained by dividing n between PICLK1 and PICLK2.
[0020]
FIG. 4 is a timing chart showing the output signal PICLK1 of the phase interpolation circuit 30 and the output signals DCLK1 to DCLKn of the delay elements 34-1 to 34-n.
[0021]
As shown in FIG. 4, the output signal PICLK1 of the phase interpolation circuit 30 is a signal delayed from the reference clock signal REFCLK by the phase ly / m. Here, y is a range in which the phase interpolation circuit 30 can adjust the phase, m is the phase adjustment resolution of the phase interpolation circuit 30, and l is a value corresponding to the input digital code. The output signals DCLK1 to DCLKn of the delay elements 34-1 to 34-n are signals delayed from the signal PICLK1 by z / n to nz / n, respectively. Here, z is the amount of phase delay of the entire delay element array, and n is the total number of delay elements.
[0022]
For example, the output signal DCLKs from the s-th delay element 34-s is a signal having a phase delay of ly / m + sz / n with respect to the reference clock signal REFCLK. Therefore, n polyphase signals can be generated by phase adjustment according to the resolution of the phase interpolation circuit 30 and the resolution of the delay elements 34-1 to 34-n.
[0023]
Here, the phase comparator 32, the charge pump 33, and the delay elements 34-1 to 34-n constitute a DLL (Delay Locked Loop) circuit 35. Each delay element of the DLL circuit has variations, and each delay element output includes a skew error. However, when comparing the phase interpolation circuit and the delay element, the delay element can be configured to have a smaller size and smaller variation.
[0024]
As described above, in the present invention, by connecting the DLL circuit to the output of the phase interpolation circuit, based on the signal whose phase has been adjusted with the resolution of the phase interpolation circuit, the phase at equal intervals corresponding to the resolution of the DLL circuit can be obtained. A plurality of multi-phase clock signals can be generated. Since the DLL is used, it is easier to secure the timing than a configuration in which a plurality of phase interpolation circuits and a plurality of frequency dividers are prepared, and it is possible to generate a multi-phase clock signal with less timing deviation. Further, since a flip-flop is not required as a circuit element, digital switching noise can be reduced.
[0025]
FIG. 5 is a diagram showing a configuration of a second embodiment of the phase control circuit according to the present invention. 5, the same components as those of the phase control circuit of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.
[0026]
The phase control circuit of FIG. 5 is configured such that the phase interpolation circuit 31 is deleted from the phase control circuit of FIG. 3, and instead the output of the phase interpolation circuit 30 is supplied to the phase comparator 32 as it is. In the configuration of FIG. 3, if the same digital code is input to the phase interpolation circuits 30 and 31, it is logically the same as the configuration of FIG. When designing a circuit suitable for high-speed operation, it is difficult to secure a band in the phase interpolation circuit. Therefore, in order to reduce the load, two phase interpolation circuits (30 and 30) as shown in FIG. 31) It is desirable to provide.
[0027]
On the other hand, in the case of a circuit whose operation speed is relatively slow, a configuration using a single phase interpolation circuit 30 as shown in FIG. 5 may be used. In this case, since an error due to a variation in a plurality of phase interpolation circuits is suppressed, there is an advantage that the timing is easily guaranteed as compared with the configuration of FIG.
[0028]
FIG. 6 is a timing chart for explaining the operation of the phase control circuit of FIG.
[0029]
The output PICLK of the phase interpolation circuit 30 is a signal whose phase is delayed by T1 with respect to the reference clock signal REFCLK. The phase delay T1 has an amount corresponding to the digital code input l to the phase interpolation circuit 30. The phase comparator 32 compares the signal PICLK with the signal obtained by delaying the signal PICLK by the delay elements 34-1 to 34-n, and adjusts the delay amount of the delay element so that both signals have the same phase.
[0030]
FIG. 6 shows an example in which the number n of the delay elements 34-1 to 34-n is four. In this case, one cycle of the signal PICLK (the same as one cycle of the reference clock REFCLK) is divided into four to obtain the output DCLK1 to DCLK4 of each delay element as a multiphase clock signal.
[0031]
In this way, in the phase control circuit according to the second embodiment of FIG. 5, the DLL circuit is connected to the output of the phase interpolation circuit, and the output of the phase interpolation circuit and the signal delayed by the delay element array The delay of the delay element array is controlled so that the phases match. This makes it possible to generate a plurality of multi-phase clock signals having phases at equal intervals corresponding to the resolution of the DLL circuit, based on the signal whose phase has been adjusted with the resolution of the phase interpolation circuit.
[0032]
FIG. 7 is a diagram showing the configuration of a third embodiment of the phase control circuit according to the present invention. 7, the same components as those of the phase control circuit of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.
[0033]
The phase control circuit of FIG. 7 is configured so that the input of the phase comparator 32, which has directly received the output of the phase interpolation circuit 30 in the phase control circuit of FIG. 5, is used as the reference clock signal REFCLK. In this configuration, the phase comparator 32 controls the delay element 34-1 so that the phase of the signal obtained by delaying the output PICK of the phase interpolation circuit 30 by the delay elements 34-1 to 34-n and the reference clock signal REFCLK match. The delay amounts of 1 to 34-n are controlled.
[0034]
FIG. 8 is a timing chart for explaining the operation of the phase control circuit of FIG.
[0035]
The output PICLK of the phase interpolation circuit 30 is a signal whose phase is delayed by T1 with respect to the reference clock signal REFCLK. The phase delay T1 has an amount corresponding to the digital code input l to the phase interpolation circuit 30. The phase comparator 32 compares the signal obtained by delaying the signal PICLK by the delay elements 34-1 to 34-n with the reference clock signal REFCLK, and adjusts the delay amount of the delay element so that both signals have the same phase. I do.
[0036]
FIG. 8 shows an example in which the number n of the delay elements 34-1 to 34-n is four. In this case, the outputs DCLK1 to DCLK4 of the respective delay elements are obtained as a multiphase clock signal obtained by dividing a period obtained by subtracting T1 from one cycle of the reference clock REFCLK into four.
[0037]
Thus, in the phase control circuit according to the third embodiment of FIG. 7, the DLL circuit is connected to the output of the phase interpolation circuit, and the signal obtained by delaying the output of the phase interpolation circuit by the delay element array and the reference clock signal The delay of the delay element array is controlled so that the phases of the delay element rows coincide with each other. In other words, a phase interpolation circuit is inserted as one of the delay elements of the DLL circuit. This makes it possible to generate a plurality of multi-phase clock signals having phases at equal intervals corresponding to the resolution of the DLL circuit, based on the signal whose phase has been adjusted with the resolution of the phase interpolation circuit.
[0038]
In the third embodiment shown in FIG. 7, the total delay amount of the delay element array dynamically changes in accordance with the change in the phase of the phase interpolation circuit 30. Unlike the configuration of the second embodiment shown in FIG. 5, a multi-phase clock having a phase shifted by a predetermined phase amount (for example, 90 degrees) corresponding to the number n of delay elements with respect to the clock signal PICLK is generated. Instead, it is possible to generate a multi-phase clock signal having an adjustable phase interval regardless of the number n of delay elements.
[0039]
FIG. 9 is a circuit diagram showing an example of a circuit configuration of the phase comparator 32.
[0040]
The phase comparator 32 in FIG. 9 includes NAND circuits 41 to 49, a NOR circuit 50, inverters 51 to 54, and buffers 55 and 56. The phase comparator 32 changes the state of the corresponding internal flip-flop in response to the edge that has arrived earlier between the signal ref_ck and the signal fb_ck, thereby determining the context of the edge timing. As a result, the output signals UP and DN are appropriately output according to the order of the edge timing between the signal ref_ck and the signal fb_ck. For example, the output signal UP is output when the signal fb_ck is behind the signal ref_ck, and the output signal DN is output when the signal fb_ck is ahead of the signal ref_ck.
[0041]
For example, when corresponding to the configuration of FIG. 7, the signal ref_ck corresponds to the reference clock signal REFCLK, and the signal fb_ck corresponds to the final output signals DCLKn of the delay elements 34-1 to 34-n. The phase detection signal pd is a signal for controlling ON / OFF of the phase comparison operation of the phase comparator 32. The phase detection signal pd causes the phase comparison operation to be executed when the signal is LOW and stops the phase comparison operation when the signal is HIGH.
[0042]
FIG. 10 is a circuit diagram showing an example of a circuit configuration of the charge pump 33.
[0043]
The charge pump 33 in FIG. 10 includes current limits 61 and 62, a PMOS transistor 63, and an NMOS transistor 64. The PMOS transistor 63 and the NMOS transistor 64 are enhancement-type field-effect transistors. When the potential difference between the gate and the source is zero, the source-drain is completely cut off and no current flows.
[0044]
When the signal UP or the signal DN is supplied from the phase comparator 32, the PMOS transistor 63 or the NMOS transistor 64 is turned on. The voltage of the control signal CNTL rises or falls according to the time and the number of times the signal UP or the signal DN is supplied. This control signal CNTL is supplied to each of the delay elements 34-1 to 34-n, and controls each delay time.
[0045]
FIG. 11 is a circuit diagram showing an example of a circuit configuration of the delay element controlled by the control signal CNTL. This delay element corresponds to each of the delay elements 34-1 to 34-n of the phase control circuit.
[0046]
The delay element in FIG. 11 includes PMOS transistors 61 to 63 and NMOS transistors 64 to 66. The signal IN is a signal input to a delay element, and the signal input is delayed to output a signal OUT. This delay time is controlled by the voltage of the control signal CNTL. When the voltage of the control signal CNTL increases, the amount of current supplied to the inverter including the PMOS transistor 63 and the NMOS transistor 65 increases, and the rise time and the fall time of the signal OUT decrease. That is, the delay time by the delay element is shortened. Conversely, when the voltage of the control signal CNTL decreases, the amount of current supplied to the inverter including the PMOS transistor 63 and the NMOS transistor 65 decreases, and the rise time and the fall time of the signal OUT increase. That is, the delay time of the delay element becomes longer.
[0047]
Thus, the delay time of the delay element can be controlled by the control signal CNTL.
[0048]
FIG. 12 is a circuit diagram showing another example of the circuit configuration of the delay element controlled by the control signal CNTL.
[0049]
12 includes a PMOS transistor 71, an NMOS transistor 72, a variable resistor 73, and a capacitor 74. The signal IN is a signal input to a delay element, and the signal input is delayed to output a signal OUT. This delay time is controlled by the voltage of the control signal CNTL. When the voltage of the control signal CNTL increases, the resistance value of the variable resistor 73 decreases, the time constant decreases, and the rise time and the fall time of the signal OUT decrease. That is, the delay time by the delay element is shortened. Conversely, when the voltage of the control signal CNTL decreases, the resistance value of the variable resistor 73 increases, the time constant increases, and the rise time and fall time of the signal OUT increase. That is, the delay time of the delay element becomes longer.
[0050]
Thus, the delay time of the delay element can be controlled by the control signal CNTL.
[0051]
FIG. 13 is a circuit diagram showing still another example of the circuit configuration of the delay element controlled by the control signal CNTL. Although the input / output signals are single-phase in the configurations of FIGS. 11 and 12, the configuration of FIG. 13 corresponds to the case where the input / output signals are differential signals.
[0052]
13 includes NMOS transistors 81 and 82, variable resistors 83 and 84, and a constant current source 85. The signals IN and INX are differential signal inputs to the delay element, and the differential signal inputs are delayed to output differential signal outputs OUT and OUTX. This delay time is controlled by the voltage of the control signal CNTL.
[0053]
When the voltage of the control signal CNTL increases, the resistance values of the variable resistors 83 and 84 decrease, the source-drain voltages of the NMOS transistors 81 and 82 increase, and the switching speed of the NMOS transistors increases. That is, the delay time by the delay element is shortened. Conversely, when the voltage of the control signal CNTL decreases, the resistance values of the variable resistors 83 and 84 increase, the source-drain voltages of the NMOS transistors 81 and 82 decrease, and the switching speed of the NMOS transistors decreases. That is, the delay time of the delay element becomes longer.
[0054]
Thus, the delay time of the delay element can be controlled by the control signal CNTL.
[0055]
As described above, the phases are compared by the phase comparator as shown in FIG. 9, and based on the result of the phase comparison, the voltage of the control signal is controlled by using the charge pump as shown in FIG. The delay amount of the delay element as shown in any of FIGS. 11 to 13 is adjusted by the signal. In this way, the feedback control is performed, and it is possible to lock the signals to be compared by the phase comparator so that the phases match.
[0056]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the above-described phase control circuit, by connecting a DLL circuit to the output of the phase interpolation circuit, the phase of the phase adjusted at the resolution of the phase interpolation circuit is basically used, and the equally-spaced phase corresponding to the resolution of the DLL circuit is obtained. Can be generated. Since the DLL is used, it is easier to secure the timing than a configuration in which a plurality of phase interpolation circuits and a plurality of frequency dividers are prepared, and it is possible to generate a multi-phase clock signal with less timing deviation.
[0057]
Further, since a flip-flop is not required as a circuit element, digital switching noise can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a configuration of a mixer circuit used in a phase interpolation circuit.
FIG. 2 is a diagram illustrating an example of a configuration of a phase interpolation circuit including the mixer circuit of FIG. 1;
FIG. 3 is a diagram showing a configuration of a first embodiment of a phase control circuit according to the present invention.
FIG. 4 is a timing chart showing an output signal of a phase interpolation circuit and output signals of a plurality of delay elements.
FIG. 5 is a diagram showing a configuration of a second embodiment of the phase control circuit according to the present invention.
FIG. 6 is a timing chart for explaining the operation of the phase control circuit of FIG. 5;
FIG. 7 is a diagram showing a configuration of a third embodiment of the phase control circuit according to the present invention.
FIG. 8 is a timing chart for explaining the operation of the phase control circuit of FIG. 7;
FIG. 9 is a circuit diagram showing an example of a circuit configuration of the phase comparator 32.
FIG. 10 is a circuit diagram illustrating an example of a circuit configuration of a charge pump.
FIG. 11 is a circuit diagram showing an example of a circuit configuration of a delay element controlled by a control signal.
FIG. 12 is a circuit diagram showing another example of a circuit configuration of a delay element controlled by a control signal.
FIG. 13 is a circuit diagram showing still another example of the circuit configuration of the delay element controlled by the control signal.
[Explanation of symbols]
30, 31 Phase interpolation circuit 32 Phase comparator 33 Charge pumps 34-1 to 34-n Delay element 35 DLL circuit

Claims (10)

A phase interpolation circuit for outputting a second clock signal having a phase relationship according to the input digital signal with respect to the first clock signal;
A DLL circuit for delaying the second clock signal based on a feedback control by a delay element array including a plurality of delay elements, wherein the second clock signal and some of the output signals of the plurality of delay elements are included; As a multi-phase clock signal. A second phase interpolation circuit that outputs a third clock signal having a phase relationship corresponding to the input digital signal with respect to the first clock signal, wherein the DLL circuit converts the second clock signal into the second clock signal; 2. The phase control circuit according to claim 1, wherein the delay amounts of the plurality of delay elements are feedback-controlled so that the phase of the signal delayed by the delay element row and the phase of the third clock signal match. The DLL circuit feedback-controls delay amounts of the plurality of delay elements so that a signal obtained by delaying the second clock signal by the delay element row and a phase of the second clock signal match. The phase control circuit according to claim 1, wherein The DLL circuit feedback-controls the delay amounts of the plurality of delay elements so that the phase of the signal obtained by delaying the second clock signal by the delay element row and the phase of the first clock signal match. The phase control circuit according to claim 1, wherein The phase interpolation circuit includes a mixer circuit that changes a current amount of a plurality of clock signals having different phases according to the input digital signal and generates a clock signal of a desired phase by superimposing the plurality of clock signals. The phase control circuit according to claim 1, wherein: 2. The phase control circuit according to claim 1, wherein each of the plurality of delay element arrays has the same delay amount. The DLL circuit is
The plurality of delay elements constituting the delay element row;
A phase comparator for comparing the phase of the signal obtained by delaying the second clock signal with the delay element row with another clock signal;
2. The phase control circuit according to claim 1, further comprising a circuit that generates a control signal based on a phase comparison result of the phase comparator, and controls a delay of each of the plurality of delay elements by the control signal. 8. The phase control circuit according to claim 7, wherein each of the plurality of delay elements controls a delay by changing a current amount for driving an output according to a change in the potential of the control signal. 8. The phase control circuit according to claim 7, wherein each of the plurality of delay elements controls a delay by changing a time constant of charging and discharging of the capacitor according to a change in the potential of the control signal. 8. The phase control circuit according to claim 7, wherein each of the plurality of delay elements controls a delay by changing a voltage between a source and a drain of the MOS transistor according to a change in the potential of the control signal.

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