CN115118283A

CN115118283A - Current source drive circuit, analog-to-digital converter and receiver

Info

Publication number: CN115118283A
Application number: CN202110296515.0A
Authority: CN
Inventors: 杨晓雷; 李林洋; 朱昊
Original assignee: Amlogic Shanghai Co Ltd
Current assignee: Amlogic Shanghai Co Ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2022-09-27

Abstract

Current source drive circuit, adc and receiver, wherein, current source drive circuit includes: the latch circuit module is suitable for outputting a first latch signal and a first latch inverted signal based on a first path of input signals and outputting a second latch signal and a second latch inverted signal based on a second path of input signals; the differential complementary circuit module comprises two complementary switch group submodules, and any switch group submodule is respectively coupled with one current source branch circuit of the first current source branch circuit and the second current source branch circuit; and the driving circuit module is suitable for outputting multi-path switch control signals to the switch group sub-modules of the differential complementary circuit module based on the first latching signal, the first latching inverted signal, the second latching signal and the second latching inverted signal, so that a switch in the switch group sub-module corresponding to any current source branch is in a conducting state at any moment to drive the current source in the corresponding current source branch. The scheme can avoid current source reconstruction.

Description

Current source drive circuit, analog-to-digital converter and receiver

Technical Field

The embodiment of the specification relates to the technical field of electronic circuits, in particular to a current source driving circuit, an analog-to-digital converter and a receiver.

Background

The receiver can be classified into a super-heterodyne structure, a zero intermediate frequency structure, and a low intermediate frequency structure based on differences in structures. At present, a zero intermediate frequency receiver and a low intermediate frequency receiver are commonly used, and the zero intermediate frequency receiver and the low intermediate frequency receiver respectively have advantages and disadvantages. Where WIFI communication typically uses a zero intermediate frequency receiver, Bluetooth (Bluetooth) or some narrowband communication typically uses a low intermediate frequency receiver.

Referring to fig. 1, a schematic structural diagram of a Low-intermediate frequency receiver may be applied to a bluetooth/Low energy bluetooth (BT/BLE) module, where the Low-intermediate frequency receiver 10 may be composed of a Low-Noise Amplifier (LNA), a transconductance (gm), a mixer (mixer), a transimpedance Amplifier (TIA), a Complex Filter (Complex Filter)1A, and an Analog-to-Digital Converter (ADC), the Low-intermediate frequency receiver 10 may be coupled to a physical layer (PHY), a radio frequency signal is received by an antenna, amplified by the LNA, and demodulated to obtain two orthogonal signals: an In-phase (I) input signal and a Quadrature (Quadrature) input signal. For I path and Q path input signals, voltage input signals are converted into current output signals through gm respectively, radio frequency signals in a current form are down-converted to low intermediate frequency through a mixer, the current signals after down-conversion are converted into voltage output signals through TIA, out-of-band noise signals and interference are filtered out through a complex filter 1A, then received analog signals are converted into digital signals through ADC, and the digital signals are output to PHY for modulation and demodulation and other processing of the signals. The ADC generally has two implementation modes, one is a Successive Approximation Analog-to-Digital Converter (SAR ADC), and the other is a Sigma-Delta (SD) modulation ADC, which considers power consumption and complexity comprehensively and is often selected as the SAR ADC.

With the rise Of applications such as Internet Of Things (IOT), True Wireless Stereo (TWS), and the like, higher requirements are put on the power consumption Of BT/BLT products. In order to reduce power consumption, the low if receiver of the structure shown in fig. 1 is often modified. Another structure diagram of the low-if receiver shown in fig. 2 is different from fig. 1 in that the complex filter 1A and the SAR ADC in fig. 1 can be implemented by a complex continuous-time sdadc (complex CT sdadc)2A, which can save the complex filter 1A.

Although the system power consumption can be reduced by using the complex continuous time SDADC, mismatch of In-phase Quadrature (IQ) is a serious problem, and the mismatch generates a mirror image signal corresponding to the signal at a negative frequency, thereby reducing the system demodulation performance. Among all mismatches in the IQ two-path, the mismatch influence of the Analog-to-Digital Converter (DAC) for feedback is the largest.

In order to solve the mismatch problem of the IQ two paths, the circuit can be further optimally designed, wherein a common method for eliminating the mismatch of the IQ two paths of feedback DACs is to exchange DAC current sources of the IQ two paths according to a certain rule.

The multi-bit feedback DAC is very commonly used in the design of the low-power SD ADC, and the mismatch of the multi-bit DAC itself is also a serious problem, which causes the performance of the modulator to be seriously degraded. Therefore, for the DAC of the I path or the Q path, the DAC unit needs to be randomly selected according to a certain requirement, so that the mismatch is dispersed into noise, and then the noise is shaped and pushed to a high frequency, thereby achieving the effect of improving the performance of the regulator. Therefore, in addition to the need for switching between the IQ two-way DACs, switching between the I and Q DAC cells is also required. Current steering DACs are one of the common DAC implementations.

However, one problem with the above implementation is that it is difficult to ensure that the switches connected to each current source are not closed at the same time at any input, thus potentially resulting in the current sources needing to be re-established, which in turn results in a degradation of the performance of the complex continuous-time SDADC.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a current source driving circuit, an analog-to-digital converter, and a receiver, which can achieve that a current source does not need to be re-established under any circumstances, improve stability of the current source driving circuit, and further improve performance of the analog-to-digital converter and the receiver using the current source driving circuit.

First, an embodiment of the present specification provides a current source driving circuit, which is adapted to drive a current source, and includes:

the latch circuit module is suitable for outputting a first latch signal and a first latch inverted signal based on a first path of input signals and outputting a second latch signal and a second latch inverted signal based on a second path of input signals;

a differential complementary circuit module comprising: two complementary switch bank sub-modules, wherein: any switch set submodule is respectively coupled with one current source branch of the first current source branch and the second current source branch, and the switch set submodule comprises a plurality of coupled switches;

and the driving circuit module is respectively coupled with the latch circuit module and the differential complementary circuit module, and is suitable for outputting a multi-path switch control signal to the switch group submodule of the differential complementary circuit module based on the first latch signal, the first latch inverted signal, the second latch signal and the second latch inverted signal, so that a switch in the switch group submodule corresponding to any current source branch is in a conducting state at any moment to drive the current source in the corresponding current source branch.

Embodiments of the present specification further provide an analog-to-digital converter, including: a first input path, a second input path, and a feedback path, wherein:

the first input path is suitable for obtaining a first path output signal based on a first input signal and a first feedback signal output by the feedback path;

the second input path is suitable for obtaining a second output signal based on a second input signal and a second feedback signal output by the feedback path;

the feedback path, coupled to the first input path and the second input path, respectively, includes:

a first current source branch;

a second current source branch;

in the current source driving circuit according to any embodiment of the present disclosure, a first input terminal of the current source driving circuit is coupled to an output terminal of the first input path, and a first output signal output by the first input path is used as a first input signal of a feedback path; a second input end of the second feedback path is coupled with an output end of the second input path, a second output signal output by the second input path is used as a second input signal of the feedback path, and the first feedback path digital-to-analog converter and the first current source branch are conducted and the second feedback path digital-to-analog converter and the second current source branch are conducted based on the first input signal and the second input signal;

and the feedback path digital-to-analog conversion device is suitable for outputting the first feedback signal to the first input path and outputting the second feedback signal to the second input path based on the switching control of the current source driving circuit.

Embodiments of the present specification further provide a receiver, including:

the demodulation device is suitable for demodulating a radio frequency input signal to obtain a first input signal and a second input signal which are in-phase and orthogonal;

the analog-to-digital converter according to any embodiment of this specification is adapted to perform analog-to-digital conversion on the first input signal and the second input signal to obtain a first channel output signal and a second channel output signal.

By adopting the current source driving circuit provided by the embodiment of the present specification, the current source driving circuit includes a latch circuit module, a driving circuit module and a differential complementary circuit module, wherein the differential complementary circuit module includes two complementary switch group sub-modules, any one of the switch group sub-modules is respectively coupled to one of the first current source branch and the second current source branch, the switch group sub-module includes a plurality of switches coupled to each other, the latch circuit module outputs a first latch signal and a first latch inverted signal based on a first path of input signal, and outputs a second latch signal and a second latch inverted signal based on a second path of input signal, and the driving circuit module outputs a plurality of switch signals to the switch group sub-module of the differential complementary circuit module based on the first latch signal, the first latch inverted signal, the second latch signal and the second latch inverted signal, in other words, all switches connected with the current sources are not closed at the same time, so that the current sources do not need to be reestablished under any condition, and the performances of the analog-to-digital converter and the receiver applying the current source can be improved.

Further, the driving circuit module includes a logic control submodule and two non-overlapping clock submodules coupled to the logic control submodule respectively and having the same structure, wherein the logic control submodule performs a predetermined logic operation based on the first latch signal and the second latch signal to output a first control signal and a second control signal, and the two non-overlapping clock submodules output multi-way switch control signals to corresponding switch group submodules based on the input first latch signal, the input first latch inverted signal, the input first control signal and the input second control signal, respectively, so that the two non-overlapping clock submodules can have switches in a conducting state at any time by controlling the operation logic of the logic control submodule, and thus a current source in the first current source branch and the second current source branch can always be in a conducting state In the current source driving circuit analog-to-digital converter in the embodiment of the present specification, since the current sources in the first current source branch and the second current source branch are always in a conducting state, when the mismatch of the analog-to-digital converter is eliminated by exchanging the first current source and the second current source in the feedback path of the analog-to-digital converter, the current source reconstruction may be avoided, and thus, the performance of the analog-to-digital converter and the performance of the receiver using the analog-to-digital converter may be improved.

Further, since each current source branch comprises a first current source and a second current source which are coupled between the power supply and the ground and have opposite current directions, each current source branch comprises two output ends with opposite current directions, and the switch set submodule comprises a control switch coupled between the first current source and the second current source on the corresponding current source branch, bidirectional switching of the current directions can be realized for any current source branch at any time.

Further, the logic control submodule includes an exclusive or gate unit, a first delay unit and a second delay unit, which are coupled in sequence, wherein a first input terminal of the exclusive or gate unit is adapted to input the first latch signal, a second input terminal of the exclusive or gate unit is adapted to input the second latch signal, output terminals of the exclusive or gate unit are coupled to an input terminal of the first delay unit and a first input terminal of the second delay unit, respectively, an output terminal of the first delay unit is adapted to output the first control signal, an output terminal of the second delay unit is adapted to output the second control signal, and a delay duration of the second delay unit is shorter than a delay duration of the first delay unit, since the first control signal and the second control signal have a delay duration of the second delay unit, the two non-overlapping clock submodules are controlled by the first control signal and the second control signal, the switch in the switch group submodule of the corresponding current source branch can be in a conducting state at any time, and the current source coupled with the switch is conducted.

Furthermore, the non-overlapping clock sub-modules include two non-overlapping clock units with the same structure and coupled with each other, wherein any one of the non-overlapping clock units includes a third delay unit, a second nand gate unit, a first nor gate unit and a fourth not gate, on one hand, the output signals of the first control signal and the third delay unit are input into the second nand gate unit, and the output end of the second nand gate unit outputs a corresponding switch control signal to control the on-off of a control switch of a current source branch coupled with the second nand gate unit; on the other hand, the second control signal and the output signal of the third delay unit are input to the first nor gate unit, the first nor gate unit is coupled to the fourth not gate, and the fourth not gate outputs a switch control signal to the control switch coupled thereto to control on/off of the control switch of the current source branch coupled thereto, so that at any time, switches coupled to the non-overlapping clock submodules in the first current source branch and the second current source branch are in a conducting state to conduct corresponding current sources, thereby avoiding current source reconstruction occurring in the exchange process of the first input signal and the second input signal of the analog-to-digital converter.

Further, when the first current source branch and the second current source branch respectively include a first current source and a second current source in opposite flow directions, and the current source branches respectively include two output terminals in opposite current flow directions, the non-overlapping clock unit further includes a fifth not gate and a sixth not gate, where the fifth not gate is coupled to the output terminal of the second nand gate, and the sixth not gate is coupled to the output terminal of the fourth not gate, and the non-overlapping clock unit respectively outputs a control signal to the control switch coupled between the current source and the current source branch output terminal of the corresponding current source branch, so as to control the on/off and flow directions of the current sources in the corresponding current source branches, so that in the process of exchanging the first input signal and the second input signal of the analog-to-digital converter, both the first current source branch and the second current source branch have current sources in a conducting state, current source reconstruction can thus be avoided.

Further, the third delay unit includes an and gate, a fourth delay unit, and a seventh not gate that are coupled in sequence, where an output of the seventh not gate is used as the first output of the first delay unit, and an output of the fourth delay unit is used as the output of the third delay unit, so that timings of switch control signals output by the second nand gate unit and the fourth not gate in the non-overlapping clock unit are more synchronous, and at least one switch in a switch group submodule coupled to one current source at any time is in a conducting state.

Further, by setting the delay time of the first delay unit to be longer than the delay time of the fourth delay unit, and adjusting the delay times of the first delay unit and the fourth delay unit according to practical application, different conduction overlapping times can be obtained.

Furthermore, the relative duration of the time delay in the driving circuit only depends on the number of logic gates, so that the driving circuit is not easily influenced by voltage, temperature and process angle and has better robustness.

Further, through a delay calibration module respectively coupled to the first delay unit and the fourth delay unit, the delay duration of the fourth delay unit is initially set to be a fixed value, and the delay adjustment step size of the first delay unit is 1/2 of the total adjustment step size ^N And inputting a preset test clock signal into the delay calibration module, so that the first delay unit performs cumulative counting, and when the output of the delay calibration module meets a preset condition, the time duration corresponding to the first delay unit is taken as the delay time duration of the first delay unit in the current source driving circuit, so that the absolute value of the difference between the delay time durations of the first delay unit and the fourth delay unit can be minimized, and the time delay of the whole current source driving circuit can be reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings needed to be used in the embodiments of the present specification or in the description of the prior art will be briefly described below, it is obvious that the drawings described below are only some embodiments of the present specification, and it is also possible for a person skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic diagram of a low intermediate frequency receiver;

fig. 2 shows a schematic diagram of another low intermediate frequency receiver;

FIG. 3 shows a schematic diagram of a complex continuous-time SDADC architecture;

fig. 4 is a schematic diagram illustrating a current source driving circuit in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a latch circuit module according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a connection relationship between modules of a current source driving circuit in an embodiment of the present specification;

FIG. 7 is a schematic diagram of a differential complementary circuit module in an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram illustrating a driving circuit module in an embodiment of the present disclosure;

9A-9D are waveform diagrams illustrating the input signal switching process and the switch control signals of the corresponding switch block sub-modules in the embodiments of the present description;

fig. 10 is a schematic structural diagram illustrating a delay calibration module in an embodiment of the present disclosure;

fig. 11 is a flowchart illustrating an automatic calibration process corresponding to the delay calibration module shown in fig. 10 in an embodiment of the present disclosure;

fig. 12 is a schematic diagram illustrating an analog-to-digital converter according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram showing a structure of another analog-to-digital converter in an embodiment of the present description;

fig. 14 shows a schematic structural diagram of a receiver in an embodiment of the present specification.

Detailed Description

As described in the background, the problem of mismatch of IQ two paths of the complex continuous-time SDADC is a serious problem, and the mismatch may generate an image signal corresponding to the signal at a negative frequency, thereby degrading the demodulation performance of the system. Of all mismatches in the IQ-two path, the influence of the mismatch of the DAC used for feedback is the largest.

Fig. 3 shows a schematic structure of a complex continuous-time SDADC, wherein the SDADC 30 includes an in-phase signal input path 31, a quadrature signal input path 32, and a feedback path 33, wherein:

the in-phase signal input path 31 is adapted to obtain a first output signal outI based on a first input signal inI and a first feedback signal I output by the feedback path;

the quadrature signal input path 32 is adapted to obtain a second output signal outQ based on a second input signal inQ and a second feedback signal Q output by the feedback path;

more specifically, the in-phase input path 31 and the quadrature signal input path 32 each comprise an adder, a filter and a quantizer, wherein:

in the in-phase signal input path 31, the first input signal inI and the first feedback signal I fed back by the feedback path are accumulated by an adder, and are filtered by a filter in a loop together with other modules to eliminate quantization noise; the quantizer quantizes the continuous signal output by the filter into a discrete signal to complete the basic function of analog-to-digital conversion.

The feedback path 33, coupled to the in-phase signal input path 31 and the quadrature signal input path 32 respectively, includes a Data Weighted Averaging (DWA) module, a driving circuit, and a feedback digital-to-analog conversion apparatus DACI + DACQ shared by an I path and a Q path, where:

the DWA module mainly converts the digital signal output by the quantizer to be transmitted to the DACI + DACQ, and the feedback digital-to-analog conversion device DACI + DACQ feeds back a first feedback signal I and a second feedback signal Q to the in-phase signal input path 31 and the quadrature signal input path 32, respectively, under the control of the driving circuit.

A common way to eliminate the mismatch of the IQ two-way feedback DAC is to exchange the IQ two-way DAC current sources (not shown) according to a certain rule, and one specific way is to exchange the IQ two-way current sources when the IQ two-way feedback DAC input signals are the same, and not to exchange the IQ two-way current sources when the IQ two-way feedback input signals are different.

The multi-bit feedback DAC is very commonly used in the design of the low-power SD ADC, and the mismatch of the multi-bit DAC itself is also a serious problem, which causes the performance of the modulator to be seriously degraded. Therefore, for the DAC of the I path or the Q path, the DAC unit is randomly selected according to certain requirements, so that the mismatch is dispersed into noise, and then the noise is pushed to a high frequency position through noise shaping. Therefore, besides the IQ two-path DAC needs to be exchanged, the I path DAC unit and the Q path DAC unit need to be switched. Current steering DACs are one of the common DAC implementations.

However, the above implementation has a problem that the switches of the IQ two-path current source and the switches of the switching current source increase the number of switches, and it is difficult to ensure that the switches connected to each current source are not turned off at the same time under any input, which causes the current sources to be re-established, and further causes the demodulation performance of the complex continuous time SDADC to be degraded.

In order to achieve that a current source does not need to be reestablished under any condition, stability of a current source driving circuit is improved, and performance of an ADC is improved, an embodiment of the present disclosure provides a current source driving circuit, which includes a latch circuit module, a driving circuit module, and a differential complementary circuit module that are sequentially coupled, where the differential complementary circuit module includes two switch set submodules that are complementary, each of the switch set submodules is coupled to one of a first current source branch and a second current source branch, and the switch set submodules include a plurality of switches that are coupled to each other, and output a first latch signal and a first latch inverted signal based on a first input signal through the latch circuit module, and output a second latch signal and a second latch inverted signal based on a second input signal through the latch circuit module, and further output a second latch signal and a second latch inverted signal based on the first latch signal by the driving circuit module, The first latch inverted signal, the second latch signal and the second latch inverted signal output multiple switch signals to the switch group submodule of the differential complementary circuit module, so that switches in the switch group submodule corresponding to any current source branch are in a conducting state at any moment to drive current sources in the corresponding current source branch, in other words, all switches connected with the current sources are not closed at the same time, therefore, the current sources do not need to be re-established under any condition, and the performance of an analog-to-digital converter and a receiver applying the current sources can be improved.

For a better understanding and appreciation of the illustrative embodiments by those skilled in the art, reference will now be made to the accompanying drawings, in which, in connection with the specific application, illustrated embodiments will be described in detail.

Referring to a schematic structural diagram of the current source driving circuit shown in fig. 4, in this embodiment, as shown in fig. 4, the current source driving circuit 40 is adapted to drive a current source, and more specifically, may drive current sources on the first current source branch 4A and the second current source branch 4B respectively, and the current source driving circuit 40 may include: a latch circuit block 41, a differential complementary circuit block 43, and a driving circuit block 42, wherein:

the latch circuit module 41 is adapted to output a first latch signal data1p and a first latch inverted signal data1n based on the first path of input signal data1, and output a second latch signal data2p and a second latch inverted signal data2n based on the second path of input signal data 2;

differential complementary circuit module 43, comprising: two complementary switch set sub-modules (e.g., a first switch set sub-module 431 and a second switch set sub-module 432), wherein: any switch set submodule is respectively coupled with one current source branch of the first current source branch 4A and the second current source branch 4B, and the switch set submodule comprises a plurality of coupled switches;

a driving circuit block 42 coupled to the latch circuit block 41 and the differential complementary circuit block 43, respectively, and adapted to output multi-way switch control signals (e.g., multi-way switch control signals SWi, SWj) to switch group sub-blocks of the differential complementary circuit block 43, such as the first switch group sub-block 431 and the second switch group sub-block 432, based on the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p and the second latch inverted signal data2n, so that at any moment, switches in the switch group submodules corresponding to any current source branch (for example, the first current source branch 4A and the second current source branch 4B) are in a conducting state, to drive a current source in a respective current source branch, e.g. the first current source branch 4A or the second current source branch 4B.

With the current source driving circuit, the latch module 41 outputs the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p and the second latch inverted signal data2n based on the first input signal data1 and the second input signal data2, and the driving circuit module 42 outputs the multi-way switch control signal to the switch group submodule in the differential complementary circuit module 43 based on the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p and the second latch inverted signal data2n, since any one of the two complementary switch group submodules in the differential complementary circuit module 43 is coupled to one of the first current source branch and the second current source branch respectively, the switch group submodule includes a plurality of switches, therefore, no matter the first input signal data1 and the second input signal data2 are the same or different, or the first input signal data1 and the second input signal data2 are matched with the latch circuit module 41 and the differential complementary circuit module 43 during the switching process, the switches in the switch group sub-modules corresponding to the first current source branch and the second current source branch can be in the on state by the driving circuit module 42, that is, at any time, in the case that the first input signal and the second input signal are any signals, the current source in any current source branch driven by the current source driving circuit 40 will not be turned off, so that the current source can be prevented from being re-established, and the performance of the ADC using the current source can be enhanced.

For better understanding and implementation by those skilled in the art, the following shows some specific circuit structures capable of implementing that at any time, a switch in a switch group submodule corresponding to any current source branch is in a conducting state, so as to drive a current source in the corresponding current source branch. The circuit configurations of the latch circuit block, the differential complementary circuit block, and the driver circuit block are respectively explained below as examples.

In a specific implementation, the latch circuit module may include: and the input end of any latch submodule is suitable for inputting the first path of input signal or the second path of input signal, the first output end of the latch submodule is suitable for outputting a latch signal which is in phase with the input signal of the corresponding path, and the second output end of the latch submodule is suitable for outputting a latch inverted signal which is inverted with the input signal of the corresponding path.

In a specific example of the present specification, the latch submodule includes: a first not gate, a second not gate and a latch coupled in sequence, wherein: the first input end of the latch is coupled with the output end of the first NOT gate, the second input end of the latch is coupled with the output end of the second NOT gate, the first output end of the latch is suitable for outputting the latching signal of the corresponding path, and the second output end of the latch is suitable for outputting the latching inverted signal of the corresponding path.

Referring to fig. 5, a circuit structure of a latch circuit block is schematically shown, the latch circuit block 50 includes: two first latch submodule 51 and second latch submodule 52 having the same structure, wherein:

the first latch submodule 51 includes: a first NOT gate NOT11, a second NOT gate NOT12, and a first latch 51A coupled in series, wherein: the first NOT11 delays and inverts the first path of input signal data1 to output a first delayed and inverted signal m; the second NOT gate NOT12 delays and inverts the output second delayed and inverted signal n based on the first delayed and inverted signal m; a first input terminal of the first latch 51A is coupled to the output terminal of the first NOT gate 11, a second input terminal of the first latch 51A is coupled to the output terminal of the second NOT gate 12, a first output terminal of the first latch 51A is adapted to output the latch signal of the corresponding path, i.e., the first latch signal data1p, and a second output terminal of the first latch 51A is adapted to output the latch inverted signal of the corresponding path, i.e., the first latch inverted signal data1 n.

As a specific example, the first latch 51A may specifically include: a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM4, and a fourth NMOS transistor NM4, wherein: the gate of the third NMOS transistor is used as a first input terminal of the first latch 51A, and is adapted to input the first delayed inverted signal m; a gate of the fourth NMOS transistor NM4, serving as a second input terminal of the first latch 51A, is adapted to input the second delayed inverted signal n; the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both coupled to a power supply VCC; drains of the first, second, third and fourth NMOS transistors NM1, NM2, NM3 and NM4 are all coupled with ground; the source of the first NMOS transistor NM1, the source of the third NMOS transistor NM3, and the drain of the first PMOS transistor PM1, and the gate of the second NMOS transistor NM2 and the gate of the second PMOS transistor PM2 are cross-coupled and adapted to output the first latch signal data1 p; the source of the second NMOS transistor NM2, the source of the fourth NMOS transistor NM4, and the drain of the second PMOS transistor PM2, and the gate of the first NMOS transistor NM1 and the gate of the first PMOS transistor PM1 are cross-coupled and adapted to output the first latch inverted signal data1 n.

Similarly, the second latch submodule 52 may include the same structural circuit as the first latch submodule 51. As a specific example, the second latch submodule 52 may include: a third NOT gate NOT21, a fourth NOT gate NOT22, and a second latch 52A coupled in series, wherein: the third NOT21 delays and inverts the second path of input signal data2 to output a third delayed inverted signal x; the fourth NOT gate NOT22 delays and inverts the output of the fourth delayed inverted signal y based on the third delayed inverted signal x; the first input terminal of the second latch 52A is coupled to the output terminal of the third NOT gate NOT21 and is adapted to input the third delayed inverted signal x, the second input terminal of the second latch 52A is coupled to the output terminal of the fourth NOT gate NOT22 and is adapted to input the fourth delayed inverted signal y, the first output terminal of the second latch 52A is adapted to output the latched signal of the corresponding path, i.e., the second latched signal data2p, and the second output terminal of the second latch 52A is adapted to output the latched inverted signal of the corresponding path, i.e., the second latched inverted signal data2 n.

With continued reference to fig. 5, the second latch 52A may have the same structure as the first latch 51A, and as a specific example, the second latch 52A may include: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8, wherein: the gate of the seventh NMOS transistor is adapted to input the third delayed inverted signal x; the gate of the eighth NMOS transistor NM8 is adapted to input the fourth delayed inverted signal y; the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4 are both coupled to a power supply VCC; drains of the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8 are all coupled with ground; a source of the fifth NMOS transistor NM5, a source of the seventh NMOS transistor NM7, and a drain of the third PMOS transistor PM3, and a gate of the sixth NMOS transistor NM6 and a gate of the fourth PMOS transistor PM4 are cross-coupled and adapted to output the second latch signal data2 p; a source of the sixth NMOS transistor NM6, a source of the eighth NMOS transistor NM8, and a drain of the fourth PMOS transistor PM4, and a gate of the fifth NMOS transistor NM5 and a gate of the seventh PMOS transistor PM7 are cross-coupled, and adapted to output the second latched inverted signal data2 n.

With the latch circuit module, intermediate node signals m, n, x and y are respectively generated based on input signals data1 and data2, and output signals are obtained based on the intermediate node signals m, n, x and y: data1p, data1n, data2p, and data2 n. With the latch circuit module with the above structure, because the first NOT gate 11, the second NOT gate NOT12, the third NOT gate NOT21, the fourth NOT gate NOT22, and the first latch 51A and the second latch 52A are the most basic circuit units, the delay of the edges of the first latch signal data1p and the first latch inverted signal data1n and the delay of the edges of the second latch signal data2p and the second latch inverted signal data2n can be reduced, so that the switching performance during the switching process of the first input signal data1 and the second input signal data2 can be further improved, and the switching efficiency can be improved.

In a specific implementation, the first latch 51A and the second latch 52A may also adopt latches of other structures as long as the first latch signal data1p and the first latch inverted signal data1n that are synchronously inverted can be output based on the first delayed inverted signal m and the second delayed inverted signal n, and the second latch signal data2p and the second latch inverted signal data2n that are synchronously inverted can be output based on the third delayed inverted signal x and the fourth delayed inverted signal y.

It is understood that the latch circuit block may also have other forms of latch structures. In a specific embodiment of the present disclosure, two latch sub-modules with the same structure in the latch circuit module may be composed of only two nor gates connected in series. Specifically, referring to fig. 5, the first latch submodule 51 may include only: the first NOT11 and the second NOT12 connected in series in sequence; the second latch submodule 52 may include only: the third NOT21 and the fourth NOT22 are connected in series in sequence. In this embodiment, the output signal m of the first NOT gate NOT11 can be directly used as the first latch inverted signal data1n, and the output signal n of the second NOT gate NOT12 can be used as the first latch signal data1 p; and directly taking the output signal x of the third NOT gate NOT21 as the second latch inverted signal data2n and taking the output signal y of the fourth NOT gate NOT22 as the second latch signal data2 p. In a specific implementation, the timings of the first latching signal data1p, the first latching inverted signal data1n, the second latching signal data2p and the second latching inverted signal data2n may be adjusted in the subsequent driving circuit modules, so that the timings of the four are kept synchronous.

In order to make those skilled in the art better understand and implement some exemplary schemes in the embodiments of the present disclosure, the current source in any current source branch is driven by making a switch in a switch group submodule corresponding to any current source branch at any time in a conducting state, so as to avoid current source reconstruction.

Fig. 6 shows a connection relationship diagram of each module in a current source driving circuit, fig. 7 shows a structural diagram of a differential complementary circuit module, fig. 8 shows a structural diagram of a driving circuit module, and the driving principle of the current source driving circuit is described in detail below with reference to fig. 6 to 8.

In some embodiments of the present disclosure, the differential complementary circuit module may be a fully differential complementary circuit module, and may also be a half differential complementary circuit module. Fig. 7 shows a fully differential complementary circuit module, wherein a fully differential complementary circuit 70 is coupled to the first current source branch and the second current source branch, respectively, to form a fully differential complementary current source. Wherein, the first current source branch I1 includes: a first branch first current source Ip1 and a first branch second current source In1 coupled In opposite directions between the power source VCC and ground; the second current source branch includes: a second branch current source Ip2 and a second branch current source In2 coupled between the power source VCC and the ground, and having opposite current directions, respectively, and including two output terminals having opposite current directions. Specifically, as shown in fig. 7, the first current source branch includes: the first output terminal iop1 and the second output terminal ion1 have opposite current flow directions; the second current source branch includes: the current flows to the opposite first output terminals iop2 and ion 2.

A current source driving circuit as shown in fig. 6, wherein the current source driving circuit 60 comprises a latch circuit module 61, a driving circuit module 80, and a differential complementary current source 70, wherein the differential complementary current source has a differential complementary circuit module, the first current source branch and the second current source branch integrated therein. The following is a brief explanation of the working principle based on the signal flow direction:

the latch circuit module 61 may output the first latch signal data1p and the first latch inverted signal data1n based on the input first input signal data1, and output the second latch signal data2p and the second latch inverted signal data2n based on the input second input signal data 2. Further, the driving circuit module 62 respectively outputs swn1_ o, swn1_ inv _ o, swp1_ o, swp1_ inv _ o, ex _ swn1_ o, ex _ swn1_ inv _ o, ex _ swp1_ o, ex _ swp1_ inv _ o, swn2_ o, swn2_ inv _ o, swp2_ o, swp2_ inv _ o, ex _ swn2_ o, ex _ swn2_ inv _ o, ex _ swp2_ o, ex _ swp2_ inv _ o to the differential complementary current source 70 based on the first latching signal data1p, the first latching inverting signal data1n, the second latching signal data2p, and the second latching inverting signal data2 n.

In a specific implementation, for any one of the switch group sub-modules in the differential complementary circuit module, the switch group sub-module may include: a conducting switch unit and a transfer switch unit, wherein:

the conduction switch unit comprises a current source coupled between the corresponding current source branch and the corresponding current source branch output end, and is suitable for conducting a current source output channel formed by the current source on the corresponding current source branch and the corresponding branch output end based on the received switch enabling control signal;

the switch unit is coupled between the output ends of different current source branches and is suitable for switching the output end of the current source coupled with the switch unit based on the received switch enabling control signal.

As can be seen from the above, the conducting switch unit includes a plurality of conducting switches, and the switch unit includes a plurality of switches.

With reference to fig. 6 and 7, in the fully differential complementary circuit module 7A shown in fig. 7, a plurality of MOS transistors coupled between the first current source branch and the second current source branch are used as a conducting switch or a transfer switch to form a fully differential complementary current source 70, which includes a plurality of N-type transistors and P-type transistors, so as to distinguish the N-type transistors and the P-type transistors from the transistors in the latch circuit module, hereinafter, the NMOS-type transistors in the fully differential complementary circuit module are collectively referred to as N-type switching transistors, which are abbreviated as N-type transistors, and the PMOS-type transistors in the fully differential complementary circuit module are collectively referred to as P-type switching transistors, which are abbreviated as P-type transistors.

Specifically, as shown in fig. 7, in the fully differential complementary circuit 70, the first N-type tube N1, the second N-type tube N2, the first P-type tube P1, and the second P-type tube P2 are conducting switches, and the first complementary fully differential current source I01 is formed by the current sources I1P and I1N of the first current source branch I1, where swn1, swp1, swn1_ inv, and swp1_ inv are switch enable control terminals, complementary signals are received by the switch enable control terminals swn1 and swn1_ inv, and complementary signals are received by the switch enable control terminals swp1 and swp1_ inv; current sources I2P and I2N of the third N-type tube N3, the fourth N-type tube N4, the third P-type tube P3, the fourth P-type tube P4 and the second current source branch I2 constitute a second complementary fully differential current source I02, wherein swn2, swp2, swn2_ inv and swp2_ inv are switch enable control terminals, complementary signals are received by the switch enable control terminals swn2 and swn2_ inv, and complementary signals are received by the switch enable control terminals swp2 and swp2_ inv; the outputs of the complementary fully differential current sources Ip1, In1 are iop1 and ion 1; the outputs of the complementary fully differential current sources Ip2, In2 are iop2 and ion 2. A fifth N-type pipe N5, a sixth N-type pipe N6, a seventh N-type pipe N7, an eighth N-type pipe N8, a fifth P-type pipe P5, a sixth P-type pipe P6, a seventh P-type pipe P7, and an eighth P-type pipe P8 are used as switches of the first complementary fully-differential current source I01 and the first complementary fully-differential current source I02, and ex _ swn1, ex _ swp1, ex _ swn2, ex _ swp2, ex _ swn1_ inv, ex _ swp1_ inv, ex _ swn2_ inv, and ex _ swp2_ inv are enable control terminals of the switches.

Referring to a schematic structural diagram of the driving circuit module shown in fig. 8, a specific scheme is illustrated in which the driving circuit module controls on/off of a switch in the differential circuit module based on a signal output by the latch circuit module, so that the switch is in a conducting state in a switch group submodule corresponding to any current source branch at any time.

In some embodiments of the present description, as shown in fig. 8, the driving circuit module 80 includes: logic control

The driving circuit module includes: a logic control submodule 81, and two non-overlapping clock submodules, namely a first non-overlapping clock submodule 82 and a second non-overlapping clock submodule 83, which are respectively coupled to the logic control submodule and have the same structure, wherein:

the logic control submodule 81 is adapted to perform a preset logic operation based on the first latch signal data1p and the second latch signal data2p, and output a first control signal a and a second control signal b.

And the two non-overlapping clock submodules respectively output a switch control signal to the complementary switch group submodules, wherein for any non-overlapping clock submodule, a plurality of paths of switch control signals are output to the switch group submodule corresponding to the corresponding current source branch based on the latch signal, the latch inverted signal, the first control signal a and the second control signal b input by the corresponding latch submodule respectively, so that a switch of the switch group submodule corresponding to the corresponding current source branch is in a conducting state at any moment.

Specifically, as shown in fig. 8, the first non-overlapping clock submodule 82 is adapted to output a plurality of switch control signals to the switch group submodule corresponding to the first current source branch I1 based on the input first latch signal data1p, the first latch inverted signal data1n, the first control signal a, and the second control signal b, so that a switch of the switch group submodule corresponding to the first current source branch I1 is in a conducting state at any time;

the second non-overlapping clock submodule 83 is adapted to output a plurality of switch control signals to the switch group submodule corresponding to the second current source branch I2 based on the input second latch signal data2p, the second latch inverted signal data2n, the first control signal a, and the second control signal b, so that a switch of the switch group submodule corresponding to the second current source branch I2 is in a conducting state at any time.

In some embodiments of the present description, with continued reference to fig. 8, the logic control sub-module 81 may include: an exclusive or gate unit XOR, a first delay unit delay1 and a second delay unit delay2, wherein:

the exclusive-or gate unit XOR having a first input adapted to input the first latch signal data1p, a second input adapted to input the second latch signal data2p, and outputs coupled to the input of the first delay unit delay1 and the first input of the second delay unit delay2, respectively;

the first delay unit delay1 has an input coupled to the output of the XOR gate unit XOR and an output adapted to output the first control signal a, and is coupled to a second input of the second delay unit delay 2;

the second delay unit delay2, adapted to output the second control signal b;

wherein: the delay time duration of the second delay unit delay2 is smaller than the delay time duration of the first delay unit delay 1.

As a specific example, the second delay unit delay2 includes: a first NAND gate unit NAND1 and a fifth NOT gate NOT5, wherein:

a first NAND-gate unit NAND1 having a first input coupled to the output of the XOR-gate unit XOR and to the input of the first delay unit delay1, a second input coupled to the output of the first delay unit delay1, and adapted to input the first control signal a, and an output coupled to the input of the fifth NOT-gate NOT 5;

the fifth NOT gate NOT5 has an input coupled to the output of the first NAND gate unit NAND1 and an output adapted to output the second control signal b.

In a specific implementation, the non-overlapping clock sub-modules may include: two mutually-overlapped clock units with the same structure and coupled to each other may include, as a specific example: a third delay unit, a second nand gate unit, a first nor gate unit, and a sixth not gate, wherein:

the first input end of the third delay unit corresponds to the overlapped clock submodule, the third delay unit is suitable for correspondingly inputting one of the first latch signal, the first latch inverted signal, the second latch signal and the second latch inverted signal, the second input end of the third delay unit is suitable for being coupled with the output end of the third delay unit of another non-overlapped clock unit in the same non-overlapped submodule and comprises two inverted first output ends and two inverted second output ends, and the delay time length of the third delay unit is smaller than that of the first delay unit and is larger than that of the second delay unit;

a first input end of the second nand gate unit is suitable for being coupled with a first output end of the third delay unit, a second input end of the second nand gate unit is suitable for inputting the first control signal, and an output end of the second nand gate unit is suitable for outputting a corresponding switch control signal to a control switch coupled with the second nand gate unit to control the on-off of the control switch coupled with the second nand gate unit;

the first nor gate unit has a first input terminal coupled to the second output terminal of the third delay unit, a second input terminal coupled to the second control signal, and an output terminal coupled to the output terminal of the sixth not gate;

the sixth NOT gate is suitable for outputting a corresponding switch control signal to the control switch coupled with the sixth NOT gate and controlling the on-off of the control switch coupled with the sixth NOT gate;

the input end of the seventh not gate is coupled to the output end of the second nand gate unit, and the output end of the seventh not gate is suitable for outputting a corresponding switch control signal to the control switch coupled thereto to control the on-off of the control switch coupled thereto;

and the input end of the eighth not gate is suitable for being coupled with the output end of the sixth not gate, and the output end of the eighth not gate is suitable for outputting a corresponding switch control signal to the control switch coupled with the eighth not gate to control the on-off of the control switch coupled with the eighth not gate.

As a specific example, the third delay unit may include: and gate, fourth delay unit and ninth not gate coupled in order, wherein: an output end of the ninth not gate is used as a first output end of the third delay unit, and an output end of the fourth delay unit is used as a second output end of the third delay unit.

In a specific implementation, the delay time duration of the first delay unit is greater than the delay time duration of the fourth delay unit.

For a better understanding and implementation by those skilled in the art, a specific circuit structure of the first non-overlapping clock submodule 82 shown in fig. 8 is explained below.

The first non-overlapping clock sub-module 82 includes: two mutually-non-overlapping clock units with the same structure and coupled with each other, namely a first mutually-non-overlapping clock unit 82A and a second mutually-non-overlapping clock unit 82B, wherein:

the first non-overlapping clock unit 82A includes: a third delay unit delay3, a second NAND gate unit NAND2, a first NOR gate unit NOR1, a sixth NOT gate NOT6, a seventh NOT gate NOT7 and an eighth NOT gate NOT8, wherein:

the third delay unit delay3, a first input of which corresponds to the crossover clock submodule, is adapted to correspond to the input of the first latch signal data1p, a second input of which is adapted to be coupled to the output of the third delay unit delay3 of the second non-crossover clock unit 82B, and comprises two inverted first and second outputs, and the delay duration of the third delay unit delay3 is smaller than the delay duration of the first delay unit delay1 and is greater than the delay duration of the second delay unit delay 2.

The first input terminal of the second NAND gate unit NAND2 is adapted to be coupled to the first output terminal of the third delay unit delay3, the second input terminal thereof is adapted to input the first control signal a, and the output terminal thereof is adapted to output the corresponding switch control signal swp1_ o to the control switch coupled thereto, so as to control the on/off of the control switch coupled thereto. As can be seen from fig. 6 to 8, after the signal in the first non-overlapping clock unit 82A passes through the NAND gate NAND2, the output switch control signal is suitable for controlling the second P-type pipe P1 in the fully differential complementary circuit module 70, and when the output signal is at a low level, the second P-type pipe P2 is turned on, and the current source Ip1 in the first current source branch I1 can output a current through the output terminal ion 1.

The first NOR gate unit NOR1 has a first input terminal adapted to be coupled to the second output terminal of the third delay unit dealy3, a second input terminal adapted to input the second control signal b, and an output terminal coupled to an output terminal of the sixth NOT gate NOT6, and the sixth NOT gate NOT6 is adapted to output a corresponding switch control signal to the control switch coupled thereto, so as to control the on/off of the control switch coupled thereto. As can be seen from fig. 6, 7 and 8, the controlled switch is an eighth P-type transistor P8, and when the eighth P-type transistor P8 is turned on, the current source Ip1 in the first current source branch I1 can output current through the output terminal ion 2.

The input end of the seventh NOT gate NOT7 is coupled to the output end of the second NAND gate unit NAND2, and the output end of the seventh NOT gate NOT7 is adapted to output a corresponding switch control signal to the control switch coupled thereto, so as to control the on/off of the control switch coupled thereto. As can be seen from fig. 6 to 8, the controlled switch is the first N-type transistor N1, and when the first N-type transistor N1 is turned on, the current source In1 In the first current source branch I1 can flow a current through the output terminal iop 1.

The input end of the eighth NOT gate NOT8 is adapted to be coupled to the output end of the sixth NOT gate NOT6, and the output end thereof is adapted to output a corresponding switch control signal to the control switch coupled thereto, so as to control the on/off of the control switch coupled thereto. As can be seen from fig. 6, 7 and 8, the controlled switch is a fifth N-type transistor N5, and when the fifth N-type transistor N5 is turned on, the current source In1 In the first current source branch I1 can flow a current through the output terminal iop 2.

With reference to fig. 6 to 8, it can be seen that a control relationship between the switch control signal output by each output terminal in the driving circuit module 80 shown in fig. 8 and each switch in the fully differential complementary circuit module shown in fig. 7 is shown, and by the driving circuit module 80, it can be realized that none of the switches connected to any current source in fig. 7 is turned off at the same time.

The following briefly describes the operation characteristics of the current source drive circuit in the embodiment adopted in this specification.

In any case (including the first input signal data1 and the second input signal data2 being both 1 at the same time, 0 at the same time, or one of 0 and one of 1):

1) the N-type transistors N1, N2, N5, N8 connected to the current source In1 are not turned off at the same time, i.e., the switch enable control terminals swp1_ inv, swn1_ inv, ex _ swn1_ inv, ex _ swp1_ inv are not turned low at the same time;

2) the N-type transistors N3, N4, N6, N7 connected to the current source In2 are not turned off at the same time, i.e., the switch enable control terminals swp2_ inv, swn2_ inv, ex _ swp2_ inv, ex _ swn2_ inv are not turned low at the same time;

3) the P-type transistors P1, P2, P5, and P8 connected to the current source Ip1 are not turned off at the same time, that is, the switch enable control terminals swn1, swp1, ex _ swn1, and ex _ swp1 are not turned high at the same time;

4) the P-type transistors P3, P4, P6, and P7 connected to the current source Ip2 are not turned off at the same time, that is, the switch enable control terminals swn2, swp2, ex _ swn2, and ex _ swp2 are not turned high at the same time.

5) When the first input signal data1 and the second input signal data2 are the same, the current sources Ip1 and In1 of the first current source branch flow into or out of the output terminals iop1 and ion1, and the current sources Ip2 and In2 of the second current source branch flow into or out of the output terminals iop2 and ion 2;

6) when the first input signal data1 and the second input signal data2 are different, the current sources Ip1 and In1 of the first current source branch flow into or out of the output terminals iop2 and ion2, and the current sources Ip2 and In2 of the second current source branch flow into or out of the output terminals iop1 and ion 1.

When a signal at a control end of a current source switch changes, the working characteristics can avoid a process that a current source needs to be reestablished because a switch connected with the current source is simultaneously turned off in the switching process of the first path and the second path.

As for the first input signal data1 and the second input signal data2, as described above, it is possible that both are 0 (corresponding to a low level) and both are 1 (corresponding to a high level), one of them is switched from 0 to 1, and one of them is switched from 1 to 0. Correspondingly, the first latch signal data1p and the second latch signal data2p are output after the corresponding delay of the latch circuit module, the first latch signal data1p is consistent with the first input signal data1, and the second latch signal data2p is consistent with the second input signal data 2. Referring to the waveform diagrams of the switch control signals of the corresponding switch bank submodule during the switching of the input signals shown in fig. 9A to 9D, voltage waveform diagrams of the switch enable signals swn1, swp1, ex _ swn1, and ex _ swp1 corresponding to the transistors P1, P2, P5, and P8 in each case corresponding to the first latch signal data1P and the second latch signal data2P are shown.

Specifically, fig. 9A shows voltage waveform diagrams of corresponding latch signals and corresponding switches during the first latch signal data1p is kept at 0, and the second latch signal data2p is switched from 0 to 1. Referring to fig. 6-8 in combination with fig. 9A, as can be seen from fig. 9A, when both the first latch signal data1P and the second latch signal data2P are 0, the switch enable signal swn1 corresponding to the transistor P1 is 0, and therefore, the first current source Ip1 coupled thereto is not turned off; during the switching of the second latch signal data2P from 0 to 1, as can be seen from fig. 9A, one of the transistors P2, P5, P8 is always kept at 0, so that the first current source Ip1 coupled thereto is always in a conducting state, and after the switching is completed, the transistor P5 is kept at 0, so that the first current source Ip1 can output a current through the output terminal iop 2.

Fig. 9B shows a voltage waveform diagram of the corresponding latch signal and the corresponding switch during the switching of the first latch signal data1p from 0 to 1 and the synchronization of the second latch signal data2p from 1 to 0, that is, the situation of the corresponding switching current source. Referring to fig. 6-8 in conjunction with fig. 9B, as can be seen from fig. 9B, when the first latch signal data1P is 0 and the second latch signal data2P is 1, the switch enable signal ex _ swn1 corresponding to the transistor P5 is 0, and therefore the first current source Ip1 coupled thereto is not turned off; during the switching of the second latch signal data2P from 0 to 1, as can be seen from fig. 9B, the transistor P5 remains at 0, so that the first current source Ip1 coupled thereto is still in a conducting state, and after the switching is completed, the transistor P2 remains at 0, so that the first current source Ip1 can output a current through the output terminal ion 1.

Fig. 9C illustrates voltage waveform diagrams of corresponding latch signals and corresponding switches in a process in which the first latch signal data1p switches from 0 to 1, and the second latch signal data2p always remains as 1. Referring to fig. 6-8 in conjunction with fig. 9C, as can be seen from fig. 9C, when the first latch signal data1P is 0 and the second latch signal data2P is 1, the switch enable signal ex _ swn1 corresponding to the transistor P5 is 0, and therefore the first current source Ip1 coupled thereto is not turned off; during the switching of the first latch signal data1P from 0 to 1, as can be seen from fig. 9C, the transistor P5 remains at 0, so that the first current source Ip1 coupled thereto is still in a conducting state, and after the switching is completed, the transistor P8 remains at 0, so that the first current source Ip1 can output a current through the output terminal ion 2.

Fig. 9D shows voltage waveform diagrams of the corresponding latch signal and the corresponding switch during the switching of the first latch signal data1p from 1 to 0 and the switching of the second latch signal data2p from 1 to 0 in synchronization. Referring to fig. 6-8 in combination with fig. 9D, as can be seen from fig. 9D, when the first latch signal data1P is 1 and the second latch signal data2P is 1, the switch enable signal ex _ swp1 corresponding to the transistor P8 is 0, so that the first current source Ip1 coupled thereto is not turned off, and a current is output through the output terminal ion 2; during the synchronous switching of the first latch signal data1P and the second latch signal data2P from 1 to 0, as can be seen from fig. 9D, the transistor P8 remains at 0, so that the first current source Ip1 coupled thereto is always in a conducting state, and after the switching is completed, i.e., after the synchronous switching of the first latch signal data1P and the second latch signal data2P to 0, the transistor P1 remains at 0, so that the first current source Ip1 can output a current through the output terminal iop 1.

As can be seen from the voltage waveform diagrams of the enable switch control signals of the transistors P1, P2, P5 and P8 coupled between the first current source Ip1 and the four output terminals respectively as described above, as a function of the first latch signal data1P and the second latch signal data2, no matter what the values of the first latch signal data1P and the second latch signal data2 are input, no matter how the first latch signal data1P and the second latch signal data2 are changed, the switches are always in the on state between the first current source Ip1 and the output terminals iop1, iop2, ion1 and ion2, and thus the first current source Ip1 is not turned off regardless of the changes of the first input signal data1 and the second input signal data2 even during fast switching.

Similarly, no matter how the first input signal data1 and the second input signal data2 change, at least one of the switches coupled to the first branch second current source In1, the second branch first current source Ip2, and the second branch second current source In2 and the output terminals iop1, iop2, ion1, and ion2 is always In a conducting state, so that In any case, the first branch second current source In1, the second branch first current source Ip2, and the second branch second current source In2 all have a conducting current flowing-In or flowing-out path, and the description is omitted here.

In an implementation, the differential complementary circuit module may be a half-differential complementary circuit module, and referring to the circuit structure diagram of the differential complementary circuit module shown In fig. 7, In an implementation, the differential complementary circuit module may be a differential complementary circuit module 7A coupled between the first branch first current source Ip1 and the second branch first current source Ip2 and the plurality of output terminals iop1, iop2, ion1 and ion2, In this case, the first branch second current source In1 and the second branch second current source In2 are directly connected between the plurality of output terminals iop1, iop2, ion1 and ion2, and the first branch first current source Ip1 and the second branch first current source Ip2 have current values. Similarly, the differential complementary circuit module used may also be the differential complementary circuit module 7B coupled between the first branch second current source In1 and the second branch second current source In2 and the output terminals iop1, iop2, ion1 and ion2, In which case the first branch first current source Ip1 and the second branch first current source Ip2 are directly connected between the plurality of output terminals iop1, iop2, ion1 and ion2, and the current values of the first branch second current source In1 and the second branch second current source In2 are doubled.

Correspondingly, the structures of the driving circuit modules corresponding to the half-differential complementary circuit modules 7A and 7B can be obtained through matching, referring to fig. 8, if a half-differential complementary circuit module 7A or 7B is adopted in the current source driving circuit as required, the corresponding driving circuit modules are not overlapped with each other, and the unused control signals in the clock units are kept open, that is, the driving circuit modules are not connected with other modules; alternatively, if it is determined that the current source driving circuit is only suitable for the half-differential complementary circuit module, the half-differential complementary circuit module 7A or 7B may NOT include corresponding devices, for example, the seventh NOT gate NOT7 and the eighth NOT gate NOT8 may NOT be included.

As can be seen from the above-mentioned operating characteristics 1) -4), the switches of any current source connected to each output terminal are not turned off at the same time, which means that there is a common on-time at the edge instant, and the common on-time can be obtained by adjusting the delay time of the fourth delay unit delay4 and the delay time of the first delay unit delay 1.

In high-speed application, the requirement on the delay time length is high, and for the delay time lengths t2, t3 and t1 corresponding to the delay units delay2, delay3 and delay1, except that t2 < t3 < t1, the shorter the absolute time of the delay is, the better the absolute time of the delay is. Therefore, in some embodiments of the present disclosure, a delay detection method is provided, which can minimize the absolute delay time based on the above condition.

Specifically, a delay calibration module may be coupled to the first delay unit delay1 and the fourth delay unit delay4, respectively, where the delay duration t4 of the fourth delay unit delay4 is initially set to be a fixed value, the delay duration t1 of the first delay unit delay1 is t1> t4, and the t1 is adjusted by a step size 1/2 that is equal to the total adjusted delay duration of the first delay unit delay1 ^N Then, a preset test clock signal is input into the delay calibration module, and the first delay unit delay1 is enabled to perform cumulative counting until the time duration corresponding to the first delay unit delay1 when the output of the delay calibration module meets a preset condition is the delay time duration of the first delay unit delay1 in the current source driving circuit.

In some embodiments of the present disclosure, as shown in the schematic structural diagram of the delay calibration module shown in fig. 10, the delay calibration module 100 may include a clock input unit CK, a first flip-flop D1, a second flip-flop D2, and two reset units RS1 and RS2 with the same structure, wherein:

the clock input unit CK, a first input terminal of which is adapted to input the test clock signal test _ clk, a second input terminal of which is adapted to input a test enable signal test _ en, and an output terminal of which is adapted to output the first clock signal clk to the first delay unit delay1 and the fourth delay unit delay 4;

the first flip-flop D1 has a D input terminal adapted to be coupled to the power supply VDD, a clock signal input terminal CK coupled to the output terminal of the fourth delay unit delay4, and an output terminal adapted to output the first detection signal q 1;

the second flip-flop D2 has a D input terminal adapted to be coupled to the power supply VDD, a clock signal input terminal CK coupled to the output terminal of the first delay unit delay1, and an output terminal adapted to output a second detection signal q 2;

the reset unit RS1 is adapted to output a reset signal RST1 to a reset terminal RST of a first flip-flop D1 coupled thereto based on an input reset signal;

the reset unit RS2 is adapted to output a reset signal RST2 to a reset terminal RST of a second flip-flop D2 coupled thereto based on an input reset signal;

wherein the preset condition is that the first detection signal q1 and the second detection signal q2 jump with the accumulation of the delay time lengths of the first delay unit delay 1.

More specifically, with continued reference to fig. 10, the clock input unit CK includes: a third NAND gate unit NAND3 and a tenth NOT gate NOT10 coupled in sequence, wherein:

the third NAND gate unit NAND3, having a first input adapted to input the test clock signal test _ clk, and a second input adapted to input a test enable signal test _ en;

the tenth NOT gate 10 is adapted to output the first clock signal clk0 based on the second clock signal clk1 output by the third NAND gate unit NAND 3.

As a specific example, the reset unit RS1 may include: a second NOR gate unit NOR2 and an eleventh NOR gate NOT9, wherein:

the second NOR gate unit NOR2 has a first input adapted to input the reset signal rst, a second input adapted to be coupled to an output q2 of a second flip-flop D2 (i.e., a flip-flop NOT to be reset), and an output adapted to be coupled to an input of the eleventh NOT gate NOT 11;

the eleventh NOT gate NOT11 is coupled to the reset terminal RST of the first flip-flop D1 (corresponding flip-flop to be reset).

The reset unit RS2 has the same structure as the reset unit RS1, and thus, the description thereof is omitted.

The following describes, with reference to fig. 11, an automatic calibration process of the delay calibration module shown in fig. 10 for obtaining the delay time duration of the first delay unit delay1 based on the delay time duration t4 of the fourth delay unit delay 4.

Before detection, the outputs of the first flip-flop D1 and the second flip-flop D2 are reset, q1 and q2 are both 0 (indicating low level), the delay time length t4 of the fourth delay unit delay4 is fixed, and the initial value of the first delay unit delay1 is adjusted. In a specific implementation, a multi-bit storage unit trim < X:0> may be used to store the setting value of the first delay unit delay 1. As a specific example, the 6-bit storage unit stores the setting value Trim <5:0> of the delay1, and based on the setting value Trim <5:0>, the delay time t1 of the first delay unit delay1 may be obtained.

When the set value trim <5:0> -000000, t1< t 4; when the set value trim <5:0> is 111111, t1> t4, at which time the test clock test _ clock is input. Observing the output, because t1< t4 is adjusted to be minimum, q1 is 0, q2 is 1(0 is low level, equivalent to ground GND, 1 is high level, equivalent to power supply VDD), next, adding 1 to Trim <5:0> value, repeating the above process until q1 is 1, q2 is 0, delay2> delay1, and the absolute time delay is minimum, when the calibration value delay1_ num is obtained, Trim <5:0> current accumulated count value, namely delay1_ num is Trim <5:0 >.

The calibration flowchart is shown in fig. 11, and may specifically include the following steps:

step S10, i.e. corresponding to the initial state, the test clock enable signal test _ en is set to 0, and the reset signal rst is set to 1;

step S11, the following settings are made: the reset signal rst is 0, trim <5:0> is 000000, and the test enable signal test _ en is 1.

Step S12, determining whether the output q1 of the first flip-flop is equal to 1 and the output q2 of the second flip-flop is equal to 0, if yes, performing step S13; otherwise, executing step S14;

step S13, the delay adjustment value delay _ num corresponding to the first delay unit delay1 is trim <5:0 >;

step S14, making Trim <5:0> +1, namely accumulating and counting the set value Trim <5:0 >;

in step S15, the test clock enable signal test _ en is reset to 0, and the reset signal rst is reset to 1.

After steps S11 to S13, if the absolute value of the difference between the delay time t1 of the first delay unit delay1 and the delay time t4 of the fourth delay unit delay4 is the smallest, then the delay1_ num corresponding to the first delay unit delay1 is taken as Trim <5:0>, and step S15 is executed, i.e. the delay calibration module returns to the initial state again.

In a specific implementation, the precision of the absolute value of the delay difference between the first delay unit delay1 and the fourth delay unit delay4 is related to the number of bits of the setting value trim < X:0>, and the greater the number of bits, the higher the relative precision and the smaller the absolute delay difference.

In specific implementation, before the current source driving circuit normally works, the automatic calibration circuit and the calibration process in the above embodiments may be used to perform full automatic calibration, so as to meet specific application requirements of the circuit.

It is understood that the reset units RS1 and RS2 may have other circuit structures, as long as the automatic calibration of the delay time duration of the first delay unit delay1 can be realized based on the delay time duration of the fourth delay unit delay 4.

By adopting the current source driving circuit in the embodiment of the specification, the current source path can be prevented from being closed for a short time in the switching process.

The current source driving circuit in the embodiment of the present disclosure may be applied to an analog-to-digital converter, and in order to make the implementation and understanding of the present disclosure better, the embodiment of the present disclosure further provides a corresponding analog-to-digital converter, and refer to a schematic structural diagram of an analog-to-digital converter shown in fig. 12, which may be used as a complex analog-to-digital conversion device, for example, in a complex continuous-time SDADC, and may be specifically applied to a receiver for radio frequency modulation.

As shown in fig. 12, the analog-to-digital converter 120 may include: a first input path 12I, a second input path 12Q, and a feedback path 12F, wherein:

the first input path 12I is adapted to obtain a first output signal outI based on a first input signal inQ and a first feedback signal I output by the feedback path 12F;

the second input path 12Q is adapted to obtain a second output signal outQ based on a second input signal inQ and the first feedback signal Q output by the feedback path 12F;

the feedback path 12F, coupled to the first input path 12I and the second input path 12Q respectively, includes: a first current source branch (not shown) and a second current source branch (not shown) and a current source drive circuit 12D and a feedback path analog-to-digital conversion device, wherein:

a first input terminal of the current source driving circuit 12D is coupled to the output terminal of the first input path, and the first output signal outI output by the first input path 12I is used as the first input signal data1 of the feedback path 12F; a second input end of the second input path 12Q is coupled to an output end of the second input path 12Q, a second output signal outQ output by the second input path 12Q is taken as a second input signal data2 of the feedback path 12F, the feedback path digital-to-analog converter and the first current source branch are turned on based on the first input signal data1 and the second input signal data2, and the second feedback path digital-to-analog converter and the second current source branch are turned on;

a feedback path digital-to-analog conversion device DACI + DACQ adapted to output the first feedback signal I to the first input path 12I and output the second feedback signal Q to the second input path 12Q based on switching control of the current source drive circuit 12D.

The current source driving circuit in the feedback path may adopt the current source driving circuit in any one of the foregoing embodiments in this specification, and specifically, reference may be made to the foregoing embodiments, and a description thereof is not repeated here.

With the analog-to-digital converter in the above embodiment, the current source driving circuit 12D may drive two DACs at the same time, and as a specific example, one DAC may drive an I DAC, that is, DACI; the other can drive a Q-way DAC, DACQ.

In the feedback path 12F, the DAC current sources of the I path and the Q path, that is, the current sources of the first current source branch and the second current source branch corresponding to DACI and DACQ, may be switched according to a certain rule, so as to reduce or eliminate the mismatch of the feedback DACs (that is, DACI + DACQ) corresponding to the I path and the Q path. For example, when the input signals data1 and data2 corresponding to the IQ two-way feedback DAC (i.e., DACI + DACQ) are the same, the current sources corresponding to the IQ two-way feedback DAC may be switched, i.e., switched; when the input signals data1 and data2 corresponding to the IQ two-way feedback DAC (i.e. DACI + DACQ) are different, the IQ two-way corresponding current sources do not need to be exchanged.

As can be seen from the foregoing embodiments, no matter what data is specifically input by the first (e.g., I) input signal data1 and the second (e.g., Q) input signal data2, or how the data is switched, the I and Q paths corresponding to the DACI have current sources turned on, so that the situation that the current sources are temporarily turned off and need to be reconstructed does not occur, and therefore, the mismatch of the feedback path 12F can be reduced, and the current source driving circuit 12D is applied to the analog-to-digital converter for signal demodulation, so that the demodulation performance can be improved.

In a specific implementation, each of the first input path 12I and the second input path 12Q may include: an adder and a quantizer, wherein: the adder is suitable for accumulating the input signal and the feedback signal of the corresponding channel to obtain a continuous signal; the quantizer is suitable for quantizing the continuous signal into a discrete signal so as to complete the basic function of analog-to-digital conversion.

As shown in fig. 12, the first input path 12I may include an adder 1 and a quantizer 1, and the second input path 12Q may include an adder 2 and a quantizer 2.

In a specific implementation, in order to filter quantization noise, each of the first input path 12I and the second input path 12Q further includes a filter, which may be disposed between the adder and the quantizer. In the loop, the filter can form a filter circuit together with other modules to filter out the in-band quantization noise. As shown in fig. 12, the first input path 12I further includes a filter 1, and the second input path 12Q further includes a filter 2.

In a specific implementation, the feedback path 12F may further include: a Data Weighted Averager (DWA), coupled between the output end of the corresponding input path and the current source driving circuit 12D, adapted to perform a predetermined transformation on the discrete signal quantized by the corresponding input path to obtain a digital signal after DWA transformation, where the feedback DAC (i.e. DACI + DACQ) can convert the digital signal after DWA transformation into an analog signal and send the analog signal to the input end of the modem, i.e. the input end of the first input path (I) and the input end of the second input path (Q).

As shown in fig. 12, the feedback path 12F may include DWAs 1 and DWAs 2, where: a DWA1 coupled between the output end of the first input path 12I and the current source drive circuit 12D; a DWA2 coupled between the output terminal of the second input path 12Q and the current source driving circuit 12D.

In a specific implementation, the feedback path digital-to-analog conversion device (DAC + DACQ) may employ a multi-channel feedback DAC, that is, for both the I-channel DAC and the Q-channel DAC, a plurality of DAC units may be employed, and the plurality of DAC units are all connected in parallel to the corresponding current source branches and share the current source output terminal.

In the embodiment of the present specification, the latch circuit module, the driver circuit module, the differential complementary circuit module and the corresponding current sources may form a basic current source unit, such as the structural schematic diagram of a multi-feedback DAC shown in fig. 13, as a specific example, the multi-feedback DAC130 includes 32 DAC units 13i, the 32 DAC units 13i may be connected in parallel, and for any DAC unit 13i in the 32 DAC units, the latch circuit module, the driver circuit module and the differential complementary circuit module (e.g., the fully differential complementary circuit module) shown in the foregoing embodiment of the present specification are included, and the output ends iop1, ion1, iop2 and ion2 of each current source branch are shared, as shown in fig. 13.

In addition, in the feedback path, the inputs of the plurality of DAC units and the outputs of the quantizers are in one-to-one correspondence, and even if DWA is arranged in the feedback path to change the correspondence between the two, the bit numbers of the two are kept consistent.

For example, the quantizer outputs a 5-level thermometer code, corresponding to outputs: 0000, 0001, 0011, 0111, 1111, having 4 bits. Because two paths of IQ are integrated together, 4 bits exist in the path I, 4 bits also exist in the path Q, and assuming that 4 bits corresponding to the path I are bitI3 bitI2 bitI1 bitI0 from high to low, 4 bits corresponding to the path Q are bitQ3 bitQ2 bitQ1 bitQ0 from high to low, the bit value of the corresponding bit is the input of one latch circuit module, for example, the bitI3 bitQ3 is the input of one latch circuit module, the bitI2 bitQ2 is the input of the other latch circuit module, and so on, the four latch circuit modules are totally arranged, the corresponding driving circuit module, the corresponding differential complementary circuit module and the corresponding current source are also divided into 4 groups, and the four groups of current sources share the output.

With DWA, the digital signal output from the quantizer is converted to be sent to the DAC, which can be used to eliminate the mismatch between multi-bit DAC cells, for example, the mismatch between 32 DAC cells 13i shown in fig. 13 can be eliminated.

In a specific implementation, the analog-to-digital converter can be applied to a receiver, for example, a low intermediate frequency receiver. In this embodiment, referring to a schematic structural diagram of a receiver shown in fig. 14, the receiver 140 may include: a demodulating means 141 and an analog-to-digital converter 142, wherein:

a demodulating means 141 adapted to demodulate a radio frequency input signal RF to obtain an in-phase and quadrature first input signal inI and a second input signal inQ;

the analog-to-digital converter 142 is adapted to perform analog-to-digital conversion on the first input signal and the second input signal to obtain a first path output signal outI and a second path output signal outQ.

The specific implementation of the analog-to-digital converter 142 may adopt the specific embodiments of the foregoing analog-to-digital converter, and will not be described herein.

In a specific implementation, to further improve the performance of the receiver, the receiver 140 may further include the following circuit devices:

the low noise amplifier LNA is suitable for carrying out low noise amplification processing on the input signal RF to obtain a voltage signal;

a transconductance amplifier gm adapted to convert the voltage signal subjected to the low noise amplification into a current signal and output the current signal;

and the trans-impedance amplifier TIA is suitable for converting the current signal into a voltage signal and outputting the voltage signal.

The positions and connection relationships of the above-described devices can be seen with reference to fig. 14.

In specific implementation, only a part of circuits or devices in the embodiments of the present specification may be used as needed, or a plurality of embodiments may be used in combination as needed.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims

1. A current source driver circuit adapted to drive a current source, comprising:

the latch circuit module is suitable for outputting a first latch signal and a first latch inverted signal based on the first path of input signal and outputting a second latch signal and a second latch inverted signal based on the second path of input signal;

2. The current source driving circuit according to claim 1, wherein the latch circuit block comprises: and the input end of any latch submodule is suitable for inputting the first path of input signal or the second path of input signal, the first output end of the latch submodule is suitable for outputting a latch signal in phase with the input signal of the corresponding path, and the second output end of the latch submodule is suitable for outputting a latch inverted signal in phase opposite to the input signal of the corresponding path.

3. The current source driving circuit of claim 2, wherein the latch submodule comprises: the first NOT gate and the second NOT gate are connected in series in sequence.

4. The current source driving circuit of claim 2, wherein the latch submodule comprises: a first not gate, a second not gate and a latch coupled in sequence, wherein: the first input end of the latch is coupled with the output end of the first NOT gate, the second input end of the latch is coupled with the output end of the second NOT gate, the first output end of the latch is suitable for outputting the latching signal of the corresponding path, and the second output end of the latch is suitable for outputting the latching inverted signal of the corresponding path.

5. The current source driving circuit according to claim 1, wherein the driving circuit module comprises: a logic control submodule, and a first non-overlapping clock submodule and a second non-overlapping clock submodule which are respectively coupled with the logic control submodule and have the same structure, wherein:

the logic control submodule is suitable for performing preset logic operation based on the first latching signal and the second latching signal and outputting a first control signal and a second control signal;

the first non-overlapping clock submodule is adapted to output a plurality of switch control signals to the switch group submodule corresponding to the first current source branch based on the input first latch signal, the first latch inverted signal, the first control signal and the second control signal, so that a switch of the switch group submodule corresponding to the first current source branch is in a conducting state at any time;

the second non-overlapping clock sub-modules are adapted to output multi-path switch control signals to the switch group sub-modules corresponding to the second current source branch based on the input second latch signal, the second latch inverted signal, the first control signal and the second control signal, so that switches of the switch group sub-modules corresponding to the second current source branch are in a conducting state at any time.

6. The current source driving circuit according to claim 5, wherein any one of the current source branches comprises: the current source circuit comprises a first current source, a second current source, a first current source and a second current source, wherein the first current source and the second current source are coupled between a power supply and ground in opposite flowing directions;

the switch block submodule includes: a conducting switch unit and a transfer switch unit, wherein:

7. The current source driving circuit of claim 6, wherein the logic control submodule comprises: exclusive-or gate unit, first delay unit and second delay unit, wherein:

the exclusive-or gate unit has a first input terminal adapted to input the first latch signal, a second input terminal adapted to input the second latch signal, and output terminals respectively coupled to the input terminal of the first delay unit and the first input terminal of the second delay unit;

the input end of the first delay unit is coupled to the output end of the exclusive-or gate unit, the output end of the first delay unit is suitable for outputting the first control signal, and the input end of the first delay unit is coupled to the second input end of the second delay unit;

the second delay unit is suitable for outputting the second control signal;

wherein: the delay time of the second delay unit is less than the delay time of the first delay unit.

8. The current source driving circuit according to claim 7, wherein the second delay unit comprises: a first nand gate cell and a fifth not gate, wherein:

the first nand gate unit has a first input terminal coupled to the output terminal of the exclusive-or gate unit and the input terminal of the first delay unit, a second input terminal coupled to the output terminal of the first delay unit, and an output terminal coupled to the input terminal of the fifth not gate;

and an input end of the fifth not gate is coupled to the output end of the first nand gate unit, and an output end of the fifth not gate is suitable for outputting the second control signal.

9. The current source driving circuit of claim 8, wherein the non-overlapping clock submodules comprise: two mutually-overlapped clock units with the same structure and mutually coupled, wherein the mutually-overlapped clock units comprise: a third delay unit, a second nand gate unit, a first nor gate unit, and a sixth not gate, wherein:

a first input end of the second nand gate unit is suitable for being coupled with a first output end of the third delay unit, a second input end of the second nand gate unit is suitable for inputting the first control signal, and an output end of the second nand gate unit is suitable for outputting a corresponding switch control signal to a conduction control switch coupled with the second nand gate unit to control the on-off of the conduction control switch coupled with the second nand gate unit;

and the sixth NOT gate is suitable for outputting a corresponding switch control signal to the switching control switch coupled with the sixth NOT gate so as to control the on-off of the switching control switch coupled with the sixth NOT gate.

10. The current source driving circuit according to claim 9, wherein the non-overlapping clock units further comprise: a seventh not gate and an eighth not gate, wherein:

the input end of the seventh not gate is coupled with the output end of the second nand gate unit, and the output end of the seventh not gate is suitable for outputting a corresponding switch control signal to the conduction control switch coupled with the seventh not gate to control the on-off of the conduction control switch coupled with the seventh not gate;

and the input end of the eighth not gate is suitable for being coupled with the output end of the sixth not gate, and the output end of the eighth not gate is suitable for outputting a corresponding switch control signal to the switching control switch coupled with the eighth not gate to control the on-off of the switching control switch coupled with the eighth not gate.

11. The current source driving circuit according to claim 9 or 10, wherein the third delay unit comprises: and gate, fourth delay unit and ninth not gate coupled in order, wherein: an output end of the ninth not gate is used as a first output end of the third delay unit, and an output end of the fourth delay unit is used as a second output end of the third delay unit.

12. The current source driving circuit according to claim 11, wherein a delay time period of the first delay unit is longer than a delay time period of the fourth delay unit.

13. The current source driving circuit according to claim 12, further comprising: a time delay calibration module, which is respectively coupled with the first time delay unit and the fourth time delay unit, wherein the time delay duration of the fourth time delay unit is initially set to be a fixed value, and the time delay adjustment step length of the first time delay unit is 1/2 of the total adjustment step length ^N And then inputting a preset test clock signal into the time delay calibration module, and enabling the first time delay unit to perform cumulative counting until the time corresponding to the first time delay unit when the output of the time delay calibration module meets a preset condition is the time delay time of the first time delay unit in the current source driving circuit.

14. The current source driving circuit according to claim 13, wherein the delay calibration module comprises: the reset circuit comprises a clock input unit, a first flip-flop, a second flip-flop and two reset units with the same structure, wherein:

the clock input unit has a first input end suitable for inputting the test clock signal, a second input end suitable for inputting a test enable signal, and an output end suitable for outputting a first clock signal to the first delay unit and the fourth delay unit;

the D input end of the first flip-flop is suitable for being coupled with a power supply, the clock signal input end of the first flip-flop is coupled with the output end of the fourth delay unit, and the output end of the first flip-flop is suitable for outputting a first detection signal;

the D input end of the second trigger is suitable for being coupled with a power supply, the clock signal input end of the second trigger is coupled with the output end of the first delay unit, and the output end of the second trigger is suitable for outputting a second detection signal;

any one of the reset units is suitable for outputting a reset signal to a reset end of the first flip-flop or the second flip-flop coupled with the reset unit based on an input reset signal;

the preset condition is that the first detection signal and the second detection signal jump with the accumulation of the delay time of the first delay unit.

15. The current source driving circuit according to claim 14, wherein the clock input unit comprises: a third nand gate unit and a tenth not gate coupled in sequence, wherein:

the first input end of the third nand gate unit is suitable for inputting the test clock signal, and the second input end of the third nand gate unit is suitable for inputting the test enable signal;

the tenth not gate is adapted to output the first clock signal based on the second clock signal output by the third nand gate unit.

16. The current source driving circuit according to claim 14, wherein the reset unit comprises: a second NOR gate unit and an eleventh NOR gate, wherein:

the first input end of the second NOR gate unit is suitable for inputting the reset signal, the second input end of the second NOR gate unit is suitable for being coupled with the output end of the trigger not to be reset, and the output end of the second NOR gate unit is suitable for being coupled with the input end of the eleventh NOR gate;

the eleventh NOT gate is coupled with the reset end of the corresponding trigger to be reset.

17. An analog-to-digital converter, comprising: a first input path, a second input path, and a feedback path, wherein:

the second input channel is suitable for obtaining a second output signal based on a second input signal and a second feedback signal output by the feedback channel;

a first current source branch;

a second current source branch;

the current source driving circuit as claimed in any one of claims 1 to 16, wherein a first input terminal of the current source driving circuit is coupled to an output terminal of the first input path, and the first output signal output by the first input path is used as a first input signal of the feedback path; a second input end of the second feedback path is coupled with an output end of the second input path, a second output signal output by the second input path is used as a second input signal of the feedback path, and the first feedback path digital-to-analog converter and the first current source branch are conducted and the second feedback path digital-to-analog converter and the second current source branch are conducted based on the first input signal and the second input signal;

18. The analog-to-digital converter of claim 17, wherein the first input path and the second input path each comprise: an adder and a quantizer, wherein:

the adder is suitable for accumulating the input signal and the feedback signal of the corresponding input channel to obtain a continuous signal;

the quantizer is adapted to quantize the continuous signal into a discrete signal.

19. The analog-to-digital converter according to claim 18, wherein each of said first and second input paths further comprises a filter disposed between said adder and said quantizer adapted to filter quantization noise.

20. The analog-to-digital converter according to claim 18, wherein said feedback path digital-to-analog converting means comprises: and the plurality of digital-to-analog conversion units respectively correspond to the corresponding input channels, respectively comprise the latch circuit module, the drive circuit module and the differential complementary circuit module, and share the output end of each current source branch.

21. The analog-to-digital converter of claim 20, wherein the feedback path further comprises:

and the data weighting averager is coupled between the output end of the corresponding input path and the current source driving circuit and is suitable for carrying out preset transformation on discrete signals obtained by quantizing the corresponding input path so as to eliminate mismatch among the plurality of digital-to-analog conversion units.

22. A receiver, comprising:

the demodulation device is suitable for demodulating the radio frequency input signal to obtain a first input signal and a second input signal which are in-phase and orthogonal;

an analog to digital converter as claimed in any of claims 17 to 21, adapted to perform analog to digital conversion on said first input signal and said second input signal to obtain a first path output signal and a second path output signal.

23. The receiver of claim 22, further comprising:

the low-noise amplifier is suitable for performing low-noise amplification processing on the input signal and outputting a voltage signal;

a transconductance amplifier coupled between the low noise amplifier and the demodulation device and adapted to convert a voltage signal output by the low noise amplifier into a current signal and output the current signal;

and the trans-impedance amplifier is coupled between the demodulation device and the analog-to-digital converter and is suitable for converting the current signal into a voltage signal and outputting the voltage signal.