KR101292667B1 - Digital RF converter and digital RF modulator and transmitter including the same - Google Patents

Abstract

The present invention relates to a digital RF converter and a digital RF modulator and transmitter including the same to improve the dynamic range and the signal-to-noise ratio of the transmitter. The digital RF converter has a first sampling rate and is applied to the lowest n bits of the input signal. A Delta-sigma modulated bits (DSMB) subblock that generates a corresponding current magnitude; A Least-Significant Bit (LSB) sub-block for generating a current magnitude corresponding to a middle k bit of the input signal at a second sampling rate lower than the first sampling rate; And a most-significant bit (MSB) subblock that generates a current magnitude corresponding to the most significant m bit of the input signal at the second sampling rate.

Description

Digital RF converter and digital RF modulator and transmitter including the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital RF converter, and to a digital RF converter and a digital RF modulator and transmitter including the same to improve a dynamic range and a signal-to-noise ratio of a transmitter.

The present invention is derived from a study performed as part of the IT source technology development project of the Ministry of Knowledge Economy [Task Management Number: 2008-F-008-02, Title: Development of Advanced Digital RF technology for the next generation wireless convergence terminal].

In wireless communication applications, the design has continually directed simple and inexpensive wireless structures that have increased the level of integration of mobile terminals.

1 shows a typical analog circuit based transmitter. Referring to FIG. 1, the transmitter circuit includes a digital-to-analog converter (D / A) 11, 12, a low pass filter (LPF) 13, 14; ), Mixers 15 and 16, bandpass filters (BPFs) 17 and linear power amplifiers (PAs) 18.

The digital-to-analog converters 11 and 12 convert the baseband in-phase signal I and quadrature signal Q, which are discrete signals having a plurality of data bits, into analog signals, respectively, and the low pass filter 13, 14) filters unwanted waves occurring at a position separated by a multiple of the sampling frequency of the baseband due to the characteristics of the digital signal.

The mixers 15 and 16 up-convert the lowpass signal based on the carrier signals (cosω _LO t and sinω _LO t) generated by the frequency synthesizer, and the bandpass filter 17 is completely processed by the lowpass filter. It filters out unwanted waves and cosine signals caused by unresolved clutter or nonlinearity in the mixer.

The linear power amplifier 18 amplifies this filtered signal to generate an RF signal and is transmitted to the antenna via a duplexer or switch.

However, the transmitter shown in FIG. 1 has the following problem. First, non-ideal operation of analog circuits, such as mixers in the transmitter circuit, non-linearity of lowpass filters, carrier feedthrough, and so on, can degrade the performance of the entire transmitter system. Second, analog baseband circuits limit the bandwidth of the signal to be transmitted. Third, when the circuit including all the above functions is configured, the area occupied on the semiconductor substrate becomes large.

Shakeshaft (US 2005/01115330 A1) introduces the concept of a current steering D / A converter to solve the above problem, such as a plurality of Gilbert-Cell mixers as shown in Figs. (Gilbert-cell mixer) form a digital RF-to-RF converter that combines the functions of a digital-to-analog converter and the frequency up-converting mixer by connecting each cell in parallel and controlling each with a digital signal. And was applied to the transmitter circuit system as shown in FIG.

In the present invention, the dynamic range of the transmitter is limited by the number of cells connected in parallel, that is, the data bit size of the digital control signal connected to each cell. The maximum voltage of the output signal in the operating region is limited by the magnitude of the supply voltage of the circuit, the minimum voltage is limited by the size of the least-significant bit (LSB) cell in Figure 2, This size is determined by the size of the transistor with the smallest gate width produced in a semiconductor process.

As the operation area is limited by the number of cells in this manner, the maximum signal-to-noise ratio (SNR) that the transmitter circuit can obtain is limited by the limitations of the semiconductor process and the supply voltage of the circuit.

In addition, the unit-weighted design of each cell tends to improve the overall linearity of the transmission system. However, the number of cells increases, which complicates the design in the semiconductor circuit layout and the electrical coupling in the circuit. This has the disadvantage of increasing signal interference and increasing design area. For example, if the data bit size of the digital control signal is 8 bits, the total number of cells required is 256.

In the above-mentioned invention, as shown in FIG. 2, two kinds of cells having different sizes are used to form a LSB subblock by connecting large cells having a small operating current in parallel and parallel cells having a large operating current. By concatenating the most-significant bit (MSB) subblock, the total number of cells required for the transmitter circuit is reduced. Assuming that the current of a cell having a large operating current is 8 times larger than the current of a cell having a small operating current, the number of LSB cells constituting the LSB subblock is 7 and that of the MSB cell constituting the MSB subblock. The number of 31 can be achieved to achieve a signal-to-noise ratio comparable to that of a transmitter circuit consisting of only 255 LSB cells.

However, even in the case of the structure of the present invention, if the performance of the transmitter circuit consisting of only 1023 LSB cells is required, the number of 7 LSB cells and 127 MSB cells is required.

Accordingly, in the present invention, the baseband signal is controlled as a digital signal by using existing digital RF conversion cells, and the sigma-delta modulated signal is applied by adding a plurality of cells having the smallest current magnitude, thereby providing the smallest To provide a digital RF converter and a digital RF modulator and transmitter including the same to allow a current having a smaller magnitude than that generated by a single cell to improve the dynamic range and signal-to-noise ratio of the entire transmitter. do.

As a means for solving the above problem, according to an embodiment of the present invention, a DSMB (Delta-sigma modulated bits) subblock that generates a current magnitude corresponding to the lowest n bits of an input signal at a first sampling rate. A least-significant bit (LSB) subblock that generates a current magnitude corresponding to an intermediate k bit of the input signal at a second sampling rate lower than one sampling rate, and the highest m of the input signal at the second sampling rate. It is possible to provide a digital RF converter including a Most-Significant Bit (MSB) subblock that generates a current magnitude corresponding to a bit.

The least significant n bits are sigma-delta modulated, oversampled and noise shaped signals, wherein the first sampling rate is the same as the sigma-delta modulation rate.

The DSMB sub-block provides 2 ⁿ -1 cells having a minimum current magnitude and the lowest n bits to the 2 ⁿ -1 cells at the first sampling rate, so that the amount of current flowing through the 2 ⁿ -1 cells May include 2 ⁿ −1 latches to make them variable.

The LSB subblock may include k cells having a current magnitude varying in a binary weighting manner and k latches providing the intermediate k bits to the k cells at the second sampling rate.

The MSB sub-block is the most significant m bits in accordance with the said least significant m bits into 2 ^m -1 of cells and the second sampling rate, which changes the signal value of the output signal to a current size of the unit 2, ^k I 2 ^m - It may include 2 ^m -1 latch provided to one cell.

As a means for solving the above problems, according to another embodiment of the present invention, a pulse shaping digital filter for receiving a baseband digital signal and pulse shaping only the digital signal included in the communication bandwidth, the least significant n bits of the pulse-shaped signal A sigma-delta modulator for performing sigma-delta modulation decoding the sigma-delta modulated n bits, the middle k bits of the pulse shaped signal and the most significant m bits of the pulse shaped signal into a thermometer code or binary code, respectively. And a digital-analog conversion by segmenting the decoder and the decoded n bits, the decoded k bits and the decoded m bits, wherein the decoded n bits are digital-analog converted at the same sampling rate as the sigma-delta modulator. And the decoded k bits and m bits are the sigma-delta modulator complement. Digital-to-low sampling rates may provide the digital RF modulator comprises a digital-to-analog conversion to RF converter.

The digital RF converter is at the same sampling rate as the sigma-delta modulator, at a lower sampling rate than the delta-sigma modulated bits (DSMB) subblock that generates the current magnitude corresponding to the decoded n bits. Least-Significant Bit (LSB) subblocks that generate current magnitudes corresponding to the decoded k bits and MSBs that generate current magnitudes corresponding to the decoded m bits at lower sampling rates than the sigma-delta modulator. -Significant Bit) may include a subblock.

The DSMB subblock is the n-bit decoded at the same sampling rate as the sigma-delta modulator and 2 ⁿ -1 cells and the signal value of the output signal in units of current magnitude of I according to the decoded n bits. 2 ⁿ -1 latches may be provided to the 2 ⁿ -1 cells.

The LSB subblock includes k cells for changing the signal value of the output signal in a binary weighted manner according to the decoded k bits and the k cells for the decoded k bits at a lower sampling rate than the sigma-delta modulator. It may include k latches provided to.

The MSB sub-block is decoded at a lower sampling rate than the sigma-delta modulator and 2 ^m −1 cells that change the signal value of the output signal in units of current magnitude of 2 ^k I in accordance with the decoded m bits. and 2 ^m −1 latches that provide m bits to the 2 ^m −1 cells.

In addition, the digital RF modulator may, if necessary, delay compensation circuitry such that the middle k bits of the pulse shaped signal and the highest m bits of the pulse shaped signal are input to the decoder in synchronization with the sigma-delta modulated n bits. It may further include.

As a means for solving the above problems, according to another embodiment of the present invention, two digital RF modulator for modulating and outputting some bits of the in-phase signal and quadrature signal at different sampling rates The in-phase signal and quadrature A carrier signal generator for generating a carrier signal for modulation of the signal; a differential-single output converter for converting the modulated in-phase signal and the quadrature signal into a single output signal to remove the cosine signal and the unwanted wave included in the single output signal; A direct upconversion transmitter including a filter and a power amplifier for amplifying and outputting the filtered signal may be provided.

Each of the two digital RF modulators receives the in-phase signal or the quadrature signal to pulse-shape only a digital signal included in a communication bandwidth, and performs sigma-delta modulation on the lowest n bits of the pulse-shaped signal. A sigma-delta modulator for performing the decoding of the sigma-delta modulated n bits, the middle k bits of the pulse shaped signal and the highest m bits of the pulse shaped signal into a thermometer code or a binary code, respectively; segment the n bits, the decoded k bits, and the decoded m bits to digital-analog conversion, wherein the decoded n bits are digital-analog converted at the same sampling rate as the sigma-delta modulator, and the decoded k Bits and mbits have a lower sampling rate than the sigma-delta modulator And a digital RF converter to digital-to-analog conversion.

The digital RF converter is at the same sampling rate as the sigma-delta modulator, at a lower sampling rate than the delta-sigma modulated bits (DSMB) subblock that generates the current magnitude corresponding to the decoded n bits, Least-Significant Bit (LSB) subblocks that generate current magnitudes corresponding to the decoded k bits and MSBs that generate current magnitudes corresponding to the decoded m bits at lower sampling rates than the sigma-delta modulator. -Significant Bit) may include a subblock.

Accordingly, the digital RF converter and the digital RF modulator and the transmitter including the same of the present invention can effectively increase the dynamic range and the signal-to-noise ratio of the transmitter without significantly increasing the number of digital RF conversion cells.

In addition, by minimizing the proportion of analog circuits and increasing the proportion of digital circuits, the system performance can be prevented from deteriorating due to external conditions such as supply voltage, semiconductor process, and temperature, and the proportion of digital circuits increases. Minimize power consumption required for operation. In addition, the area occupied by the circuit on the semiconductor chip can be reduced.

1 is a diagram illustrating a general analog circuit based transmitter.
2 is a diagram showing the configuration of a digital RF converter according to the prior art.
3 is a diagram illustrating a detailed configuration of a cell included in a digital RF converter according to the prior art.
4 is a functional diagram of a digital RF converter according to the prior art.
5 is a diagram illustrating a configuration of a digital RF converter according to an embodiment of the present invention.
6 is a diagram functionally showing a digital RF converter according to an embodiment of the present invention.
7 illustrates a digital RF modulator including a digital RF converter according to an embodiment of the present invention.
8 illustrates a direct up-conversion transmitter including a digital RF modulator according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The term and / or includes any combination of a plurality of related items or any of a number of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the present invention, the same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

5 is a diagram illustrating a configuration of a digital RF converter according to an embodiment of the present invention.

Referring to FIG. 5, the digital RF converter 300 includes a plurality of cells 311 to 31N and a plurality of latches 321 to 32N connected in parallel, and these are referred to as Delta-sigma modulated bits (DSMB) subblocks 331. ), And is divided into a LSB (Least-Significant Bit) subblock 332 and a MSB (Most-Significant Bit) subblock 333.

If the digital signal coming from the baseband is divided into n bits, k bits, and m bits in order from the lower bits, the least significant n bits are oversampled and noise-shaped through a sigma-delta modulator (not shown), and then the DSMB subblock 331 ), And the intermediate k bits and the most significant m bits are applied to the LSB subblock 332 and the MSB subblock 333 without modification.

The DSMB subblock 331 is driven at a faster sampling frequency than the LSB subblock 332 and the MSB subblock 333. That is, the DSMB subblock 331 performs digital-to-analog conversion in synchronization with the first clock CLK1 having the same oversampled frequency as the sigma-delta modulator, but the LSB and MSB subblocks 332 and 333 A digital-to-analog conversion is performed in synchronization with the second clock CLK2 having an existing sampling frequency (ie, a sampling frequency lower than the first clock CLK1).

To this end, the DSMB sub-block 331 is synchronized to the 2 ⁿ -1 cells 311 to 312 having the minimum current magnitude (I) and the first clock (CLK1) to the lowest n bits (V _L1 to V _L2 ). a 2 ⁿ -1 cells (311-312) to provide 2 ⁿ -1 comprises the cells (311-312) 2 ⁿ -1 latches (321-322) such that a variable amount of current flowing through to, and the The LSB sub-block 332 is configured to synchronize the k bits (313 to 315) and the second clock (CLK2) with the current magnitudes changed in a binary weighting scheme, thereby k k cells (V _L3 to V _L4 ) in the middle. And k latches 323 to 325 provided to the 313 to 315 to vary the amount of current flowing through the k cells 313 to 315, wherein the MSB sub-block 333 is 2 ^k I (where, K is the number of cells included in the LSB subblock, and I is the highest m bit in synchronization with 2 ^m −1 cells 316 to 31N and the second clock CLK2 having a current magnitude of the minimum current magnitude. the ^{_{2 m -1 (V L5 ~ V}} LN) one And a cell (316 ~ 31N) 2 ^m -1 to provide the cells (316 ~ 31N) 2 ^m -1 latches (326 ~ 32N) such that the amount of current flowing through the variable.

Accordingly, the digital RF converter 300 has a current magnitude corresponding to the least n bits oversampled and noise-shaped through the DSMB subblock 331, and a current magnitude corresponding to the middle k bits through the LSB subblock 332. Then, through the MSB sub-block 333 to generate a current magnitude corresponding to the most significant m bits, respectively.

However, since the DSMB subblock 331 is driven at a faster sampling frequency than the LSB and MSB subblocks 332 and 333 as described above, the minimum current size of the cell provided in the digital RF converter 300 ( It is possible to generate smaller current magnitudes. This means that oversampling the DSMB subblock 331 causes the current magnitude generated by the DSMB subblock 331 to be averaged, and the averaged current magnitude is the minimum current magnitude I of the cell provided in the digital RF converter 300. Because it can be smaller.

As a result, the digital RF converter 300 may finely adjust and output the signal value of the output signal RFout according to the current magnitude generated through the DSMB sub-block 331.

As such, the digital RF converter 300 of the present invention further includes a DSMB subblock 331 capable of generating a current size smaller than the minimum current size I of the cell provided in the digital RF converter 300. The signal value of the output signal RFout can be adjusted more precisely, thereby improving the dynamic range and signal-to-noise ratio of the transmitter to which the digital RF converter 300 is applied.

6 is a functional diagram illustrating a digital RF converter according to an embodiment of the present invention. Referring to FIG. 6, the digital RF converter includes a DSMB subblock 331, an LSB subblock 332, and an MSB subblock. 333 is functionally classified, and the DSMB subblock 331 is driven in synchronization with the first clock CLK1 having a higher frequency than the second clock CLK2 of the other two subblocks 332 and 333. Able to know.

For reference, there is a method of increasing the number of cells constituting the MSB subblock to expand the dynamic range and signal-to-noise ratio of the transmitter.However, as the number of cells constituting the MSB subblock increases, the layout design becomes complicated. A problem arises in that the linearity of is lowered. Accordingly, in the present invention, by adding the DSMB sub-block configured and operated as described above, the dynamic range and the signal-to-noise ratio of the transmitter are effectively improved without increasing the total number of cells.

7 illustrates a digital RF modulator including a digital RF converter according to an embodiment of the present invention.

As shown in FIG. 7, the digital RF modulator includes a pulse shaping digital filter 410, a sigma-delta modulator 420, first and second delay correction circuits 430 and 440, and first and second thermometer code decoders. 450 and 470, a binary decoder 460, and a digital RF converter 300 constructed and operated as shown in FIG.

The pulse shaping digital filter 410 receives a baseband digital signal, removes unnecessary digital signals appearing at a position corresponding to a multiple of a carrier frequency, and selects and pulses only the digital signals included in the communication bandwidth.

In this case, the digital signal output from the pulse shaping digital filter 410 may be divided into n bits, k bits, and m bits in order from the lower bits, and the lowest n bits are the first delay correction circuit as the sigma-delta modulator 420. The middle k bits are transmitted to 430, and the most significant m bits are transmitted to the second delay correction circuit 440, respectively.

The sigma-delta modulator 420 modulates the least significant n bits according to the sigma-delta modulation scheme, and outputs the oversampled and noise shaped n bits. At this time, the sigma-delta modulator 420 is synchronized with the first clock CLK1 of the DSMB sub-block 331 even if the signal input thereto has a small data bit width to perform oversampling so that the output signal has improved resolution. Allow them to have

The first and second delay correction circuits 430 and 440 have the same delay component as the delay component of the sigma-delta modulator 420, thereby delaying the middle k bits and the most significant m bits. The output signal is synchronized with the output signal of 420. In other words, the middle k bits and the most significant m bits are synchronized with the least significant n bits to be passed to the next stage.

The first thermometer code decoder 450 decodes the lowest n bits transmitted through the sigma-delta modulator 420 to generate a thermometer code, and the binary decoder 460 transmits through the first delay correction circuit 430. The intermediate k bits are decoded to generate a binary code, and the second thermometer code decoder 470 generates a thermometer code by decoding the most significant m bits transmitted through the second delay correction circuit 440.

The digital RF converter 300 segments the digital signal output from the pulse shaping digital filter 310 by n + k + m through the DSMB subblock 331, the LSB subblock 332, and the MSB subblock 333. (segmentation) to convert.

Hereinafter, the operation of the digital RF modulator of FIG. 7 will be described.

First, the baseband digital signal input to the digital RF modulator 400 is converted into a pulse-shaped signal according to the communication bandwidth while passing through the pulse-shaping digital filter 410, and then divided into n-bit, k-bit, and m-bit sigma Delta modulator 420, first and second delay correction circuits 430, 440.

Then, the least significant n bits are converted into a signal having a relatively small bit through the sigma-delta modulator 420 and then input to the DSMB subblock 331 of the digital RF converter 300 through the first thermometer code decoder 450. do.

At the same time, the intermediate k-bits and the most significant m-bits are corrected by the time that the lowest n bits are delayed through the sigma-delta modulator 420 through the first and second delay correction circuits 430 and 440. The decoder 460 and the second thermometer code decoder 470 are input to the LSB subblock 332 and the MSB subblock 333 of the digital RF converter 300, respectively.

Then, the n bits, k bits, and m bits are segmented by the DSMB subblock 331, the LSB subblock 332, and the MSB subblock 333 of the digital RF converter 300, and then added after digital-to-analog conversion. The final output is in the form of one analog signal RFout.

8 illustrates a direct up-conversion transmitter including a digital RF modulator according to an embodiment of the present invention.

Referring to FIG. 8, the direct up-conversion transmitter 500 is configured and operated as shown in FIG. 7 so that some bits (ie, in-phase signal I and quadrature signal Q) input in the form of a digital signal. Two digital RF modulators 400, an in-phase signal I and a quadrature signal, which digital-to-analog convert and output the least significant n bits at a different sampling rate than the remaining bits (i.e., intermediate k and m bits). An output matching circuit for matching the impedance matching of two analog signals output from two digital RF modulators 400 to a carrier signal generator (or frequency synthesizer) 510 for generating a carrier signal for modulation of Q) 520), a differential-single output converter (or balun) 530 that converts two analog signals transmitted through the output matching circuit 520 into a single output signal, a cosine signal included in the single output signal, and unnecessary wave It includes a cancellation filter 540, and a power amplifier (PA Power Amplifier) (550) for amplifying the power of the filtered signal by the filter 540 such that.

Accordingly, the in-phase signal (I) and quadrature signal (Q) transmitted to the baseband input to the direct up-conversion transmitter 500 of FIG. 8 are analog signal differential pairs through two digital RF modulators 400. And then impedance matched through output matching circuit 520.

The impedance matched differential signal pair is converted into a single output signal through a differential-to-single output converter or a balun 530, and band-pass filtered through a filter 540 to remove the cosine signal and the unwanted wave, and then the PA 550. Power amplified).

The signal thus amplified is wirelessly transmitted through a duplexer or a switch and an antenna.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

300: digital RF converter 331: DSMB subblock
332: LSB subblock 333: MSB subblock
311 ~ 31N: Cell 321 ~ 32N: Latch

Claims (15)

A Delta-sigma modulated bits (DSMB) subblock generating a current magnitude corresponding to the lowest n bits of the input signal at a first sampling rate;
A Least-Significant Bit (LSB) sub-block for generating a current magnitude corresponding to a middle k bit of the input signal at a second sampling rate lower than the first sampling rate; And
And a most-significant bit (MSB) subblock that generates a current magnitude corresponding to the most significant m bit of the input signal at the second sampling rate.
2. The digital RF converter of claim 1 wherein the least significant n bits are sigma-delta modulated oversampling and noise shaped signals.
The method of claim 2, wherein the first sampling rate is
Digital RF converter characterized by the same sigma-delta modulation rate.
The method of claim 1, wherein the DSMB sub block is
2 ⁿ -1 cells with a minimum current magnitude; And
And 2 ⁿ -1 latches for providing the least n bits to the 2 ⁿ -1 cells at the first sampling rate to vary the amount of current flowing through the 2 ⁿ -1 cells. Digital RF Converter.
The method of claim 4, wherein the LSB subblock is
K cells having a current magnitude that varies in a binary weighting manner; And
And k latches providing the intermediate n k bits to the k cells at the second sampling rate so that the amount of current flowing through the k cells is varied.
The method of claim 4, wherein the MSB subblock is
2 ^m -1 cells having a current magnitude of 2 ^k I (where k is the number of cells included in the LSB sub-block and I is the minimum current magnitude); And
And 2 ^m −1 latches for providing the least m bits to the 2 ^m −1 cells at the second sampling rate to vary the amount of current flowing through the 2 ^m −1 cells. Digital RF Converter.
A pulse shaping digital filter receiving a baseband digital signal and pulse shaping only a digital signal included in a communication bandwidth;
A sigma-delta modulator for performing sigma-delta modulation on the lowest n bits of the pulse-shaped signal;
A decoder for decoding the sigma-delta modulated n bits, the middle k bits of the pulse shaped signal and the most significant m bits of the pulse shaped signal into a thermometer code or a binary code, respectively; And
Segment the decoded n bits, the decoded k bits, and the decoded m bits to digital-analog conversion, wherein the decoded n bits are digital-analog converted at the same sampling rate as the sigma-delta modulator, And the decoded k and m bits comprise a digital RF converter for digital-to-analog conversion at a lower sampling rate than the sigma-delta modulator.
The method of claim 7, wherein the digital RF converter
A Delta-sigma modulated bits (DSMB) subblock that generates a current magnitude corresponding to the decoded n bits at the same sampling rate as the sigma-delta modulator;
A Least-Significant Bit (LSB) subblock that generates a current magnitude corresponding to the decoded k bits at a lower sampling rate than the sigma-delta modulator; And
And a Most-Significant Bit (MSB) subblock that generates a current magnitude corresponding to the decoded m bits at a lower sampling rate than the sigma-delta modulator.
The method of claim 8, wherein the DSMB subblock is
2 ⁿ -1 cells with a minimum current magnitude; And
And 2 ⁿ -1 latches for providing the decoded n bits to the 2 ⁿ -1 cells at the same sampling rate as the sigma-delta modulator to vary the amount of current flowing through the 2 ⁿ -1 cells. Digital RF modulator, characterized in that.
The method of claim 9, wherein the LSB subblock is
K cells having a current magnitude that varies in a binary weighting manner; And
A digital RF modulator comprising k latches for providing the decoded k bits to the k cells to vary the amount of current flowing through the k cells at a lower sampling rate than the sigma-delta modulator. .
The method of claim 9, wherein the MSB subblock is
2 ^m -1 cells having a current magnitude of 2 ^k I (where k is the number of cells included in the LSB sub-block and I is the minimum current magnitude); And
At a sampling rate lower than that of the sigma-delta modulator, providing 2 ^m −1 latches for providing the decoded m bits to the 2 ^m −1 cells to vary the amount of current flowing through the 2 ^m −1 cells. Digital RF modulator comprising a.
The method of claim 7, wherein
And a delay compensation circuit for causing the middle k bits of the pulse shaped signal and the most significant m bits of the pulse shaped signal to be input to the decoder in synchronization with the sigma-delta modulated n bits. RF modulator.
Two digital RF modulators for modulating and outputting some bits of the in-phase and quadrature signals at different sampling rates;
A carrier signal generator for generating a carrier signal for modulation of the in-phase signal and the quadrature signal;
A differential-single output converter for converting the modulated in-phase and quadrature signals into a single output signal;
A filter for removing the cosine signal and the unwanted wave included in the single output signal; And
And a power amplifier for amplifying and outputting the filtered signal.
14. The apparatus of claim 13, wherein each of the two digital RF modulators is
A pulse shaping digital filter which receives the in-phase signal or the quadrature signal and pulses only the digital signals included in the communication bandwidth;
A sigma-delta modulator for performing sigma-delta modulation on the lowest n bits of the pulse-shaped signal;
A decoder for decoding the sigma-delta modulated n bits, the middle k bits of the pulse shaped signal and the most significant m bits of the pulse shaped signal into a thermometer code or a binary code, respectively; And
Segment the decoded n bits, the decoded k bits, and the decoded m bits to digital-analog conversion, wherein the decoded n bits are digital-analog converted at the same sampling rate as the sigma-delta modulator, And the decoded k-bits and m-bits comprise a digital RF converter for digital-analog conversion at a lower sampling rate than the sigma-delta modulator.
15. The digital RF converter of claim 14 wherein the digital RF converter is
A Delta-sigma modulated bits (DSMB) subblock that generates a current magnitude corresponding to the decoded n bits at the same sampling rate as the sigma-delta modulator;
A Least-Significant Bit (LSB) subblock that generates a current magnitude corresponding to the decoded k bits at a lower sampling rate than the sigma-delta modulator; And
And a Most-Significant Bit (MSB) subblock that generates a current magnitude corresponding to the decoded m bits at a lower sampling rate than the sigma-delta modulator.

Images