CN110311663A - Low-power consumption comparison circuit, successive approximation analog-digital converter and chip - Google Patents
Low-power consumption comparison circuit, successive approximation analog-digital converter and chip Download PDFInfo
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- CN110311663A CN110311663A CN201910501595.1A CN201910501595A CN110311663A CN 110311663 A CN110311663 A CN 110311663A CN 201910501595 A CN201910501595 A CN 201910501595A CN 110311663 A CN110311663 A CN 110311663A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Abstract
This application involves a kind of low-power consumption comparison circuit, successive approximation analog-digital converter and chips.Above-mentioned low-power consumption comparison circuit includes logic processing module, comparison module and trigger module, and logic processing module obtains comparison control signal according to the output signal of clock frequency signal, sampling frequency signal and trigger module；Comparison module determines the operating mode of current comparison module according to comparison control signal, operating mode includes comparison pattern and shutdown mode, when comparison module is in comparison pattern, extraneous first comparator input signal and extraneous second comparator input signal are compared, output, which is compared, completes signal；Trigger module generates output signal according to completion signal is compared, and passes through output signal and controls comparison module shutdown.The low-power consumption comparison circuit of the application resets comparison module after comparison module compares completion, reduces the dynamic power consumption of comparison procedure.
Description
Technical field
This application involves analog circuit fields, turn more particularly to low-power consumption comparison circuit, successive approximation simulation numeral
Parallel operation and chip.
Background technique
SAR ADC(successive approximation register Analog to Digital
Converter, successive approximation analog-digital converter) in conversion process each time, it can be by traversing all quantizations
Be worth and be translated into the analogue value, by input signal with its one by one compared with, finally obtain the digital signal to be exported.
Currently, SAR ADC is more obvious with the advantage of the reduction power consumption of size, be mainly used in intermediate resolution, in
Speed, low-power consumption and the small aspect of area.Wherein SAR ADC mainly includes the power consumption of DAC, comparator, digital logic portion, low
In power dissipation design, comparator is frequently with the comparator of dynamic latch, only dynamic power consumption, without quiescent dissipation, but when low
When speed is using and using synchronous logic, it may appear that comparator has compared completion but it is still in working condition, wastes function
Consumption.
Summary of the invention
Based on this, it is necessary to aiming at the problem that synchronous sequence bring power consumption on the SAR ADC of above-mentioned low speed, provide one kind
The low-power consumption comparison circuit, successive approximation analog-digital converter and chip of power consumption on the SAR ADC of low speed can be reduced.
A kind of low-power consumption comparison circuit, comprising: logic processing module, comparison module and trigger module；
The logic processing module is believed according to the output of clock frequency signal, sampling frequency signal and the trigger module
Number, obtain comparison control signal；
The comparison module determines the operating mode of current comparison module, the Working mould according to the comparison control signal
Formula includes comparison pattern and shutdown mode, when the comparison module is in comparison pattern, compares input letter to the external world first
Number and extraneous second comparator input signal be compared, output, which is compared, completes signal；
The trigger module generates output signal according to the signal of relatively completing, and the output signal compares for controlling
Module shutdown.
The logic processing module is specifically used for receiving clock frequency signal, sample frequency in one of the embodiments,
The output signal of signal and the trigger module, and to the clock frequency signal, the sampling frequency signal and described
The output signal of trigger module carries out or logic processing, obtains comparison control signal, and to the clock frequency signal and
The sampling frequency signal carries out or logical process, obtains reset trigger signal.
In one of the embodiments, it is characterized in that, the logic processing module include first or logic unit and
Or logic unit, described first or the first input end of logic unit receive clock frequency signal, described first or logic list
Second input terminal of member receives sampling frequency signal, described first or logic unit output end and the or logic unit
Second input terminal of the connection of the reset terminal of first input end and the trigger module, the or logic unit receives the touching
The output signal of module is sent out, the output end of the or logic unit exports the comparison control signal.
The signal of relatively completing includes first comparing and completing signal and second completeer in one of the embodiments,
At signal, the trigger module obtains described first and compares output signal and described second compare output signal, and to described
First comparison signal and second comparison signal progress or logical process, obtain edging trigger clock signal, according to described
Edging trigger clock signal and the reset trigger signal generate output signal.
The trigger module includes second or logic unit and edge triggered flip flop in one of the embodiments, described
Second or the first input end of logic unit receive described first and compare output signal, described second or logic unit it is second defeated
Enter end and receive described second to compare output signal, described second or logic unit output end and the edge triggered flip flop clock
The reset terminal of triggering end connection, the edge triggered flip flop receives the reset trigger signal, the output end of the edge triggered flip flop
Export the output signal.
The edge triggered flip flop includes d type flip flop in one of the embodiments,.
The edge triggered flip flop includes the first JK flip-flop and third phase inverter in one of the embodiments, described
First JK flip-flop obtains extraneous input voltage by the third phase inverter.
The comparison module includes dynamic latch comparator in one of the embodiments,.
A kind of successive approximation analog-digital converter, including digital analog converter, control circuit, S/R latch and
Low-power consumption comparison circuit described in above-mentioned any one, the first input end of comparison module receives in the low-power consumption comparison circuit
Second input terminal of simulation input, the comparison module of the low-power consumption comparison circuit is connect with the digital analog converter, institute
It states the first input end of the S/R latch output end compared with the first of the comparison module to connect, the second of the S/R latch is defeated
Enter end output end compared with the second of the comparison module to connect, the first output end of the S/R latch and the control circuit
Connection, the second output terminal of the S/R latch are connect with the control circuit.
A kind of chip, the chip include and above-mentioned any one described in low-power consumption comparison circuit.
Above-mentioned low-power consumption comparison circuit, successive approximation analog-digital converter and chip, when starting sampling, logic
For processing module according to clock frequency signal and sampling frequency signal, the comparison for generating control comparison module operating mode controls letter
Number, comparison module determines to be currently entering comparison pattern or shutdown mode according to the comparison control signal, compares when entering
When mode, extraneous first comparator input signal and extraneous second comparator input signal are compared, completion letter is compared in output
Number to trigger module, trigger module completes signal and generates output signal according to comparing.Logic processing module is according to trigger mode at this time
The output signal of block updates the control signal of comparison module, and comparison module is switched to shutdown mode, stops comparing.The application's
Low-power consumption comparison circuit switches to shutdown mode after comparison module compares completion, by comparison module, reduces comparison procedure
Dynamic power consumption.
Detailed description of the invention
Fig. 1 is the structure chart of low-power consumption comparison circuit in one embodiment；
Fig. 2 is the structure chart of low-power consumption comparison circuit in another embodiment；
Fig. 3 is the timing diagram of signal in low-power consumption comparison circuit in one embodiment；
Fig. 4 is the structure chart of successive approximation analog-digital converter in one embodiment.
Specific embodiment
The application in order to facilitate understanding is described more fully the application below with reference to relevant drawings.In attached drawing
Give the preferred embodiment of the application.But the application can realize in many different forms, however it is not limited to herein
Described embodiment.On the contrary, purpose of providing these embodiments is keeps the understanding to disclosure of this application more saturating
It is thorough comprehensive.
As shown in Figure 1, this application provides a kind of low-power consumption comparison circuits 200, comprising: logic processing module 210 compares
Module 230 and trigger module 250；
The timing diagram of various signals in the application is specifically referred to Fig. 2, and clock frequency signal is specifically referred to Fig. 2
In Clk signal, sampling frequency signal is referred to the Clks signal in Fig. 2, and the output signal of trigger module 250 is referred to
Valid signal in Fig. 2, after Clk+Clks signal is clock frequency signal and sampling frequency signal progress or logical process
Signal, Clkc signal are that the output signal of clock frequency signal, sampling frequency signal and trigger module 250 carries out or logic
Treated signal.
The logic processing module 210 is according to the output of clock frequency signal, sampling frequency signal and trigger module 250
Signal obtains comparison control signal；
Logic processing module 210 receives clock frequency signal, sampling frequency signal and touching in one of the embodiments,
The latch data signal of module 250 is sent out, and to the latch number of clock frequency signal, sampling frequency signal and trigger module 250
It is believed that number progress or logic processing, trigger signal is compared in acquisition, in addition, also to clock frequency signal and sampling frequency signal
Progress or logical process obtain reset trigger signal；
The logic processing module includes first or logic unit and or logic unit, and described first or logic list
Member first input end receive clock frequency signal, described first or logic unit the second input terminal receive sample frequency letter
Number, described first or the output end of logic unit connect with the first input end of the or logic unit, the or logic
Second input terminal of unit receives the output signal of the trigger module, and the output end of the or logic unit exports the ratio
Compared with control signal.
Wherein first or logic unit can be realized by nor gate and phase inverter, or logic unit can by or
NOT gate is realized, as shown in Fig. 2, logic processing module 210 specifically includes the first nor gate 212, the in one of the embodiments,
One phase inverter 214 and the second nor gate 216, the first input end of the first nor gate 212 receive clock frequency signal, first or
Second input terminal of NOT gate 212 receives sampling frequency signal, and the output end of the first nor gate 212 is defeated with the first phase inverter 214
Enter end connection, the output end of the first phase inverter 214 and the second first input end of nor gate 216 and answering for trigger module 250
The connection of position end, the second input terminal of the second nor gate 216 receive the output signal of trigger module 250, the second nor gate 216 it is defeated
Trigger signal is compared in outlet output.Logic processing module 210 can specifically regard the nor gate inputted as one three as, double by two
The nor gate of input and a phase inverter are constituted, and the first nor gate 212 receives clock frequency signal and sampling frequency signal, right
It carries out or logic processing, then by phase inverter acquisition clock frequency signal and sampling frequency signal or logical process
Signal afterwards, i.e. Clk+Clks signal.It is then carried out by the latch data signal of Clk+Clks signal and trigger module 250 or non-
Logical process, the consequential signal Clkc of output are clock frequency signal Clk, sampling frequency signal Clks and output signal
The or logic processing result data of Valid passes through the first nor gate 212, the first phase inverter 214 and the second nor gate 216
Constituting logic processing module 210 can be performed corresponding or logic processing operation, can also pass through the first nor gate 212 and the
For one phase inverter 214 is constituted or door come reset trigger signal needed for obtaining trigger module 250, required device is less, convenient fast
It is prompt.
The comparison module 230 determines the operating mode of current comparison module 230 according to the comparison control signal, described
Operating mode includes comparison pattern and shutdown mode, when the comparison module is in comparison pattern, is compared the external world first
Input signal and extraneous second comparator input signal are compared, and output, which is compared, completes signal, when comparison module is off
When mode, stop comparing.
The trigger module 250 generates output signal according to completion signal is compared, and output signal is for controlling comparison module
Shutdown.
Compare in one of the embodiments, complete signal include first compare output signal and second compare output letter
Number, trigger module 250 obtains first and compares output signal and second compare output signal, and to the first comparison signal and the
Two comparison signals carry out or logical process, obtain edging trigger clock signal, then according to edging trigger clock signal and again
Position trigger signal generates latch output signal.
As shown in figure 3, trigger module 250 includes in one of the embodiments, or door and edge triggered flip flop or door can
To be realized by nor gate and phase inverter, i.e., trigger module 250 include third nor gate 252, the second phase inverter 254 and
Edge triggered flip flop 256, the first input end of third nor gate 252 receive first and compare output signal, and the of third nor gate 252
Two input terminals receive second and compare output signal, and the output end of third nor gate 252 passes through the second phase inverter 254 and edging trigger
The clock triggering end of device 256 connects, and the reset terminal of edge triggered flip flop 256 receives reset trigger signal, edge triggered flip flop 256 it is defeated
Outlet output signal output is to the second nor gate 216.
Wherein third nor gate 252 and the second phase inverter 254 are for comparing output to comparison module 230 exports first
Signal and second compare output signal carry out or logical process, and will processing complete signal as edge triggered flip flop 256
Clock trigger signal.Comparison module 230 relatively after the completion of, it is that the third nor gate 252 and the second phase inverter 254 are constituted or
Door can export a corresponding rising edge signal to edge triggered flip flop 256, so that it is high to export the output end of edge triggered flip flop 256
Level signal Valid.Edge triggered flip flop 256 includes d type flip flop in one of the embodiments,.In another embodiment, side
It include the first JK flip-flop and third phase inverter along trigger 256, wherein the first input end acquisition of the first JK flip-flop is outer
Second input terminal of boundary's input voltage, the first JK flip-flop obtains extraneous input voltage by third phase inverter.In addition to d type flip flop
Except, the function of edge triggered flip flop can also be realized by the first JK flip-flop and third phase inverter.
The low-power consumption comparison circuit of the application when working at the beginning, that is, when starting sampling phase, at input logic
The Clk signal and Clks signal for managing module 210 are high level, and the latch data signal Valid of trigger module 250 is initially
Low level, the Clkc signal that logic processing module 210 exports after carrying out or handling are low level.Clkc signal is that mould is compared in output
The trigger signal of block 230, when Clkc signal is low level, characterization resets.Comparison module 230 executes after receiving the Clkc signal
Operation is resetted, sampling terminates.And when Clk signal and Clks signal are low level, the Valid signal of trigger module 250 by
It is not carried out in the reset of comparison module 230 and is more still maintained low level, Clkc signal is Clk signal, Clks signal, Valid
The high level that signal generates after or logic processing, when Clkc signal is low level, characterization is waken up, and compares mould at this time
Block 230 starts to be compared operation, is compared to extraneous first comparator input signal and extraneous second comparator input signal,
Comparison result signal is exported, i.e., first compares output signal and second compare output signal, wherein first compares output letter
Output signal is two one high and one low different output signals number compared with second.Trigger module 250 is more defeated in reception first
Signal after output signal, first to the first comparison signal and the progress of the second comparison signal or logical process, produces compared with second out
Raw high level signal, while a rising edge signal is generated, letter is triggered using the rising edge signal as the clock of trigger module 250
Number, the output end of triggering trigger module 250 exports the latch data signal Valid of corresponding high level, then make Clk,
The Clks and Valid or signal Clkc of non-post is low level, and comparison module 230 is reset again, due to edging trigger
Device 256 be rising edge triggering, therefore even if the clock trigger signal of edge triggered flip flop 256 comparison module 230 reset after be reduced to it is low
Level, output end Valid output remains as high level and remains unchanged, but signal after Clk and Clks or logical process is
The reset terminal of high level, trigger module 250 will be triggered, and the output end Valid of trigger module 250 will be set to 0, later
The step of repeat the above process.
Above-mentioned low-power consumption comparison circuit, when starting sampling, extraneous sampling frequency signal is the first level, for example, high electricity
Usually, this is after the processing of logic processing module 210, and the trigger signal of input comparison module 230 is low level, and comparison module is multiple
Position, sampling terminates, when extraneous sampling frequency signal and extraneous clock frequency signal are second electrical level, i.e. low level, input
The trigger signal of comparison module 230 is high level, and comparison module 230 starts to extraneous first comparator input signal and extraneous the
Two comparator input signals are compared, relatively after, the first of comparison module 230 compares output signal and second more defeated
Out after signal input trigger module 250, after process or logical process, acquisition edging trigger clock signal, trigger module 250
According to the latch data signal of edging trigger clock signal output high level to logic processing module 210, input is then made to compare mould
The signal of block 230 is low level, and comparison module 230 is reset again, since trigger module 250 is edging trigger, therefore even if triggering
The edging trigger clock signal of module 250 is reduced to low level, the latch data of trigger module 250 after the reset of comparison module 230
The output result of signal still remains unchanged, and when extraneous sampling frequency signal and extraneous clock frequency signal or signal be high electricity
It is flat, i.e., when reset trigger signal is high level, the reset operation of triggering trigger module 250, the latch data letter of trigger module 250
It number will be set.The low-power consumption comparison circuit of the application resets comparison module 230 after comparison module 230 compares completion,
Reduce the dynamic power consumption of comparison procedure.
The low-power consumption comparison circuit 200 of the application includes: logic processing module 210, compares in one of the embodiments,
Module 230 and trigger module 250；Logic processing module 210 includes the first nor gate 212, the first phase inverter 214 and second
The first input end of nor gate 216, the first nor gate 212 receives clock frequency signal, the second input terminal of the first nor gate 212
Sampling frequency signal is received, the output end of the first nor gate 212 is connect with the input terminal of the first phase inverter 214, the first phase inverter
214 output end is connect with the reset terminal of the first input end of the second nor gate 216 and trigger module 250, the second nor gate
216 the second input terminal receives the output signal of trigger module 250, and the output end and comparison module 230 of the second nor gate 216 connect
It connects.Wherein, comparison module 230 is dynamic latch comparator.Trigger module 250 includes third nor gate 252, the second phase inverter
254 and d type flip flop, the first input end of third nor gate 252 receives first and compares output signal, third nor gate 252
Second input terminal receives second and compares output signal, and the output end of third nor gate passes through the second phase inverter 2540 and d type flip flop
The connection of clock triggering end, the reset terminal of d type flip flop receives reset trigger signal, the output end output signal output of d type flip flop
To the second nor gate 216.Logic processing module 210 is for receiving clock frequency signal, sampling frequency signal and trigger module
250 output signal, and to the output signal of clock frequency signal, sampling frequency signal and trigger module 250 carry out or it is non-
Trigger signal is compared in logical process, acquisition, and to clock frequency signal and sampling frequency signal progress or logical process, obtains
Reset trigger signal；Trigger signal is compared in the reception of comparison module 230, determines current comparison module according to the comparison control signal
Operating mode, the operating mode includes comparison pattern and shutdown mode, when the comparison module is in comparison pattern,
Extraneous first comparator input signal and extraneous second comparator input signal are compared, output, which is compared, completes signal；Triggering
Module 250 obtains first and compares output signal and second compare output signal, and compares the first comparison signal and second
Signal carries out or logical process, edging trigger clock signal is obtained, according to edging trigger clock signal and reset trigger signal
Generate output signal.
As shown in figure 4, present invention also provides a kind of successive approximation analog-digital converter, including digital-to-analogue conversion
Low-power consumption comparison circuit 200 in device 400, control circuit 600 and any one above-mentioned embodiment, low-power consumption comparison circuit
The first input end of comparison module 230 receives extraneous simulation input in 200, the comparison module 230 of low-power consumption comparison circuit 200
Second input terminal is connect with digital analog converter 400, the first output end of comparison module 230 in low-power consumption comparison circuit 200
And second output terminal is connect with control circuit 600 respectively.When low-power consumption comparison circuit simulates number for realizing successive approximation
When word converter, clock frequency is the clock frequency of successive approximation analog-digital converter, and sample frequency is successive approximation
The sample frequency of analog-digital converter.
It in one of the embodiments, further include S/R latch, first input end and the comparison module 230 of S/R latch
First compares output end connection, and the second input terminal of S/R latch output end compared with the second of comparison module connects, and SR is latched
First output end of device connects to the control circuit, and the second output terminal of S/R latch connects to the control circuit.Pass through S/R latch
Can allow comparison module 230 export first compare output signal and second compare output signal holding it is more longlasting, prevent
Comparison module 230 brings the level of mistake to enter subsequent control circuit after resetting.Further include in one of the embodiments,
Second JK flip-flop and the 4th phase inverter, the first input end of the second JK flip-flop export compared with the first of comparison module 230
End connection, the output end connection with the second of comparison module 230 compared with of the second input terminal of the second JK flip-flop, the of JK flip-flop
One output end connects to the control circuit, and the second output terminal of JK flip-flop is connected to the control circuit by phase inverter.In addition to SR is posted
Except storage, the 4th phase inverter can be added to replace SR register by JK flip-flop, reach allow comparison module 230 to export the
One compare output signal and second compare output signal holding more longlasting effect.
It in one of the embodiments, further include RC filter, the comparison module 230 in low-power consumption comparison circuit passes through RC
Filter receives extraneous simulation input.It can be filtered by simulation input of the RC filter to external world's input, improve input
The quality of successive approximation analog-digital converter signal.
Present invention also provides a kind of chip, chip includes the low-power consumption comparison circuit in any one above-mentioned embodiment.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Above embodiments only express the several embodiments of the application, and the description thereof is more specific and detailed, but can not
Therefore it is interpreted as the limitation to claim.It should be pointed out that for those of ordinary skill in the art,
Under the premise of not departing from the application design, multiple modification and improvement can also be made, these belong to the protection scope of the application.
Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of low-power consumption comparison circuit characterized by comprising logic processing module, comparison module and trigger module；
The logic processing module according to the output signal of clock frequency signal, sampling frequency signal and the trigger module,
Obtain comparison control signal；
The comparison module determines the operating mode of current comparison module, the operating mode packet according to the comparison control signal
Include comparison pattern and shutdown mode, when the comparison module is in comparison pattern, to extraneous first comparator input signal with
And extraneous second comparator input signal is compared, output, which is compared, completes signal；
The trigger module generates output signal according to the signal of relatively completing, and the output signal is for controlling comparison module
Shutdown.
2. low-power consumption comparison circuit according to claim 1, which is characterized in that the logic processing module is specifically used for connecing
The output signal of clock frequency signal, sampling frequency signal and the trigger module is received, and to the clock frequency signal, institute
The output signal for stating sampling frequency signal and the trigger module carries out or logic processing, obtains comparison control signal, and
To the clock frequency signal and the sampling frequency signal carries out or logical process, obtains reset trigger signal.
3. low-power consumption comparison circuit low-power consumption comparison circuit according to claim 2, which is characterized in that the logical process
Module includes first or logic unit and or logic unit, and described first or the first input end of logic unit when receiving
Clock frequency signal, described first or the second input terminal of logic unit receive sampling frequency signal, described first or logic unit
Output end connect with the reset terminal of the first input end of the or logic unit and the trigger module, it is described or non-patrol
Second input terminal of volume unit receives the output signal of the trigger module, described in the output end output of the or logic unit
Comparison control signal.
4. low-power consumption comparison circuit according to claim 2, which is characterized in that the signal of relatively completing includes the first ratio
Compared with completing signal and second compare and complete signal, the trigger module obtains described first and compares output signal and described the
Two compare output signal, and to first comparison signal and second comparison signal progress or logical process, obtain side
Along triggering clock signal, output signal is generated according to the edging trigger clock signal and the reset trigger signal.
5. low-power consumption comparison circuit according to claim 4, which is characterized in that the trigger module includes second or logic
Unit and edge triggered flip flop, described second or the first input end of logic unit receive and described first compare output signal, institute
State second or the second input terminal of logic unit receive described second and compare output signal, described second or logic unit output
End is connect with the clock triggering end of the edge triggered flip flop, and the reset terminal of the edge triggered flip flop receives the reset trigger letter
Number, the output end of the edge triggered flip flop exports the output signal.
6. low-power consumption comparison circuit according to claim 5, which is characterized in that the edge triggered flip flop includes d type flip flop.
7. low-power consumption comparison circuit according to claim 5, which is characterized in that the edge triggered flip flop is touched including the first JK
Device and third phase inverter are sent out, first JK flip-flop obtains extraneous input voltage by the third phase inverter.
8. low-power consumption comparison circuit according to claim 1, which is characterized in that the comparison module includes dynamic latch ratio
Compared with device.
9. a kind of successive approximation analog-digital converter, which is characterized in that including digital analog converter, control circuit and
Low-power consumption comparison circuit described in any one of claim 1-8, the first of comparison module in the low-power consumption comparison circuit
Input terminal receives simulation input, the second input terminal of the comparison module of the low-power consumption comparison circuit and the digital-to-analogue conversion
Device connection, in the low-power consumption comparison circuit the first output end of comparison module and second output terminal respectively with the control
Circuit connection.
10. a kind of chip, which is characterized in that the chip includes that low-power consumption described in any one of claim 1-8 is compared
Circuit.
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| CN110311663B (en) | 2023-01-20 |
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