CN104993830B - Binary channels time-division pilotaxitic texture is asynchronous gradually to compare type analog-to-digital converter - Google Patents
Binary channels time-division pilotaxitic texture is asynchronous gradually to compare type analog-to-digital converter Download PDFInfo
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Abstract
A kind of binary channels time-division pilotaxitic texture of present invention offer is asynchronous gradually to compare type analog-to-digital converter, and comprising the time-division asynchronous gradually comparing unit of intertexture, the time-division asynchronous gradually comparing unit of intertexture includes sampling switch S10And S20, capacitor array C1With capacitor array E1, start unit F1、F2、…、Fn, switching switch SW1、SW2、SW3、SW4、…、SW2n‑1、SW2n, comparator A1、A2、…、An, register B1、B2、…、Bn, register D1、D2、…、Dn, reset cell G1And G2.The present invention is as a result of the asynchronous gradually comparative structure of binary channels, binary channels multiplexing is carried out to one group of comparator, and use asynchronous gradually manner of comparison, reduce the delay of Digital Logic, therefore type analog-to-digital converter is gradually compared compared to traditional, with faster speed, thus analog-digital converter provided by the invention has the characteristic with low-power consumption at high speed, especially suitable for the occasion higher to analog-digital converter speed and power consumption performance requirement.
Description
Technical field
The invention belongs to modulus or digital analog converter field, and in particular to a kind of binary channels time-division pilotaxitic texture it is asynchronous by
Secondary relatively type analog-to-digital converter.
Background technology
In recent years, with the development at mobile interchange end, on the one hand need to reduce device power consumption to extend treating for mobile device
Machine usage time, the communication of another aspect system requires that component has higher speed again, with reference to the latest tendency of scientific research industrial circle
From the point of view of, the analog-digital converter with high-speed low-power-consumption performance increasingly becomes the focal point of commercial Application.
Conventional successive compares type analog-to-digital converter structure as shown in figure 1, gradually comparing type analog-to-digital converter is always considered as
It is low speed, high-precision analog-digital converter structure.It, which completes a data conversion, needs multiple clock cycle, the mould of General N position
Number converter needs just complete to quantify more than N number of timing cycles, while gradually compares in type analog-to-digital converter analog module
Analog-digital converter without using operational amplifier, therefore the type has the characteristics of low-power consumption；In addition gradually compare pattern number to turn
Parallel operation can handle the analog input signal in the range of supply voltage, so can effectively improve input signal amplitude, realize
Higher signal to noise ratio.These advantages are all gradually to compare the reason for type analog-to-digital converter turns into the focus of attention.
The operation principle that conventional successive in Fig. 1 compares type analog-to-digital converter is：First, input signal is sampled holding electricity
Road samples, and in order to realize that accurate sampling is established, this sampling process can include 2-3 internal clock cycles；Then, this
Sampled signal is used to compared with the output of capacitor array, and in fact capacitor array contains the function of sampling and will compared
Compared with the function that digital value is converted to analog voltage.Quantify conversion after input signal is stored in capacitor array to begin to, deposit
Highest order MSB in device is initially positioned at 1 remaining code value and is placed in 0, and voltage caused by capacitor array output is reference voltage
Intermediate level position.The relativeness of input signal and reference voltage intermediate level is judged by comparator, decision is to maintain MSB
High level is still reset.It is clear that when sampled signal is higher than base reference level, highest order MSB remains 1, less than centre
Highest order MSB is reset as 0 during datum.Identical judges to carry out successively in MSB-1 positions to LSB bit, is finally completed whole
The determination of coding.
Gradually comparing, the traditional capacitance array employed in type analog-to-digital converter is as shown in Figure 2.Present inventor
Research finds that the capacitor array shown in Fig. 2 is due to using single reference voltage, therefore the capacitance of its capacitor array is by LSB
The electric capacity corresponding to electric capacity to MSB positions corresponding to position is incremental according to 2 multiple step by step, therefore when digit gradually increases
Wait, being limited to capacitance size corresponding to LSB bit can cause electric capacity corresponding to MSB positions very big, and this can limit whole analog-digital converter
Speed, thus from the point of view of Integrated comparative, the speed of establishing of capacitor array turns into influence gradually to compare type analog-to-digital converter performance and referred to
One of target principal element.
The content of the invention
For conventional successive compare the capacitance of capacitor array in type analog-to-digital converter from the electric capacity corresponding to LSB bit to
Electric capacity corresponding to MSB positions is incremental according to 2 multiple step by step, when digit gradually increases, is limited to corresponding to LSB bit
Capacitance size can cause electric capacity corresponding to MSB positions very big, and this can limit the technical problem of the speed of whole analog-digital converter, this hair
A kind of bright binary channels time-division pilotaxitic texture of offer is asynchronous gradually to compare type analog-to-digital converter.
To achieve these goals, the present invention adopts the following technical scheme that：
A kind of binary channels time-division pilotaxitic texture is asynchronous gradually to compare type analog-to-digital converter, interweaves comprising the time-division and asynchronous gradually compares
Compared with unit, the time-division asynchronous gradually comparing unit of intertexture includes sampling switch S10And S20, capacitor array C1With capacitor array E1, open
Moving cell F1、F2、…、Fn, switching switch SW1、SW2、SW3、SW4、…、SW2n-1、SW2n, comparator A1、A2、…、An, register
B1、B2、…、Bn, register D1、D2、…、Dn, reset cell G1And G2；Wherein,
External input signal VinPass through sampling switch S10With capacitor array C1TOP1~TOPnInterface end is connected, and passes through
Sampling switch S20With capacitor array E1TOP1~TOPnInterface end is connected, while sampling switch S10Receive external clock CK1Control
Sampled, sampling switch S20Receive external clock CK2Control is sampled；
The start unit F1With external clock CK1And CK2It is connected and produces trigger signal, switches switch SW for controlling1With
Trigger comparator A1, comparator A1Output result pass through switch switch SW2Switching respectively with register B1And D1Input phase
Even, register B1Output end and capacitor array C1BOT1Interface end is connected, register D1Output end and capacitor array E1's
BOT1Interface end is connected；Meanwhile
The comparator A1Output result and start unit F2It is connected and produces trigger signal, switches switch SW for controlling3
With trigger comparator A2, comparator A2Output result pass through switch switch SW4Switching respectively with register B2And D2Input
It is connected, register B2Output end and capacitor array C1BOT2Interface end is connected, register D2Output end and capacitor array E1
BOT2Interface end is connected；By that analogy,
Afterbody comparator AnOutput result pass through switch switch SW2nSwitching respectively with register BnAnd DnInput
End is connected, register BnOutput end and capacitor array C1BOTnInterface end is connected, register DnOutput end and capacitor array
E1BOTnInterface end is connected, and afterbody comparator AnOutput result and reset cell G1And G2It is connected；
The reset cell G1Caused reset signal is used to reset register B1、B2、…、Bn, the reset cell G2Production
Raw reset signal is used to reset register D1、D2、…、Dn；
Capacitor array C1With capacitor array E1For the intermediate level of output reference voltage, it is suitable for judging that outside input is believed
Number VinThe relative height relation with the intermediate level of the reference voltage.
Binary channels time-division pilotaxitic texture provided by the invention is asynchronous gradually to compare type analog-to-digital converter, interweaves comprising the time-division different
Gradually comparing unit is walked, it uses binary channels capacitor array to carry out time-division intertexture quantization, therefore conversion speed is compared with single channel speed
One times is improved, simultaneously because asynchronous gradually manner of comparison is employed, therefore the numeral after comparing each time in gradually comparing
Output result can drive the electric capacity in corresponding capacitor array immediately, so compared to traditional structure, reduce each by
The Digital Logic delay of secondary comparison, while the comparator of every switches between the two channels, therefore binary channels is shared same
One group of comparator, the speed of analog-digital converter of the present invention is further increased on the premise of ensureing that power consumption is constant.Therefore, this hair
It is bright that there is higher speed ability relative to traditional structure, it can effectively meet the requirement of high-speed AD converter, it is especially suitable
For low-power consumption analog-digital converter.
Further, the capacitor array C1For more reference voltage high speed capacitor arrays, including control selections switch S11、
S12、…、S1n, reference voltage Ref1、Ref2、…、RefnAnd electric capacity C11、C12、…、C1n, the electric capacity C11Top plate with
Switch S11One end be connected, switch S11The other end pass through switch control terminal H1Control is in common-mode voltage Vcm and reference voltage
Ref1Between mutually switch, the electric capacity C12Top plate with switch S12One end be connected, switch S12The other end by opening
Close control terminal H2Control is in common-mode voltage Vcm and reference voltage Ref2Between mutually switch, by that analogy, the electric capacity C1nTop
Pole plate and switch S1nOne end be connected, switch S1nThe other end pass through switch control terminal HnControl is in common-mode voltage Vcm and reference
Voltage RefnBetween mutually switch, the sole plates of all electric capacity is connected to TOP ends, and capacitor array C1TOP1~TOPnConnect
Mouth end is connected with TOP ends respectively, BOT1~BOTnInterface end connects one to one to switch control terminal H1~Hn, and the electric capacity
C11、C12、…、C1nWith identical capacitance, the reference voltage RefnWith Refn-1Size is identical, reference voltage Refn-2~
Ref1In fixed multiple proportion.
Further, the reference voltage Refn-2~Ref1Increase in 2 exponential depth.
Further, the capacitor array E1For more reference voltage high speed capacitor arrays, including control selections switch S21、
S22、…、S2n, reference voltage Ref1、Ref2、…、RefnAnd electric capacity C21、C22、…、C2n, the electric capacity C21Top plate with
Switch S21One end be connected, switch S21The other end pass through switch control terminal H1Control is in common-mode voltage Vcm and reference voltage
Ref1Between mutually switch, the electric capacity C22Top plate with switch S22One end be connected, switch S22The other end by opening
Close control terminal H2Control is in common-mode voltage Vcm and reference voltage Ref2Between mutually switch, by that analogy, the electric capacity C2nTop
Pole plate and switch S2nOne end be connected, switch S2nThe other end pass through switch control terminal HnControl is in common-mode voltage Vcm and reference
Voltage RefnBetween mutually switch, the sole plates of all electric capacity is connected to TOP ends, and capacitor array E1TOP1~TOPnConnect
Mouth end is connected with TOP ends respectively, BOT1~BOTnInterface end connects one to one to switch control terminal H1~Hn, and the electric capacity
C21、C22、…、C2nWith identical capacitance, the reference voltage RefnWith Refn-1Size is identical, reference voltage Refn-2~
Ref1In fixed multiple proportion.
Further, the reference voltage Refn-2~Ref1Increase in 2 exponential depth.
Brief description of the drawings
Fig. 1 is the structural representation that conventional successive compares type analog-to-digital converter.
Fig. 2 is the structural representation of traditional capacitance array.
Fig. 3, which is that binary channels time-division pilotaxitic texture provided by the invention is asynchronous, gradually compares type analog-to-digital converter structural representation
Figure.
Fig. 4 is more reference voltage high speed capacitor array C provided by the invention1Structural representation.
Fig. 5 is more reference voltage high speed capacitor array E provided by the invention1Structural representation.
Fig. 6 is the asynchronous sequential signal for gradually comparing type analog-to-digital converter of binary channels time-division pilotaxitic texture provided by the invention
Figure.
Embodiment
In order that the technical means, the inventive features, the objects and the advantages of the present invention are easy to understand, tie below
Conjunction is specifically illustrating, and the present invention is expanded on further.
It refer to shown in Fig. 3, a kind of binary channels time-division pilotaxitic texture of present invention offer is asynchronous gradually to compare type analog-to-digital conversion
Device, comprising the time-division asynchronous gradually comparing unit of intertexture, the time-division asynchronous gradually comparing unit of intertexture includes sampling switch S10With
S20, capacitor array C1With capacitor array E1, start unit F1、F2、…、Fn, switching switch SW1、SW2、SW3、SW4、…、SW2n-1、
SW2n, comparator A1、A2、…、An, register B1、B2、…、Bn, register D1、D2、…、Dn, reset cell G1And G2；Wherein,
External input signal VinPass through sampling switch S10With capacitor array C1TOP1~TOPnInterface end is connected, and passes through
Sampling switch S20With capacitor array E1TOP1~TOPnInterface end is connected, while sampling switch S10Receive external clock CK1Control
Sampled, sampling switch S20Receive external clock CK2Control is sampled；
The start unit F1With external clock CK1And CK2It is connected and produces trigger signal, switches switch SW for controlling1With
Trigger comparator A1, comparator A1Output result pass through switch switch SW2Switching respectively with register B1And D1Input phase
Even, register B1Output end and capacitor array C1BOT1Interface end is connected, register D1Output end and capacitor array E1's
BOT1Interface end is connected；Meanwhile
The comparator A1Output result and start unit F2It is connected and produces trigger signal, switches switch SW for controlling3
With trigger comparator A2, comparator A2Output result pass through switch switch SW4Switching respectively with register B2And D2Input
It is connected, register B2Output end and capacitor array C1BOT2Interface end is connected, register D2Output end and capacitor array E1
BOT2Interface end is connected；By that analogy,
Afterbody comparator AnOutput result pass through switch switch SW2nSwitching respectively with register BnAnd DnInput
End is connected, register BnOutput end and capacitor array C1BOTnInterface end is connected, register DnOutput end and capacitor array
E1BOTnInterface end is connected, and afterbody comparator AnOutput result and reset cell G1And G2It is connected；
The reset cell G1Caused reset signal is used to reset register B1、B2、…、Bn, the reset cell G2Production
Raw reset signal is used to reset register D1、D2、…、Dn；
Capacitor array C1With capacitor array E1For the intermediate level of output reference voltage, it is suitable for judging that outside input is believed
Number VinThe relative height relation with the intermediate level of the reference voltage.
Binary channels time-division pilotaxitic texture provided by the invention is asynchronous gradually to compare type analog-to-digital converter, interweaves comprising the time-division different
Gradually comparing unit is walked, it uses binary channels capacitor array to carry out time-division intertexture quantization, therefore conversion speed is compared with single channel speed
One times is improved, simultaneously because asynchronous gradually manner of comparison is employed, therefore the numeral after comparing each time in gradually comparing
Output result can drive the electric capacity in corresponding capacitor array immediately, so compared to traditional structure, reduce each by
The Digital Logic delay of secondary comparison, while the comparator of every switches between the two channels, therefore binary channels is shared same
One group of comparator, the speed of analog-digital converter of the present invention is further increased on the premise of ensureing that power consumption is constant.Therefore, this hair
It is bright that there is higher speed ability relative to traditional structure, it can effectively meet the requirement of high-speed AD converter, it is especially suitable
For low-power consumption analog-digital converter.
The Asynchronous comparison mode that the present invention can just be triggered as a result of every grade of comparator after the completion of prime comparison, because
Relative to traditional structure, the comparative result of the comparator in the structure just directly drives accordingly not through digital logic module for this
Switched capacitor array, eliminate the time in digital logic module, therefore improve the bulk velocity of system.The present invention's
Work schedule principle schematic is as shown in fig. 6, the sampling clock of first passage and second channel is respectively CK1And CK2, triggering is respectively
Level comparator A1、A2、…、AnSequential refer to MSB~LSB in Fig. 6, specifically：Clock CK1Put single by starting after height
First F1The sampling for opening first analog-digital converter passage keeps function, start unit F1For clock edge detection unit, work as clock
CK1Or CK2Trailing edge then produces comparator A when arriving1Trigger signal, therefore the then trigger comparator A after the completion of sampling1Just
Often work, comparator A1Its comparative result is stored in register B after the completion of normal work1In, while pass through start unit F2Triggering
Comparator A2Carry out normal work, start unit F2Detection comparator A1Output level, as comparator A1Produce output signal level
When then start unit F2Corresponding trigger signal is produced, in comparator A2After producing comparative result, corresponding numeric results, which are stored in, posts
Storage B2In, and trigger rear class comparator simultaneously and be operated, similarly, the sequential of what rear comparator so triggers backward successively
Next stage comparator, as last comparator AnAfter producing decision level, its numeric results is stored in register BnIn, at this
After the completion of secondary comparison, reset cell G1And G2Then by detecting afterbody comparator AnOutput level, when detecting comparator
AnCorresponding trigger signal can be then produced during output, therefore passes through reset cell G1Corresponding reset signal is produced, resets register
B1、B2、…、Bn, be stored in this process because comparator compares output in corresponding register, comparator speed quickly,
After completing relatively, fiducial value stores in a register, therefore comparator is in idle state；Meanwhile when second passage
Clock CK2When putting high, second passage is sampled, start unit F1Trigger switch SW1And SW2Switch over so that comparator A1
To carry out quantization comparison to the sampled value of second passage, the decision value obtained after the completion of comparing is stored in register D1In, by
In comparator A2Idle state, comparator A are in more afterwards in completion first passage1Start unit is then triggered after completing relatively
F2Switching switch SW3And SW4And trigger rear class comparator A2It is compared, comparator A2Comparative result be stored in register D2
In, while trigger rear class comparator successively and complete subsequently relatively, to post accordingly because the result of comparators at different levels is respectively stored in
In storage, therefore comparator is completed accordingly to switch in each interchannel by switching more afterwards, when in each passage
After the completion of everybody comparison numeral output, corresponding digital court verdict is then stored in register, when last comparator
AnAfter producing decision level, its numeric results is stored in register DnIn, after the completion of all comparisons, pass through reset cell G2Production
Raw corresponding reset signal, resets register D1、D2、…、Dn.Similarly, with the clock CK of two passages1And CK2Height is put respectively,
Then two passages will be changed successively.
As specific embodiment, it refer to shown in Fig. 4, the capacitor array C1For more reference voltage high speed capacitor arrays,
S1 is switched including control selections1、S12、…、S1n, reference voltage Ref1、Ref2、…、RefnAnd electric capacity C11、C12、…、C1n,
The electric capacity C11Top plate with switch S11One end be connected, switch S11The other end pass through switch control terminal H1Control is altogether
Mode voltage Vcm and reference voltage Ref1Between mutually switch, the electric capacity C12Top plate with switch S12One end be connected, open
Close S12The other end pass through switch control terminal H2Control is in common-mode voltage Vcm and reference voltage Ref2Between mutually switch, with this
Analogize, the electric capacity C1nTop plate with switch S1nOne end be connected, switch S1nThe other end pass through switch control terminal HnControl
System is in common-mode voltage Vcm and reference voltage RefnBetween mutually switch, the sole plate of all electric capacity is connected to TOP ends, and electric
Hold array C1TOP1~TOPnInterface end is connected with TOP ends respectively, BOT1~BOTnInterface end connects one to one to switch and controlled
End H processed1~Hn, and the electric capacity C11、C12、…、C1nWith identical capacitance, the reference voltage RefnWith Refn-1Size
It is identical, reference voltage Refn-2~Ref1In fixed multiple proportion.In the present embodiment, using more reference voltages as the mould
The reference voltage of number converter capacitor array, due to using multiple reference voltages, the capacitance of the capacitor array can be substantially reduced
Size, that accelerates the capacitor array module in analog-digital converter establishes speed, so as to further lift speed.
As the presently preferred embodiments, the reference voltage Refn-2~Ref1Increase in 2 exponential depth, certainly, the skill of this area
Art personnel can also set reference voltage Ref on the basis of aforementioned preferred embodiments using other multiplesn-2~Ref1
Between relation.
As specific embodiment, it refer to shown in Fig. 5, the capacitor array E1Structure and internal annexation with it is foregoing
Capacitor array C1It is identical, specifically, the capacitor array E1Switched for more reference voltage high speed capacitor arrays, including control selections
S21、S22、…、S2n, reference voltage Ref1、Ref2、…、RefnAnd electric capacity C21、C22、…、C2n, the electric capacity C21Climax
Plate and switch S21One end be connected, switch S21The other end pass through switch control terminal H1Control is in common-mode voltage Vcm and with reference to electricity
Press Ref1Between mutually switch, the electric capacity C22Top plate with switch S22One end be connected, switch S22The other end pass through
Switch control terminal H2Control is in common-mode voltage Vcm and reference voltage Ref2Between mutually switch, by that analogy, the electric capacity C2n's
Top plate and switch S2nOne end be connected, switch S2nThe other end pass through switch control terminal HnControl is in common-mode voltage Vcm and ginseng
Examine voltage RefnBetween mutually switch, the sole plates of all electric capacity is connected to TOP ends, and capacitor array E1TOP1~TOPn
Interface end is connected with TOP ends respectively, BOT1~BOTnInterface end connects one to one to switch control terminal H1~Hn, and the electricity
Hold C21、C22、…、C2nWith identical capacitance, the reference voltage RefnWith Refn-1Size is identical, reference voltage Refn-2
~Ref1In fixed multiple proportion.In the present embodiment, using more reference voltages as the analog-digital converter capacitor array
Reference voltage, due to using multiple reference voltages, the capacitance size of the capacitor array can be substantially reduced, accelerates analog-digital converter
In capacitor array module establish speed, so as to further lift speed.
As the presently preferred embodiments, the reference voltage Refn-2~Ref1Increase in 2 exponential depth, certainly, the skill of this area
Art personnel can also set reference voltage Ref on the basis of aforementioned preferred embodiments using other multiplesn-2~Ref1
Between relation.
More reference voltage high speed capacitor arrays shown in Fig. 4 and Fig. 5 are refer to, are taken due to whole switched capacitor array
It is electric charge redistribution mode, comparison procedure is exactly that caused electric charge is carried out on electric capacity by the sampled charge of signal and reference voltage
Compare, the mode that traditional structure produces electric charge is to produce electric charge on corresponding different size of electric capacity by single reference voltage, is had
Body structure chart is as shown in Figure 2；And the present invention is due to introducing more reference voltages, thus each capacitance size can be kept the same and
Corresponding different comparison reference voltage is produced, is met respectively between Fig. 4 and more reference voltages employed in figure 5 with following formula (1)
Relation：
Ref1=2Ref2=...=2n-2Refn-1=2n-2Refn (1)
Take with such as the reference voltage level of formula (1) relation, it is ensured that the value of used capacitor array is all consistent
, therefore the capacitance in Fig. 4 and Fig. 5 has such as the relation of formula (2)：
C1=C2=C3...=Cn (2)
Due to taking the electric capacity of same capacitance in the capacitor array, on the one hand taking can with equivalent capacitor array
Carry out good matching, another aspect what is more important, for Cn=C capacitor array, its electricity overall in sampling
Hold shown in total amount such as formula (3)：
C+C+C+ ... C=nC (3)
And for the capacitor array of traditional single reference voltage as shown in Figure 2, its electric capacity total amount size such as formula (4) institute
Show：
C+C+2C+……+2N-1C=2NC (4)
Contrast (3) and formula (4) are visible, the total electricity of the capacitor arrays of more reference voltages compared to traditional sampling capacitor array
Appearance substantially reduces, therefore can reach higher speed in sampling, while the reduction of electric capacity can also be substantially reduced whole electricity
Hold the power consumption of electric charge discharge and recharge when array samples.
In summary, type structure is gradually compared because analog-digital converter provided by the invention employs binary channels, therefore
Only there was only comparator consumption power consumption in whole analog-digital converter, and comparator completes multiplexing in two interchannels, in height
On the premise of speed, there are the low power capabilities that do not have of other class type analog-to-digital converter, thus with it is significant at high speed and
The characteristics of low-power consumption.
Meanwhile the present invention combines the binary channels time-division asynchronous gradually comparing unit of intertexture and more reference voltage high speed capacitor arrays
The characteristics of, it is multiplexed using being changed between binary channels, reduces the elapsed time of digital logic module and the size of sampling capacitance, carry
The analog-digital converter of a high speed and low-power consumption is supplied.
Embodiments of the present invention are these are only, are not intended to limit the scope of the invention, it is every to utilize the present invention
The equivalent structure that specification and accompanying drawing content are made, other related technical areas are directly or indirectly used in, similarly at this
Within the scope of patent protection of invention.
Claims (5)
1. binary channels time-division pilotaxitic texture is asynchronous gradually to compare type analog-to-digital converter, it is characterised in that interweaves comprising the time-division asynchronous
Gradually comparing unit, the time-division asynchronous gradually comparing unit of intertexture include sampling switch S10And S20, capacitor array C1With electric capacity battle array
Arrange E1, start unit F1、F2、…、Fn, switching switch SW1、SW2、SW3、SW4、…、SW2n-1、SW2n, comparator A1、A2、…、An,
Register B1、B2、…、Bn, register D1、D2、…、Dn, reset cell G1And G2；Wherein,
External input signal VinPass through sampling switch S10With capacitor array C1TOP1~TOPnInterface end is connected, and passes through sampling
Switch S20With capacitor array E1TOP1~TOPnInterface end is connected, while sampling switch S10Receive external clock CK1Control is carried out
Sampling, sampling switch S20Receive external clock CK2Control is sampled；
The start unit F1With external clock CK1And CK2It is connected and produces trigger signal, switches switch SW for controlling1With triggering
Comparator A1, comparator A1Output result pass through switch switch SW2Switching respectively with register B1And D1Input be connected, post
Storage B1Output end and capacitor array C1BOT1Interface end is connected, register D1Output end and capacitor array E1BOT1Connect
Mouth end is connected；Meanwhile
The comparator A1Output result and start unit F2It is connected and produces trigger signal, switches switch SW for controlling3With touching
Send out comparator A2, comparator A2Output result pass through switch switch SW4Switching respectively with register B2And D2Input be connected,
Register B2Output end and capacitor array C1BOT2Interface end is connected, register D2Output end and capacitor array E1BOT2
Interface end is connected；By that analogy,
Afterbody comparator AnOutput result pass through switch switch SW2nSwitching respectively with register BnAnd DnInput phase
Even, register BnOutput end and capacitor array C1BOTnInterface end is connected, register DnOutput end and capacitor array E1's
BOTnInterface end is connected, and afterbody comparator AnOutput result and reset cell G1And G2It is connected；
The reset cell G1Caused reset signal is used to reset register B1、B2、…、Bn, the reset cell G2It is caused
Reset signal is used to reset register D1、D2、…、Dn；
Capacitor array C1With capacitor array E1For the intermediate level of output reference voltage, it is suitable for judging external input signal Vin
The relative height relation with the intermediate level of the reference voltage.
2. binary channels time-division pilotaxitic texture according to claim 1 is asynchronous gradually to compare type analog-to-digital converter, its feature exists
In the capacitor array C1For more reference voltage high speed capacitor arrays, including control selections switch S11、S12、…、S1n, reference
Voltage Ref1、Ref2、…、RefnAnd electric capacity C11、C12、…、C1n, the electric capacity C11Top plate with switch S11One end phase
Even, S1 is switched1The other end pass through switch control terminal H1Control is in common-mode voltage Vcm and reference voltage Ref1Between mutually switch,
The electric capacity C12Top plate with switch S12One end be connected, switch S12The other end pass through switch control terminal H2Control is altogether
Mode voltage Vcm and reference voltage Ref2Between mutually switch, by that analogy, the electric capacity C1nTop plate with switch S1nOne
End is connected, and switchs S1nThe other end pass through switch control terminal HnControl is in common-mode voltage Vcm and reference voltage RefnBetween mutually
Switching, the sole plates of all electric capacity are connected to TOP ends, and capacitor array C1TOP1~TOPnInterface end respectively with TOP ends phase
Even, BOT1~BOTnInterface end connects one to one to switch control terminal H1~Hn, and the electric capacity C11、C12、…、C1nHave
Identical capacitance, the reference voltage RefnWith Refn-1Size is identical, reference voltage Refn-2~Ref1Closed in fixed multiple
System.
3. binary channels time-division pilotaxitic texture according to claim 2 is asynchronous gradually to compare type analog-to-digital converter, its feature exists
In the reference voltage Refn-2~Ref1Increase in 2 exponential depth.
4. binary channels time-division pilotaxitic texture according to claim 1 is asynchronous gradually to compare type analog-to-digital converter, its feature exists
In the capacitor array E1For more reference voltage high speed capacitor arrays, including control selections switch S21、S22、…、S2n, reference
Voltage Ref1、Ref2、…、RefnAnd electric capacity C21、C22、…、C2n, the electric capacity C21Top plate with switch S21One end phase
Even, S2 is switched1The other end pass through switch control terminal H1Control is in common-mode voltage Vcm and reference voltage Ref1Between mutually switch,
The electric capacity C22Top plate with switch S22One end be connected, switch S22The other end pass through switch control terminal H2Control is altogether
Mode voltage Vcm and reference voltage Ref2Between mutually switch, by that analogy, the electric capacity C2nTop plate with switch S2nOne
End is connected, and switchs S2nThe other end pass through switch control terminal HnControl is in common-mode voltage Vcm and reference voltage RefnBetween mutually
Switching, the sole plates of all electric capacity are connected to TOP ends, and capacitor array E1TOP1~TOPnInterface end respectively with TOP ends phase
Even, BOT1~BOTnInterface end connects one to one to switch control terminal H1~Hn, and the electric capacity C21、C22、…、C2nHave
Identical capacitance, the reference voltage RefnWith Refn-1Size is identical, reference voltage Refn-2~Ref1Closed in fixed multiple
System.
5. binary channels time-division pilotaxitic texture according to claim 4 is asynchronous gradually to compare type analog-to-digital converter, its feature exists
In the reference voltage Refn-2~Ref1Increase in 2 exponential depth.
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