CN117749187A - Analog-to-digital converter, processor and electronic equipment - Google Patents
Analog-to-digital converter, processor and electronic equipment Download PDFInfo
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Abstract
The invention discloses an analog-to-digital converter, a processor and electronic equipment, wherein the analog-to-digital converter comprises: the capacitor array is used for sampling an input analog signal and changing the voltage of the upper polar plate under the condition of capacitance switching; the first-order integration unit comprises a first integration module and a second integration module, and the first integration module and the second integration module alternately collect and integrate residual voltage of the capacitor array to generate first-order integration voltage; the second-order integration unit comprises a third integration module and a fourth integration module, and the third integration module and the fourth integration module alternately integrate the first-order integration voltage to generate a second-order integration voltage; the comparison unit is respectively connected with the capacitor array, the first-order integration unit and the second-order integration unit, and is used for comparing according to the upper polar plate voltage, the first-order integration voltage and the second-order integration voltage to output a digital signal; and the logic unit is connected with the comparison unit and processes the digital signal to obtain a switching control signal and a clock signal.
Description
Technical Field
The present disclosure relates to analog-to-digital converters, and particularly to an analog-to-digital converter, a processor, and an electronic device.
Background
Analog-to-digital converters are widely used in the fields of aerospace, radar, communication, measurement and control, measurement, medical treatment and the like. In various ADCs (Analog to Digital Converter, analog-digital converters), the analog circuit scale of the SAR ADC (Successive approximation analog-digital converter) is far smaller than that of the digital circuit, and the SAR ADC (Successive approximation analog-digital converter) can show advantages in advanced processes of low voltage, low power consumption and high speed.
In an ideal case, the output of the SAR ADC is equal to the input signal, but in practical application, the performance of the SAR ADC is affected by various non-ideal factors, such as Noise, offset voltage, quantization error, etc., the accuracy of the SAR ADC is reduced, and the NS (Noise Shaping) SAR ADC can effectively reduce the comparator Noise and quantization Noise, and improve the performance of the ADC. NS SAR ADCs are classified into active and passive, but the power consumption of the active NS SAR ADC is large, resulting in increased power consumption of the SAR ADC, and the signal attenuation of the passive NS SAR ADC is strong, resulting in poor accuracy of the SAR ADC.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present invention is to provide an analog-to-digital converter, in which a first-order integration is alternately performed by a first integration module and a second integration module, and a second-order integration is alternately performed by a third integration module and a fourth integration module, so that signal loss in the integration process is reduced, and the accuracy of an SAR ADC is improved.
A second object of the invention is to propose a processor.
A third object of the present invention is to propose an electronic device.
To achieve the above object, an embodiment according to a first aspect of the present invention provides an analog-to-digital converter, including: the capacitor array is suitable for sampling input analog signals and changing the voltage of the upper polar plate under the condition of capacitance switching; the first-order integration unit comprises a first integration module and a second integration module, the first integration module and the second integration module alternately collect and integrate residual voltage of the capacitor array to generate first-order integrated voltage, and the residual voltage is generated under the condition that the capacitor array completes capacitor switching; the second-order integration unit comprises a third integration module and a fourth integration module, and the third integration module and the fourth integration module alternately integrate the first-order integration voltage to generate a second-order integration voltage; the comparison unit is respectively connected with the capacitor array, the first-order integration unit and the second-order integration unit, and is used for comparing the upper polar plate voltage, the first-order integration voltage and the second-order integration voltage to output a digital signal; the logic unit is connected with the comparison unit, processes the digital signals to obtain switching control signals and clock signals, wherein the clock signals are applied to the comparison unit, and the switching control signals are used for controlling the capacitor array to conduct capacitance switching.
An analog-to-digital converter according to an embodiment of the present invention includes: the capacitor array is suitable for sampling an input analog signal, the upper pole plate voltage is changed under the condition of capacitive switching, residual voltage is reserved on the capacitor array after the capacitor array is switched, the first-order integration unit comprises a first integration module and a second integration module, the first integration module and the second integration module alternately collect and integrate the residual voltage of the capacitor array to generate a first-order integration voltage, one integration module in the first integration module and the second integration module collects and integrates the first-order integration voltage, the other integration module in the first integration module and the second integration module stores the first-order integration voltage, the second-order integration unit comprises a third integration module and a fourth integration module, the third integration module and the fourth integration module alternately integrate the first-order integration voltage to generate a second-order integration voltage, the other integration module in the third integration module and the fourth integration module alternately stores the second-order integration voltage, and the comparison unit collects and integrates the second-order integration voltage according to the upper pole plate voltage and the first-order integration module, the SAR signal is output, and the SAR signal is integrated, the SAR signal is shaped, and the SAR signal transmission accuracy is improved.
According to one embodiment of the present invention, the first-order integration unit further includes: the first compensation module is arranged between the first integration module and the second integration module, compensates the integration voltage generated by one integration module of the first integration module and the second integration module to generate first-order integration voltage, and provides the first-order integration voltage to the other integration module of the first integration module and the second integration module so that the other integration module of the first integration module and the second integration module stores the first-order integration voltage.
According to one embodiment of the invention, the second order integration unit further comprises: the system comprises a first compensation module, a second compensation module, a storage capacitor and a third compensation module, wherein the input end of the first compensation module is connected with the upper polar plate of the capacitor array, the first compensation module is used for generating a first-order integrated voltage by compensating the integrated voltage generated by one of the first integration module and the second integration module, one end of the storage capacitor is respectively connected with the output end of the first compensation module, the first-order integrated voltage is stored by the storage capacitor, the first-order integrated voltage is provided for the first integration module or the second integration module, the first compensation module is arranged between the first integration module and the second integration module, the first compensation module is used for compensating the integrated voltage generated by one of the first integration module and the second integration module, the second-order integrated voltage is provided for the other one of the first integration module and the second integration module, and the second-order integrated voltage is stored by the other one of the first integration module and the second integration module.
According to one embodiment of the invention, the analog-to-digital converter further comprises: the switching unit is respectively connected with the first-order integration unit and the second-order integration unit, and the switching unit switches the first integration module and the second integration module and alternately works with the third integration module and the fourth integration module.
According to one embodiment of the present invention, a switching unit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, and a seventeenth switch, wherein the first switch is disposed between an upper plate of the capacitor array and an end of the first integrating module, the second switch is disposed between an end of the first integrating module and an input terminal of the first compensating module, the third switch is disposed between an end of the first integrating module and an output terminal of the first compensating module, the fourth switch is disposed between an end of the first integrating module and a first input terminal of the comparing unit, the fifth switch is disposed between an upper plate of the capacitor array and an end of the second integrating module, the sixth switch is disposed between an end of the second integrating module and an input terminal of the first compensating module, the eighth switch is disposed between an end of the second integrating module and an output terminal of the first compensating module, the eighth switch is disposed between an end of the second integrating module and an input terminal of the comparing unit, the eighth switch is disposed between an end of the capacitor array and an input terminal of the thirteenth module, the fifteenth switch is arranged between the input end of the third compensation module and one end of the fourth integration module, the sixteenth switch is arranged between one end of the fourth integration module and the output end of the third compensation module, the seventeenth switch is arranged between the fourth integration module and the third input end of the comparison unit, the other end of the first integration module is grounded, the other end of the second integration module is grounded, the other end of the third integration module is grounded, and the other end of the fourth integration module is grounded.
According to one embodiment of the invention, in case the capacitive array completes capacitive switching, the first switch is closed so that the first integration module collects and integrates the residual voltage, after the first integration module completes integration, the second switch and the seventh switch are closed so that the second compensation module generates and provides the first order integration voltage to the second integration module, after the second integration module completes storing the first order integration voltage, the eighth switch is closed so that the second integration module provides the first order integration to the first input of the comparison unit.
According to one embodiment of the invention, in case the capacitive array completes capacitive switching, the fifth switch is closed so that the second integration module collects and integrates the residual voltage, after the second integration module completes integration, the third switch and the sixth switch are closed so that the second compensation module generates the first order integration voltage and provides the first order integration voltage to the first integration module, after the first integration module completes storing the first order integration voltage, the fourth switch is closed so that the first integration module provides the first order integration to the first input of the comparison unit.
According to one embodiment of the invention, after the integration is completed by the first or second integration module, the ninth switch is closed so that the second compensation module generates a first order integrated voltage.
According to one embodiment of the invention, after the second compensation module generates the first order integrated voltage, the tenth switch is closed so that the third integration module integrates the first order integrated voltage, after the third integration module has completed integration, the eleventh switch and the sixteenth switch are closed so that the third compensation module generates the second order integrated voltage and supplies the second order integrated voltage to the fourth integration module, after the fourth integration module has completed storing the second order integrated voltage, the seventeenth switch is closed so that the fourth integration module supplies the second order integration to the third input of the comparison unit.
According to one embodiment of the invention, after the second compensation module generates the first order integrated voltage, the fourteenth switch is closed so that the fourth integration module integrates the first order integrated voltage, after the fourth integration module completes the integration, the twelfth switch and the fifteenth switch are closed so that the third compensation module generates the second order integrated voltage and supplies the second order integrated voltage to the third integration module, after the third integration module completes storing the second order integrated voltage, the thirteenth switch is closed so that the third integration module supplies the second order integration to the third input terminal of the comparison unit.
According to an embodiment of the present invention, the second switch, the fourth switch, and the tenth switch are simultaneously switched, the third switch, the sixth switch, and the fourteenth switch are simultaneously switched, the fourth switch and the thirteenth switch are simultaneously switched, the eighth switch and the seventeenth switch are simultaneously switched, the eleventh switch and the sixteenth switch are simultaneously switched, and the twelfth switch and the fifteenth switch are simultaneously switched.
According to one embodiment of the present invention, the capacitance of the storage capacitor is the capacitance of the capacitor array.
According to one embodiment of the present invention, the first compensation module, the second compensation module and the third compensation module respectively include: the circuit comprises a first operational amplifier, a first resistor and a second resistor, wherein one end of the first resistor is a signal input end, the other end of the first resistor is connected with the negative input end of the first operational amplifier and is provided with a first node, the positive input end of the first operational amplifier is grounded, one end of the second resistor is connected with the first node, and the other end of the second resistor is respectively connected with the output end of the first operational amplifier and is a signal output end.
According to one embodiment of the present invention, the capacitor array has two capacitor arrays, which are respectively a first capacitor array and a second capacitor array, the first-order integration unit has two capacitor arrays, which are respectively a first-order integration unit and a second first-order integration unit, the second-order integration unit has two capacitor arrays, which are respectively a first second-order integration unit and a second-order integration unit, the first-order integration unit is connected with a first positive input terminal of the comparison unit, the first second-order integration unit is connected with a third positive input terminal of the comparison unit, the second first-order integration unit is connected with a first negative input terminal of the comparison unit, the upper plate of the second capacitor array is connected with a second negative input terminal of the comparison unit, and the second-order integration unit is connected with a third negative input terminal of the comparison unit, and further includes: the positive input end of the first compensation unit is respectively connected with the first integration module and the second integration module in the first-order integration unit, the positive output end of the first compensation unit is respectively connected with the first integration module and the second integration module in the first-order integration unit, the negative input end of the first compensation unit is respectively connected with the first integration module and the second integration module in the second first-order integration unit, the negative output end of the first compensation unit is respectively connected with the first integration module and the second integration module in the second first-order integration unit, the positive input end of the second compensation unit is respectively connected with the upper polar plate of the first capacitor array, the positive output end of the second compensation unit is respectively connected with the third integration module and the fourth integration module in the first second-order integration unit, the negative output end of the second compensation unit is respectively connected with the first integration module and the second integration module in the second first-order integration unit, the positive input end of the third compensation unit is respectively connected with the positive output end of the third integration module in the third-order integration unit and the second-order integration module in the second-order integration unit, and the negative output end of the third compensation unit is respectively connected with the second integration module in the third-order integration unit.
According to an embodiment of the present invention, the first compensation unit, the second compensation unit, and the third compensation unit respectively include: the circuit comprises a first operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein one end of the first resistor is a positive signal input end, the other end of the first resistor is connected with the positive input end of the first operational amplifier and is provided with a first node, the negative input end of the first operational amplifier is grounded, one end of the second resistor is connected with the first node, the other end of the second resistor is respectively connected with the positive output end of the first operational amplifier and is a positive signal output end, one end of the third resistor is a negative signal input end, the other end of the third resistor is connected with the negative input end of the first operational amplifier and is provided with a second node, one end of the fourth resistor is connected with the second node, and the other end of the fourth resistor is respectively connected with the negative output end of the first operational amplifier and is a negative signal output end.
According to one embodiment of the present invention, the first integration module, the second integration module, the third integration module, and the fourth integration module are capacitors, respectively.
According to one embodiment of the present invention, the capacitance value of the first integration module, the capacitance value of the second integration module, the capacitance value of the third integration module and the capacitance value of the fourth integration module are respectively capacitance values of the capacitor array.
To achieve the above object, an embodiment according to a second aspect of the present invention provides a processor including an analog-to-digital converter according to any one of the foregoing embodiments.
According to the processor provided by the embodiment of the invention, by adopting the analog-to-digital converter, the first-order integration is alternately performed by the first integration module and the second integration module, and the second-order integration is alternately performed by the third integration module and the fourth integration module, so that the signal loss in the integration process is reduced, and the accuracy of the SAR ADC is improved.
To achieve the above object, an embodiment according to a third aspect of the present invention provides an electronic device including the analog-to-digital converter of any one of the foregoing embodiments or the foregoing processor.
According to the electronic equipment provided by the embodiment of the invention, by adopting the analog-to-digital converter or the processor, the first-order integration is alternately performed through the first integration module and the second integration module, and the second-order integration is alternately performed through the third integration module and the fourth integration module, so that the signal loss in the integration process is reduced, and the accuracy of the SAR ADC is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a circuit diagram of an analog-to-digital converter according to one embodiment of the invention;
fig. 2 is a circuit diagram of an analog-to-digital converter according to another embodiment of the invention;
fig. 3 is a circuit diagram of a switching unit according to one embodiment of the present invention;
FIG. 4 is a timing diagram of a switch in a switching unit according to one embodiment of the invention;
FIG. 5 is a circuit diagram of a first compensation module, a second compensation module, and a third compensation module according to one embodiment of the invention;
FIG. 6 is a circuit diagram of a differential input analog-to-digital converter according to one embodiment of the invention;
FIG. 7 is a circuit diagram of a comparison unit of differential inputs according to one embodiment of the invention;
FIG. 8 is a circuit diagram of a first compensation unit, a second compensation unit, and a third compensation unit according to one embodiment of the invention;
FIG. 9 is a system diagram of a processor according to one embodiment of the invention;
FIG. 10 is a system diagram of an electronic device according to one embodiment of the invention;
fig. 11 is a system diagram of an electronic device according to another embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
An analog-to-digital converter, a processor, and an electronic device according to an embodiment of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a circuit diagram of an analog-to-digital converter according to one embodiment of the invention. As shown in fig. 1, the analog-to-digital converter includes: a capacitor array 10, a first order integration unit 20, a second order integration unit 30, a comparison unit 40 and a logic unit 50.
The capacitor array 10 is adapted to sample an input analog signal Vin, and the upper plate voltage is changed when the capacitors are switched; the first-order integration unit 20 includes a first integration module 21 and a second integration module 22, where the first integration module 21 and the second integration module 22 alternately collect and integrate a residual voltage Vres of the capacitor array 10 to generate a first-order integration voltage Vint1, where the residual voltage Vres is generated when the capacitor array 10 completes the capacitor switching; the second-order integration unit 30 includes a third integration module 31 and a fourth integration module 32, where the third integration module 31 and the fourth integration module 32 alternately integrate the first-order integration voltage Vint1 to generate a second-order integration voltage Vint2; the comparison unit 40 is respectively connected with the capacitor array 10, the first-order integration unit 20 and the second-order integration unit 30, and the comparison unit 40 compares the upper electrode plate voltage, the first-order integration voltage Vint1 and the second-order integration voltage Vint2 and outputs a digital signal; the logic unit 50 is connected to the comparing unit 40, and the logic unit 50 processes the digital signal to obtain a switching control signal and a clock signal Φc, wherein the clock signal Φc is applied to the comparing unit 40, and the switching control signal is used for controlling the capacitor array 10 to perform capacitor switching.
Specifically, the capacitor array 10 includes a plurality of capacitors C1-Cn, the upper plates of the plurality of capacitors C1-Cn are connected, the upper plate of the capacitor array 10 is connected to the second input terminal of the comparing unit 40, and the logic unit 50 can change the voltage of the upper plate of the capacitor array 10 by switching the connection of the lower plate of the capacitor in the capacitor array 10 to the reference positive voltage Vrefp or the reference negative voltage Vrefn. After the capacitor array 10 completes the capacitor switching, the residual voltage Vres is remained on the upper plate of the capacitor array 10, the first integrating module 21 and the second integrating module 22 alternately collect and integrate the residual voltage Vres to generate a first-order integrated voltage Vint1, and store the first-order integrated voltage Vint1, the third integrating module 31 and the fourth integrating module 32 alternately integrate the first-order integrated voltage Vint1 to generate a second-order integrated voltage Vint2, store the second-order integrated voltage Vint2, and provide the first-order integrated voltage Vint1 and the second-order integrated voltage Vint2 to the comparing unit 40 after the next capacitor array 10 completes the switching. The first input end of the comparison unit 40 is connected to the output end of the first-order integration unit 20, the second input end of the comparison unit 40 is connected to the second-order integration unit 30, the third input end of the comparison unit 40 is grounded, and the comparison unit 40 outputs a digital signal according to the upper plate voltage, the first-order integration voltage Vint1 and the second-order integration voltage Vint 2.
The logic unit 50 adopts asynchronous sequential logic, the logic unit 50 includes a plurality of asynchronous processing clock modules (not shown), the number of the asynchronous processing clock modules is determined according to the number of bits of the analog-to-digital converter, for example, the number of bits of the analog-to-digital converter is 5, the number of the asynchronous processing clock modules is 5, the asynchronous processing clock modules include a clock generating sub-module (not shown) and a switch control sub-module (not shown), the clock generating sub-module is used for generating a clock signal Φc according to a digital signal and providing the clock signal Φc to the comparing unit 40, the comparing unit 40 compares when the clock signal Φc is at a high level, the comparing unit 40 resets when the clock signal Φc is at a low level, and the switch control sub-module is used for generating a switch control signal according to the digital signal and switching the connection mode of the lower electrode plate of the capacitor array 10 according to the switch control signal.
The upper plate of the capacitive array 10 is further adapted to be connected to a common mode voltage Vcm via a first sampling switch S, and the lower plate of the capacitive array 10 is connected to the analog signal Vin via a second sampling switch Sd and to the common mode voltage Vcm via a switch. In the sampling stage, the first sampling switch S and the second sampling switch Sd are closed, the upper plate voltage of the capacitor array 10 is Vcm-Vin, after sampling, the first sampling switch S is opened, then the second sampling switch Sd is opened, after the second sampling switch Sd is opened, the switch is controlled to be connected to the common mode voltage Vcm, the upper plate voltage of the capacitor array 10 is-Vin, and then the switch is in a suspended state.
In the conversion stage, the lower plate of the highest capacitor (i.e. the capacitor Cn) is connected to the reference positive voltage Vrefp, the lower plates of the other capacitors are connected to the reference negative voltage Vrefn, the voltage of the upper plate of the capacitor array 10 is-vin+vrefp/2, the first input end of the comparison unit 40 is the first-order integrated voltage Vint1 of the previous period, the voltage of the second input end of the comparison unit 40 is-vin+vrefp/2, the third input end of the comparison unit 40 is the second-order integrated voltage Vint2 of the previous period, -vin+vrefp/2+vint1 (N-1) +vint2 (N-1) > 0, the comparison unit 40 outputs 1 when the clock signal Φc is at high level, and the logic unit 50 switches the lower plate of the capacitor Cn to the reference negative voltage Vrefn, so that the first bit is 0; -vin+vrefp/2+vint1 (N-1) +vint2 (N-1). Ltoreq.0, the comparison unit 40 outputs 0, the logic unit 50 switches the lower plate of the capacitor Cn to the reference positive voltage Vrefp, and therefore the first bit is 0.
The lower plate of the next highest capacitor (i.e., capacitor Cn-1) is then connected to the reference positive voltage Vrefp, and the lower plates of the capacitors other than the capacitor Cn and the capacitor Cn-1 are connected to the reference negative voltage Vrefn. If the lower plate of the capacitor Cn is connected with the reference negative voltage Vrefn, the voltage of the upper plate of the capacitor array 10 is-vin+Vrefp/4; if the lower plate of the capacitor Cn is connected to a reference positive voltage Vrefp, the voltage of the upper plate of the capacitor array 10 is-vin+Vrefp/2+Vrefp/4. The comparison unit 40 then performs comparison, and the logic unit 50 switches the connection mode of the capacitor Cn-1 according to the result output from the comparison unit 40. The comparison of the latter capacitor is the same as the comparison of the capacitor Cn and the capacitor Cn-1, and will not be described here again.
After all the capacitors in the capacitor array 10 are switched, one of the first integration module 21 and the second integration module 22 collects and integrates the residual voltage Vres of the current period, then the other of the first integration module 21 and the second integration module 22 stores the first-order integrated voltage Vint1, one of the third integration module 31 and the fourth integration module 32 integrates the first-order integrated voltage Vint1, and the other of the third integration module 31 and the fourth integration module 32 stores the second-order integrated voltage Vint 2.
For example, after the capacitor array 10 completes the capacitor switching of the N-1 th period, the first integrating module 21 collects and integrates the residual voltage Vres (N-1) to generate the first-order integrated voltage Vint1 (N-1) of the N-1 th period, the second integrating module 22 stores the first-order integrated voltage Vint1 (N-1) of the N-1 th period, the third integrating module 31 integrates the first-order integrated voltage Vint1 (N-1) of the N-1 th period to generate the second-order integrated voltage Vint2 (N-1) of the N-1 th period, and the fourth integrating module 32 stores the second-order integrated voltage Vint2 (N-1) of the N-1 th period. When the capacitor array 10 performs the capacitor switching in the nth period, the second integrating module 22 provides the first-order integrated voltage Vint1 (N-1) in the nth period to the comparing unit 40, the fourth integrating module 32 provides the second-order integrated voltage Vint2 (N-1) in the nth period to the comparing unit 40, and the comparing unit 40 outputs the digital signal according to the plate voltage in the nth period, the first-order integrated voltage Vint1 (N-1) in the nth period, and the second-order integrated voltage Vint2 (N-1) in the nth-1 period. After the capacitor array 10 completes the capacitor switching of the nth period, the second integrating module 22 collects and integrates the residual voltage Vres (N), and since the second integrating module 22 stores the first-order integrated voltage Vint1 (N) of the nth-1 period, transmission of the first-order integrated voltage Vint1 (N) is not needed, loss of signal transmission is reduced, the second integrating module 22 generates the first-order integrated voltage Vint1 (N) of the nth period, the first integrating module 21 stores the first-order integrated voltage Vint1 (N) of the nth period, the fourth integrating module 32 integrates the second-order integrated voltage Vint2 (N) of the nth period, and since the fourth integrating module 32 stores the second-order integrated voltage Vint2 (N) of the nth-1 period, transmission of the second-order integrated voltage Vint2 (N) is not needed, loss of signal transmission is reduced, the second-order integrated voltage of the nth period is generated, and the third integrating module 31 stores the second-order integrated voltage Vint2 (N) of the nth period. When the capacitor array 10 performs the capacitance switching in the n+1th period, the first integrating module 21 provides the first-order integrated voltage Vint1 (N) in the N-th period to the comparing unit 40, the third integrating module 31 provides the second-order integrated voltage Vint2 (N) in the N-th period to the comparing unit 40, and the comparing unit 40 outputs the digital signal according to the plate voltage in the n+1th period, the first-order integrated voltage Vint1 (N) in the N-th period, and the second-order integrated voltage Vint2 (N) in the N-th period.
In an alternative embodiment, the comparison unit 40 is a second operational amplifier.
In practical applications, the operation sequence of the integrating module is not limited to the above-mentioned method, and the first integrating module 21 and the fourth integrating module 32 may perform the first-order integration and the second-order integration on the residual voltage Vres (N-1) of the N-1 th period, or the second integrating module 22 and the third integrating module 31 may perform the first-order integration and the second-order integration on the residual voltage Vres (N-1) of the N-1 th period, which is not limited in this particular.
In some embodiments, as shown in fig. 2, the first integration module 21, the second integration module 22, the third integration module 31, and the fourth integration module 32 are capacitors, respectively.
Specifically, the analog-to-digital converter of the present embodiment adopts a passive integration mode, where the first integration module 21 is a first capacitor Ci1, the second integration module 22 is a second capacitor Ci2, the third integration module 31 is a third capacitor Ci3, and the fourth integration module 32 is a fourth capacitor Ci4.
After the capacitor array 10 completes the capacitor switching of the nth period, if the first capacitor Ci1 samples the residual voltage Vres (N) of the nth period on the capacitor array 10 and performs an integration operation with the historical residual voltage Vres (N-1). Equation (1) can be derived from the principle of conservation of charge:
（1）
Wherein,first order integrated voltage for the N-1 th period, ">An integration voltage obtained by integrating the residual voltage Vres (N) of the nth period for the first capacitor Ci 1.
After the first-order integrated voltage Vint1 is obtained, if the third capacitor Ci3 integrates the first-order integrated voltage Vint1, formula (2) can be obtained according to the charge conservation theorem:
（2）
wherein,is the second order integral voltage of the N-1 th period, ">An integration voltage obtained by integrating the first-order integration voltage Vint1 of the nth period for the third capacitor Ci 3.
It should be noted that the number of the substrates,and->For intermediate process voltages, a pair +.>And->The first-order integrated voltage Vint1 and the second-order integrated voltage Vint2 are obtained by performing a process, and a specific process will be described below.
Further, in some embodiments, the capacitance of the first integration module 21, the capacitance of the second integration module 22, the capacitance of the third integration module 31, and the capacitance of the fourth integration module 32 are the capacitance of the capacitor array 10, respectively.
It can be understood that the capacitance values of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3 and the fourth capacitor Ci4 are the same as the capacitance value of the capacitor array 10, and the capacitance value relationship between the first capacitor Ci1 and the capacitor array 10 is substituted into the formula (1), so that the formula (3) can be obtained:
（3）
Substituting the capacitance relation between the first capacitor Ci1 and the capacitor array 10 into formula (2) can result in formula (4):
（4）
the capacitance values of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3, and the fourth capacitor Ci4 are not limited to the capacitance value of the capacitor array 10, and may be other capacitance values, but the capacitance values of the first capacitor Ci1 and the second capacitor Ci2 need to be kept uniform, and the capacitance values of the third capacitor Ci3 and the fourth capacitor Ci4 need to be kept uniform.
In the above embodiment, after the capacitor array completes the capacitor switching, the first integration module and the second integration module alternately perform the first-order integration, and the third integration module and the fourth integration module alternately perform the second-order integration, so that the signal loss in the integration process is reduced, the second-order noise shaping capability of the SAR ADC is improved, and the accuracy of the SAR ADC is improved.
In some embodiments, as shown in fig. 2, the first order integration unit 20 further includes: the first compensation module 23, the first compensation module 23 is disposed between the first integration module 21 and the second integration module 22, the first compensation module 23 compensates the integrated voltage generated by one of the first integration module 21 and the second integration module 22 to generate the first-order integrated voltage Vint1, and provides the first-order integrated voltage Vint1 to the other of the first integration module 21 and the second integration module 22 so that the other of the first integration module 21 and the second integration module 22 stores the first-order integrated voltage Vint 1.
Specifically, as can be seen from the formula (3), one of the first integration module 21 or the second integration module 22 will attenuate when the residual voltage Vres is integrated in the first order, so the first compensation module 23 is required to compensate the attenuation caused by the passive lossy integration back to obtain the first order integrated voltage Vint1, and the first order integrated voltage Vint1 is stored in the other of the first integration module 21 or the second integration module 22.
For example, if the first integration module 21 collects and integrates the nth period residual voltage Vres (N), the first compensation module 23 compensates the integrated voltage of the formula (3) to obtain the first order integrated voltage Vint1 (N) as shown in the formula (5), and stores the first order integrated voltage Vint1 (N) in the second integration module 22:
（5）
converting equation (5) to the z-domain can result in equation (6):
（6）
in the n+1 cycle, the second integration module 22 collects and integrates the residual voltage Vres (n+1), the first compensation module 23 compensates the integrated voltage generated by the second integration module 22 to generate the first-order integrated voltage Vint1 (n+1) in the n+1 cycle, and the first integration module 21 stores the first-order integrated voltage Vint1 (n+1) in the n+1 cycle.
In some embodiments, as shown in fig. 2, the second order integration unit 30 further includes: the second compensation module 33, the storage capacitor Ci5 and the third compensation module 34, wherein the input end of the second compensation module 33 is connected with the upper polar plate of the capacitor array 10, the second compensation module 33 compensates the integrated voltage generated by one of the first integration module 21 and the second integration module 22 to generate a first-order integrated voltage Vint1, one end of the storage capacitor Ci5 is respectively connected with the output end of the second compensation module 33, the third integration module 31 and the fourth integration module 32, the other end of the storage capacitor Ci5 is grounded, the storage capacitor Ci5 stores the first-order integrated voltage Vint1, the first-order integrated voltage Vint1 is provided to the third integration module 31 or the fourth integration module 32, the third compensation module 34 is arranged between the third integration module 31 and the fourth integration module 32, the third compensation module 34 compensates the integrated voltage generated by one of the third integration module 31 and the fourth integration module 32 to generate a second-order integrated voltage Vint2, and the second-order integrated voltage Vint2 is provided to the other of the third integration module 31 and the fourth integration module 32 to store the second-order integrated voltage Vint 2.
Specifically, after the first integration module 21 or the second integration module 22 integrates the residual voltage Vres, the voltage of the upper plate of the first integration module 21 or the second integration module 22 is the integrated voltage before compensation, and since the upper plate of the capacitor array 10 is connected to the first integration module 21 and the second integration module 22 respectively, the voltage of the upper plate of the capacitor array 10 becomes the integrated voltage before compensation, the second compensation module 33 compensates the voltage to generate the first-order integrated voltage Vint1, and stores the first-order integrated voltage Vint1 on the storage capacitor Ci5, so that the third integration module 31 and the fourth integration module 32 can collect and integrate the first-order integrated voltage Vint1 from the upper plate of the storage capacitor Ci 5. As can be seen from the formula (4), one of the third integration module 31 or the fourth integration module 32 will attenuate when performing the second-order integration on the first-order integration voltage Vint1, and therefore the third compensation module 34 is required to compensate the attenuation caused by the passive lossy integration back to obtain the second-order integration voltage Vint2, and store the second-order integration voltage Vint2 into the other of the third integration module 31 or the fourth integration module 32.
Further, in some embodiments, the capacitance value of the storage capacitor Ci5 is the capacitance value of the capacitor array 10.
Specifically, a storage capacitorCi5 is used to store the first-order integrated voltage Vint1 (N), since the capacitance of the storage capacitor Ci5 is the same as that of the capacitor array 10, the capacitor Ci5 can be used to storeWritten as->Thereby obtaining formula (2). Meanwhile, since the capacitance values of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3, the fourth capacitor Ci4, the storage capacitor Ci5 and the capacitor array 10 are the same, the attenuation of the passive lossy integration is the same, and the gains of the first compensation module 23, the second compensation module 33 and the third compensation module 34 are the same, so that the first compensation module 23, the second compensation module 33 and the third compensation module 34 can use the same amplifying circuit, thereby making the circuit structure of the SAR ADC simpler.
For example, if the first integration module 21 collects and integrates the nth period residual voltage Vres (N), the first compensation module 23 compensates the integrated voltage of the formula (4) to obtain the first order integrated voltage Vint1 (N) as shown in the formula (7), and stores the first order integrated voltage Vint1 (N) in the second integration module 22:
（7）
converting equation (7) to the z-domain can yield equation (8):
（8）
from equations (6) and (8) the transfer function (9) of the analog-to-digital converter can be derived from the mersen law:
（9）
Wherein,for the digital signal output by the comparison unit 40, +.>Is the input analog signal Vin, ">For quantization noise +.>。
As can be seen from equation (9), the analog-to-digital converter of the present embodiment has a normalized second-order noise shaping effect.
In the n+1 cycle, the fourth integration module 32 collects and integrates the first-order integrated voltage Vint1 (n+1), the third compensation module 34 compensates the integrated voltage generated by the fourth integration module 32 to generate the second-order integrated voltage Vint2 (n+1) in the n+1 cycle, and the third integration module 31 stores the second-order integrated voltage Vint2 (n+1) in the n+1 cycle.
In the above embodiment, the attenuation caused by passive lossy integration is compensated by the first compensation module, the second compensation module and the third compensation module, so that the second-order noise shaping capability of which the zero point of the noise transfer function is 1 is realized, and the precision of the SAR ADC is further improved.
In some embodiments, the analog-to-digital converter further comprises: and the switching unit is respectively connected with the first-order integration unit 20 and the second-order integration unit 30, and switches the first integration module 21 and the second integration module 22 and the third integration module 31 and the fourth integration module 32 to alternately operate.
That is, the operation timings of the first and second integration modules 21 and 22 and the third and fourth integration modules 31 and 32 are controlled by the switching unit.
In some embodiments, as shown in fig. 3, the switching unit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, a sixteenth switch S16 and a seventeenth switch S17, wherein the first switch S1 is disposed between an upper plate of the capacitor array 10 and one end of the first integration module 21, the second switch S2 is disposed between one end of the first integration module 21 and an input end of the first compensation module 23, the third switch S3 is disposed between one end of the first integration module 21 and an output end of the first compensation module 23, the fourth switch S4 is disposed between one end of the first integration module 21 and a first input end of the comparison unit 40, a fifth switch S5 is provided between the upper plate of the capacitor array 10 and one end of the second integration module 22, a sixth switch S6 is provided between one end of the second integration module 22 and the input end of the first compensation module 23, a seventh switch S7 is provided between one end of the second integration module 22 and the output end of the first compensation module 23, an eighth switch S8 is provided between one end of the second integration module 22 and the third input end of the comparison unit 40, a ninth switch S9 is provided between the upper plate of the capacitor array 10 and the input end of the second compensation module 33, a tenth switch S10 is provided between one end of the storage capacitor Ci5 and one end of the third integration module 31, an eleventh switch S11 is provided between one end of the third integration module 31 and the input end of the third compensation module 34, a twelfth switch S12 is provided between one end of the third integration module 31 and the output end of the third compensation module 34, the thirteenth switch S13 is disposed between one end of the third integration module 31 and the third input end of the comparison unit 40, the fourteenth switch S14 is disposed between one end of the storage capacitor Ci5 and one end of the fourth integration module 32, the fifteenth switch S15 is disposed between the input end of the third compensation module 34 and one end of the fourth integration module 32, the sixteenth switch S16 is disposed between one end of the fourth integration module 32 and the output end of the third compensation module 34, the seventeenth switch S17 is disposed between the fourth integration module 32 and the third input end of the comparison unit 40, wherein the other end of the first integration module 21 is grounded, the other end of the second integration module 22 is grounded, the other end of the third integration module 31 is grounded, and the other end of the fourth integration module 32 is grounded.
Specifically, the first switch S1 and the fifth switch S5 are used for controlling the first integration module 21 and the second integration module 22 to collect and integrate the residual voltage Vres, when the first switch S1 is closed, the first integration module 21 collects and integrates the residual voltage Vres, and when the fifth switch S5 is closed, the second integration module 22 collects and integrates the residual voltage Vres. The second switch S2, the third switch S3, the sixth switch S6 and the seventh switch S7 are switched according to the working states of the first integration module 21 and the second integration module 22, when the second switch S2 is closed, the input end of the first compensation module 23 is connected with one end of the first integration module 21, the first compensation module 23 compensates the integrated voltage of the first integration module 21, when the sixth switch S6 is closed, the first compensation module 23 compensates the integrated voltage of the second integration module 22, when the third switch S3 is closed, the first compensation module 23 provides the first-order integrated voltage Vint1 to the first integration module 21, and when the seventh switch S7 is closed, the first compensation module 23 provides the first-order integrated voltage Vint1 to the second integration module 22. The fourth switch S4 and the eighth switch S8 are used for controlling the first integration module 21 and the second integration module 22 to provide the first-order integrated voltage Vint1 to the comparison unit 40, when the fourth switch S4 is closed, the first integration module 21 provides the first-order integrated voltage Vint1 to the first terminal of the comparison unit 40, and when the eighth switch S8 is closed, the second integration module 22 provides the first-order integrated voltage Vint1 to the first terminal of the comparison unit 40. The ninth switch S9 is configured to control the second compensation module 33 to compensate the integrated voltage of the first integration module 21 or the second integration module 22, and when the ninth switch S9 is closed, the second compensation module 33 compensates the integrated voltage of the first integration module 21 or the second integration module 22 to generate a first-order integrated voltage Vint1. The tenth switch S10 and the fourteenth switch S14 are configured to control the third integration module 31 and the fourth integration module 32 to integrate the first-order integrated voltage Vint1, when the tenth switch S10 is closed, the third integration module 31 integrates the first-order integrated voltage Vint1, and when the fourteenth switch S14 is closed, the fourth integration module 32 integrates the first-order integrated voltage Vint1. The eleventh switch S11, the twelfth switch S12, the fifteenth switch S15, and the sixteenth switch S16 are switched according to the operating states of the third integration module 31 and the fourth integration module 32, when the eleventh switch S11 is closed, an input end of the third compensation module 34 is connected to one end of the third integration module 31, the third compensation module 34 compensates the integrated voltage of the third integration module 31, when the fifteenth switch S15 is closed, the third compensation module 34 compensates the integrated voltage of the fourth integration module 32, when the twelfth switch S12 is closed, the third compensation module 34 provides the second-order integrated voltage Vint2 to the third integration module 31, and when the sixteenth switch S16 is closed, the third compensation module 34 provides the second-order integrated voltage Vint2 to the fourth integration module 32.
In some embodiments, as shown in fig. 4, the second switch S2, the fourth switch S4, and the tenth switch S10 are simultaneously switched, the third switch S3, the sixth switch S6, and the fourteenth switch S14 are simultaneously switched, the fourth switch S4 and the thirteenth switch S13 are simultaneously switched, the eighth switch S8 and the seventeenth switch S17 are simultaneously switched, the eleventh switch S11 and the sixteenth switch S16 are simultaneously switched, and the twelfth switch S12 and the fifteenth switch S15 are simultaneously switched.
Specifically, the first control signal Φ1 is used to control the first switch S1, the second control signal Φ2 is used to control the second switch S2, the fourth switch S4, and the tenth switch S10, the third control signal Φ3 is used to control the eleventh switch S11 and the sixteenth switch S16, the fourth control signal Φ4 is used to control the eighth switch S8 and the seventeenth switch S17, the fifth control signal Φ5 is used to control the fifth switch S5, the sixth control signal Φ6 is used to control the third switch S3, the sixth switch S6, and the fourteenth switch S14, the seventh control signal Φ7 is used to control the twelfth switch S12 and the fifteenth switch S15, the eighth control signal Φ8 is used to control the fourth switch S4 and the thirteenth switch S13, and the ninth control signal Φ9 is used to control the ninth switch S9.
In some embodiments, as shown in fig. 4, in case the capacitor array 10 completes the capacitor switching, the first switch S1 is closed so that the first integration module 21 collects and integrates the residual voltage Vres, after the first integration module 21 completes the integration, the second switch S2 and the seventh switch S7 are closed so that the second compensation module 33 generates the first order integration voltage Vint1 and provides the first order integration voltage Vint1 to the second integration module 22, and after the second integration module 22 completes storing the first order integration voltage Vint1, the eighth switch S8 is closed so that the second integration module 22 provides the first order integration to the first input terminal of the comparison unit 40.
Specifically, the first sampling control signal Φs is used to control the first sampling switch S, when the first sampling control signal Φs is at a high level, the capacitor array 10 samples the analog signal Vin, and after the sampling is completed, the analog-to-digital converter performs conversion when the clock signal Φc is at a high level. In the N-1 th period, after the capacitors of the capacitor array 10 are switched, the first control signal Φ1 is at a high level, the first switch S1 is closed, and the first integration module 21 collects and integrates the residual voltage Vres (N-1) in the N-1 th period. After the integration of the first integration module 21 is completed, the first control signal Φ1 controls the first switch S1 to be opened, then the second control signal Φ2 controls the second switch S2 and the seventh switch S7 to be closed, the first integration module 21 provides the integrated voltage to the first compensation module 23, the first compensation module 23 compensates the integrated voltage to generate the first-order integrated voltage Vint1 (N-1), and the second integration module 22 stores the first-order integrated voltage Vint1 (N-1). Since the second integration module 22 stores the first-order integration voltage Vint1 (N-1), the fourth control signal Φ4 controls the eighth switch S8 to be closed during the nth period, the second integration module 22 provides the first-order integration voltage Vint1 to the comparison unit 40, and the comparison unit 40 sums and quantizes the first-order integration voltage Vint1 (N-1) during the N-1 period and the upper plate voltage during the nth period when the clock signal Φc is at a high level.
In an alternative embodiment, after the comparing unit 40 outputs the digital signal, the fourth control signal Φ4 controls the eighth switch S8 to be turned off, and the second integrating module 22 stops outputting the first-order integrated voltage Vint1 to the comparing unit 40.
In some embodiments, as shown in fig. 4, in the case where the capacitor array 10 completes the capacitor switching, the fifth switch S5 is closed so that the second integration module 22 collects and integrates the residual voltage Vres, after the second integration module 22 completes the integration, the third switch S3 and the sixth switch S6 are closed so that the second compensation module 33 generates the first order integration voltage Vint1 and provides the first order integration voltage Vint1 to the first integration module 21, and after the first integration module 21 completes storing the first order integration voltage Vint1, the fourth switch S4 is closed so that the first integration module 21 provides the first order integration to the first input terminal of the comparison unit 40.
Specifically, after the capacitors of the capacitor array 10 are switched in the nth period, the fifth control signal Φ5 is high, the fifth switch S5 is closed, and the second integrating module 22 collects and integrates the residual voltage Vres (N) in the nth period because the second integrating module 22 stores the first-order integrated voltage Vint1 (N-1) in the nth period. After the second integration module 22 completes integration, the fifth control signal Φ5 controls the fifth switch S5 to be opened, then the sixth control signal Φ6 controls the third switch S3 and the sixth switch S6 to be closed, the second integration module 22 provides the integrated voltage to the first compensation module 23, the first compensation module 23 compensates the integrated voltage to generate the first-order integrated voltage Vint1 (N), and the first integration module 21 stores the first-order integrated voltage Vint1 (N). Since the first integration module 21 stores the first-order integration voltage Vint1 (N), the eighth control signal Φ8 controls the eighth switch S8 to be closed in the n+1th period, the first integration module 21 provides the first-order integration voltage Vint1 (N) to the comparison unit 40, and the comparison unit 40 sums and quantizes the first-order integration voltage Vint1 (N) of the nth period and the upper plate voltage of the n+1th period when the clock signal Φc is at a high level.
In an alternative embodiment, after the comparing unit 40 outputs the digital signal, the eighth control signal Φ8 controls the fourth switch S4 to be turned off, and the first integrating module 21 stops outputting the first-order integrated voltage Vint1 to the comparing unit 40.
In some embodiments, as shown in fig. 4, after the first integration module 21 or the second integration module 22 completes the integration, the ninth switch S9 is closed so that the second compensation module 33 generates the first order integrated voltage Vint1.
Specifically, after the first integration module 21 or the second integration module 22 completes integration, that is, after the first switch S1 or the fifth switch S5 is turned off, the ninth control signal Φ9 controls the ninth switch S9 to be turned on, the second compensation module 33 compensates the integrated voltage of the first integration module 21 or the second integration module 22 to generate the first-order integrated voltage Vint1, and before the third integration module 31 or the fourth integration module 32 performs integration, the ninth control signal Φ9 controls the ninth switch S9 to be turned off.
In some embodiments, as shown in fig. 4, after the second compensation module 33 generates the first order integrated voltage Vint1, the tenth switch S10 is closed so that the third integration module 31 integrates the first order integrated voltage Vint1, after the third integration module 31 completes the integration, the eleventh switch S11 and the sixteenth switch S16 are closed so that the third compensation module 34 generates the second order integrated voltage Vint2 and provides the second order integrated voltage Vint2 to the fourth integration module 32, and after the fourth integration module 32 completes storing the second order integrated voltage Vint2, the seventeenth switch S17 is closed so that the fourth integration module 32 provides the second order integration to the third input of the comparison unit 40.
Specifically, after the second compensation module 33 generates the first-order integrated voltage Vint1 (N-1) in the N-1 th period, the second control signal Φ2 controls the second switch S2, the seventh switch S7 and the tenth switch S10 to be simultaneously closed, the third integration module 31 collects and integrates the first-order integrated voltage Vint1 (N-1), and the first compensation module 23 simultaneously generates the first-order integrated voltage Vint1 (N-1). After the third integration module 31 completes integration, the third control signal Φ3 controls the eleventh switch S11 and the sixteenth switch S16 to be closed, the third compensation module 34 compensates the integrated voltage to generate a second-order integrated voltage Vint2 (N-1), and the fourth integration module 32 stores the second-order integrated voltage Vint2 (N-1). Because the fourth integration module 32 stores the second-order integrated voltage Vint2 (N-1), the fourth control signal Φ4 controls the eighth switch S8 and the seventeenth switch S17 to close in the nth period, the fourth integration module 32 provides the second-order integrated voltage Vint2 (N-1) to the comparison unit 40, and the second integration module 22 simultaneously provides the first-order integration to the comparison unit 40. The comparison unit 40 sums and quantizes the first-order integrated voltage Vint1 (N-1) and the second-order integrated voltage Vint2 (N-1) of the N-1 th period and the upper plate voltage of the N-th period when the clock signal Φc is at a high level.
In some embodiments, as shown in fig. 4, after the second compensation module 33 generates the first order integrated voltage Vint1, the fourteenth switch S14 is closed so that the fourth integration module 32 integrates the first order integrated voltage Vint1, after the fourth integration module 32 completes the integration, the twelfth switch S12 and the fifteenth switch S15 are closed so that the third compensation module 34 generates the second order integrated voltage Vint2 and provides the second order integrated voltage Vint2 to the third integration module 31, and after the third integration module 31 completes storing the second order integrated voltage Vint2, the thirteenth switch S13 is closed so that the third integration module 31 provides the second order integration to the third input of the comparison unit 40.
Specifically, after the second compensation module 33 generates the first-order integrated voltage Vint1 (N) in the nth period, the sixth control signal Φ6 controls the third switch S3, the sixth switch S6 and the fourteenth switch S14 to be simultaneously closed, the fourth integration module 32 collects and integrates the first-order integrated voltage Vint1 (N), and the second compensation module 33 simultaneously generates the first-order integrated voltage Vint1 (N). After the fourth integration module 32 completes integration, the seventh control signal Φ7 controls the twelfth switch S12 and the fifteenth switch S15 to be closed, the third compensation module 34 compensates the integrated voltage to generate a second-order integrated voltage Vint2 (N), and the third integration module 31 stores the second-order integrated voltage Vint2 (N). Since the third integration module 31 stores the second-order integrated voltage Vint2 (N), the eighth control signal Φ8 controls the fourth switch S4 and the thirteenth switch S13 to be closed in the n+1th period, the third integration module 31 supplies the second-order integrated voltage Vint2 (N) to the comparing unit 40, and the first integration module 21 simultaneously supplies the first-order integration to the comparing unit 40. The comparison unit 40 sums and quantizes the first and second integrated voltages Vint1 (N) and Vint2 (N) of the nth period and the upper plate voltage of the n+1th period when the clock signal Φc is at a high level.
In the above embodiment, the operation timings of the first integration module, the second integration module, the third integration module and the fourth integration module are controlled by the plurality of switches, so that compared with the SAR ADC with the same precision, the cost of the circuit and the design difficulty of the SAR ADC are reduced, the power consumption of the SAR ADC is reduced, and the design goal of low power consumption is realized.
In some embodiments, as shown in fig. 5, the first compensation module 23, the second compensation module 33, and the third compensation module 34 each include: the first operational amplifier FIA, the first resistor R1 and the second resistor R2, wherein one end of the first resistor R1 is a signal input end, the other end of the first resistor R1 is connected with the negative input end of the first operational amplifier FIA and is provided with a first node J1, the positive input end of the first operational amplifier FIA is grounded, one end of the second resistor R2 is connected with the first node J1, and the other end of the second resistor R2 is respectively connected with the output end of the first operational amplifier FIA and is a signal output end.
Specifically, since the capacitance values of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3, the fourth capacitor Ci4, the storage capacitor Ci5, and the capacitor array 10 are the same, the circuits of the first compensation module 23, the second compensation module 33, and the third compensation module 34 are the same. One end of the first resistor R1 in the first compensation module 23 is connected to the connection point of the second switch S2 and the sixth switch S6, and the output end of the first operational amplifier FIA in the first compensation module 23 is connected to the connection point of the third switch S3 and the seventh switch S7, respectively. One end of a first resistor R1 in the second compensation module 33 is connected with the other end of the ninth switch S9, and the output end of the first operational amplifier FIA in the second compensation module 33 is connected with the upper polar plate of the storage capacitor Ci 5. One end of the first resistor R1 in the third compensation module 34 is connected to the connection point of the eleventh switch S11 and the fifteenth switch S15, and the output end of the first operational amplifier FIA in the third compensation module 34 is connected to the connection point of the twelfth switch S12 and the sixteenth switch S16.
It should be noted that the first operational amplifier FIA may be a dynamic amplifier, which may further reduce signal noise, thereby further improving the accuracy of the SAR ADC.
In the above embodiment, attenuation in the passive integration process is compensated by the multiplexing mode of the first operational amplifier, and the first operational amplifier in the first compensation module and the third compensation module directly provides the compensated integrated voltage to the other integration module, so that loss in the signal transmission process is reduced, and the accuracy of the SAR ADC is improved.
In some embodiments, as shown in fig. 6 and 7, the capacitor array 10 includes two capacitor arrays 11 and 12, the first-order integrating unit 20 includes two capacitor arrays, the first-order integrating unit 201 and the second-order integrating unit 202 include two capacitor arrays, the second-order integrating unit 30 includes two capacitor arrays, the first-order integrating unit 201 includes a first positive input terminal of the comparing unit 40, the upper plate of the first capacitor array 11 includes a second positive input terminal of the comparing unit 40, the first-order integrating unit 301 includes a third positive input terminal of the comparing unit 40, the second-order integrating unit 202 includes a first negative input terminal of the comparing unit 40, the upper plate of the second capacitor array 12 includes a second negative input terminal of the comparing unit 40, and the second-order integrating unit 302 includes a second negative input terminal of the comparing unit 40, and the upper plate of the first capacitor array 11 includes a third positive input terminal of the comparing unit 40, the second negative input terminal of the comparing unit 40, the first negative input terminal of the second negative input terminal of the comparing unit, and the second negative input terminal of the comparing unit. The first compensation unit 60, the second compensation unit 70 and the third compensation unit 80, wherein, the positive input end of the first compensation unit 60 is respectively connected with the first integration module 21 and the second integration module 22 in the first order integration unit 201, the positive output end of the first compensation unit 60 is respectively connected with the first integration module 21 and the second integration module 22 in the first order integration unit 201, the negative input end of the first compensation unit 60 is respectively connected with the first integration module 21 and the second integration module 22 in the second first order integration unit 202, the negative output end of the first compensation unit 60 is respectively connected with the first integration module 21 and the second integration module 22 in the second first order integration unit 202, the positive input end of the second compensation unit 70 is connected with the upper polar plate of the first capacitor array 11, the positive output end of the second compensation unit 70 is respectively connected with the third integration module 31 and the fourth integration module 32 in the first second order integration unit 301, the negative input end of the second compensation unit 70 is connected to the upper electrode plate of the second capacitor array 12, the negative output end of the second compensation unit 70 is connected to the first integration module 21 and the second integration module 22 in the second first-order integration unit 202, the positive input end of the third compensation unit 80 is connected to the third integration module 31 and the fourth integration module 32 in the first second-order integration unit 301, the positive output end of the third compensation unit 80 is connected to the third integration module 31 and the fourth integration module 32 in the first second-order integration unit 301, the negative input end of the third compensation unit 80 is connected to the third integration module 31 and the fourth integration module 32 in the second-order integration unit 302, and the negative output end of the third compensation unit 70 is connected to the third integration module 31 and the fourth integration module 32 in the second-order integration unit 302.
Specifically, the analog-to-digital converter of this embodiment adopts differential input, the capacitor array 10 has two, namely, the first capacitor array 11 and the second capacitor array 12, the first capacitor array 11 is suitable for inputting the positive output voltage of the analog signal Vin, the second capacitor array 12 is suitable for inputting the negative output voltage of the analog signal Vin, the first order integration unit 20 has two, namely, the first order integration unit 201 and the second first order integration unit 202, the second order integration unit 30 has two, namely, the first second order integration unit 301 and the second order integration unit 302, the comparison unit 40 has 6 input ends, wherein, 3 input ends are positive input ends, 3 input ends are negative input ends, the input end of the first order integration unit 201 is connected with the upper polar plate of the first capacitor array 11, the output end of the first order integration unit 201 is connected with the first positive input end of the comparison unit 40, the input end of the second order integration unit 301 is connected with the second positive input end of the first capacitor array 11, the input end of the second order integration unit 301 is connected with the second positive input end of the second order integration unit 302, and the output end of the second order integration unit 12 is connected with the second input end of the second capacitor array 40, and the output end of the second capacitor array 12 is connected with the second positive input end of the second integration unit 12. Since the structures and the connection manners of the first and second first order integration units 201 and 202 are the same, the first compensation unit 60 compensates for the attenuation of the first and second first order integration units 201 and 202 at the same time. Also, since the structures and connection manners of the first second order integration unit 301 and the second order integration unit 302 are the same, the second compensation unit 70 may compensate the integrated voltages of the first order integration unit 201 and the second first order integration unit 202 at the same time, and the third compensation unit 80 may compensate the attenuations of the first second order integration unit 301 and the second order integration unit 302 at the same time.
Further, in some embodiments, as shown in fig. 8, the first compensation unit 60, the second compensation unit 70, and the third compensation unit 80 respectively include: the first operational amplifier FIA, first resistance R1, second resistance R2, third resistance R3 and fourth resistance R4, wherein, the one end of first resistance R1 is positive signal input, the other end of first resistance R1 links to each other with the positive input of first operational amplifier FIA, and have first node J1, the negative input ground of first operational amplifier FIA second resistance R2's one end links to each other with first node J1, the other end of second resistance R2 links to each other with the positive output of first operational amplifier FIA respectively, and is positive signal output, the one end of third resistance R3 is negative signal input, the other end of third resistance R3 links to each other with the negative input of first operational amplifier FIA, and have second node J2, the one end of fourth resistance R4 links to each other with second node J2, the other end of fourth resistance R4 links to each other with the negative output of first operational amplifier FIA respectively, and is negative signal output.
Specifically, there are two switching units, namely, a first switching unit 91 and a second switching unit 92, the first switching unit 91 is connected to the first-order integrating unit 201 and the first second-order integrating unit 301, respectively, and the second switching unit 92 is connected to the second first-order integrating unit 202 and the second-order integrating unit 302, respectively. One end of a first resistor R1 in the first compensation unit 60 is connected to a connection point of the second switch S2 and the sixth switch S6 in the first switching unit 91, a positive output end of the first operational amplifier FIA in the first compensation unit 60 is connected to a connection point of the third switch S3 and the seventh switch S7 in the first switching unit 91, one end of the third resistor R3 in the first compensation unit 60 is connected to a connection point of the second switch S2 and the sixth switch S6 in the second switching unit 92, and a negative output end of the first operational amplifier FIA in the first compensation unit 60 is connected to a connection point of the third switch S3 and the seventh switch S7 in the second switching unit 92. One end of a first resistor R1 in the second compensation unit 70 is connected to the other end of the ninth switch S9 in the first switching unit 91, the positive output end of the first operational amplifier FIA in the second compensation unit 70 is connected to the upper plate of the storage capacitor Ci5 in the first second-order integration unit 301, one end of a third resistor R3 in the second compensation unit 70 is connected to the other end of the ninth switch S9 in the second switching unit 92, and the negative output end of the first operational amplifier FIA in the second compensation unit 70 is connected to the upper plate of the storage capacitor Ci5 in the second-order integration unit 302. One end of a first resistor R1 in the third compensation unit 80 is connected to the connection point of the eleventh switch S11 and the fifteenth switch S15 in the first switching unit 91, the positive output end of the first operational amplifier FIA in the third compensation unit 80 is connected to the connection point of the twelfth switch S12 and the sixteenth switch S16 in the first switching unit 91, one end of the first resistor R1 in the third compensation unit 80 is connected to the connection point of the eleventh switch S11 and the fifteenth switch S15 in the second switching unit 92, and the negative output end of the first operational amplifier FIA in the third compensation unit 80 is connected to the connection point of the twelfth switch S12 and the sixteenth switch S16 in the second switching unit 92.
It should be noted that, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 need to be set according to the capacitance relationship of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3, the fourth capacitor Ci4, the fifth capacitor, and the capacitor array 10. For example, if the capacitance values of the first capacitor Ci1, the second capacitor Ci2, the third capacitor Ci3, the fourth capacitor Ci4, the fifth capacitor and the capacitor array 10 are the same, the compensation coefficients of the first compensation unit 60, the second compensation unit 70 and the third compensation unit 80 are 2, the ratio of the second resistor R2 to the first resistor R1 is 2, and the ratio of the fourth resistor R4 to the third resistor R3 is 2.
In summary, the analog-to-digital converter according to the embodiment of the invention includes: the capacitor array is suitable for sampling an input analog signal, the upper pole plate voltage is changed under the condition of capacitance switching, residual voltage is reserved on the capacitor array after the capacitor array is switched, the first-order integration unit comprises a first integration module and a second integration module, the first integration module and the second integration module alternately collect and integrate the residual voltage of the capacitor array to generate a first-order integration voltage, one integration module in the first integration module and the second integration module collects and integrates the first-order integration voltage, the other integration module in the first integration module and the second integration module stores the first-order integration voltage, the second-order integration unit comprises a third integration module and a fourth integration module, the third integration module and the fourth integration module alternately integrate the first-order integration voltage to generate a second-order integration voltage, the other integration module in the third integration module and the fourth integration module alternately stores the second-order integration voltage, and the comparison unit carries out integration according to the upper pole plate voltage and the first-order integration voltage, the SAR signal is output, and the SAR signal is subjected to integral transmission accuracy is improved, and the SAR signal is subjected to integral transmission loss is reduced; and the attenuation in the passive integration process is compensated in a multiplexing mode of the operational amplifier, and the first operational amplifier in the first compensation module and the first operational amplifier in the third compensation module directly provide the compensated integrated voltage for the other integration module, so that the loss in the signal transmission process is reduced, the precision of the SAR ADC is improved, and compared with the SAR ADC with the same precision, the circuit cost and the design difficulty of the analog-to-digital converter are reduced, and the design target of low power consumption is realized.
Corresponding to the above embodiment, the embodiment of the invention also provides a processor. As shown in fig. 9, the processor 200 includes the analog-to-digital converter 100 of any of the previous embodiments.
According to the processor provided by the embodiment of the invention, by adopting the analog-to-digital converter, the first-order integration is alternately performed by the first integration module and the second integration module, and the second-order integration is alternately performed by the third integration module and the fourth integration module, so that the signal loss in the integration process is reduced, and the accuracy of the SAR ADC is improved.
Corresponding to the above embodiment, the embodiment of the invention also provides an electronic device. As shown in fig. 10 and 11, the electronic device 300 includes the analog-to-digital converter 100 of any of the foregoing embodiments or the foregoing processor 200.
According to the electronic equipment provided by the embodiment of the invention, by adopting the analog-to-digital converter or the processor, the first-order integration is alternately performed through the first integration module and the second integration module, and the second-order integration is alternately performed through the third integration module and the fourth integration module, so that the signal loss in the integration process is reduced, and the accuracy of the SAR ADC is improved.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, as used in embodiments of the present invention, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the invention that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present invention, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.
In the present invention, unless explicitly stated or limited otherwise in the examples, the terms "mounted," "connected," and "fixed" as used in the examples should be interpreted broadly, e.g., the connection may be a fixed connection, may be a removable connection, or may be integral, and it may be understood that the connection may also be a mechanical connection, an electrical connection, etc.; of course, it may be directly connected, or indirectly connected through an intermediate medium, or may be in communication with each other, or in interaction with each other. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to specific embodiments.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (19)
1. An analog-to-digital converter, comprising:
the capacitor array is suitable for sampling input analog signals and changing the voltage of the upper polar plate under the condition of capacitance switching;
the first-order integration unit comprises a first integration module and a second integration module, wherein the first integration module and the second integration module alternately collect and integrate residual voltage of the capacitor array to generate first-order integrated voltage, and the residual voltage is generated when the capacitor array completes capacitor switching;
the second-order integration unit comprises a third integration module and a fourth integration module, and the third integration module and the fourth integration module alternately integrate the first-order integration voltage to generate a second-order integration voltage;
the comparison unit is respectively connected with the capacitor array, the first-order integration unit and the second-order integration unit, and is used for comparing the upper polar plate voltage, the first-order integration voltage and the second-order integration voltage to output a digital signal;
The logic unit is connected with the comparison unit, and is used for processing the digital signals to obtain switching control signals and clock signals, wherein the clock signals are applied to the comparison unit, and the switching control signals are used for controlling the capacitor array to conduct capacitance switching.
2. The analog-to-digital converter of claim 1, wherein said first order integration unit further comprises: the first compensation module is arranged between the first integration module and the second integration module, compensates the integration voltage generated by one integration module of the first integration module and the second integration module to generate the first-order integration voltage, and provides the first-order integration voltage to the other integration module of the first integration module and the second integration module so that the other integration module of the first integration module and the second integration module stores the first-order integration voltage.
3. The analog-to-digital converter of claim 2, wherein said second order integration unit further comprises: the storage capacitor is connected with the other end of the storage capacitor to be grounded, the storage capacitor stores the first-order integral voltage and provides the first-order integral voltage to the third integral module or the fourth integral module, the third compensation module is arranged between the third integral module and the fourth integral module, and compensates the integral voltage generated by one of the third integral module and the fourth integral module to generate the second-order integral voltage and provides the second-order integral voltage to the other of the third integral module and the fourth integral module for storage.
4. An analog-to-digital converter according to claim 3, further comprising: the switching unit is respectively connected with the first-order integration unit and the second-order integration unit, and is used for switching the first integration module, the second integration module, the third integration module and the fourth integration module to alternately work.
5. The analog-to-digital converter of claim 4, wherein the switching unit comprises: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, and a seventeenth switch, wherein the first switch is disposed between an upper plate of the capacitor array and an input of the first compensation module, the second switch is disposed between an end of the first integration module and an input of the first compensation module, the third switch is disposed between an end of the first integration module and an output of the first compensation module, the fourth switch is disposed between an end of the first integration module and a first input of the comparison unit, the fifth switch is disposed between an upper plate of the capacitor array and an input of the second integration module, the seventh switch is disposed between an end of the second integration module and an input of the first compensation module, the seventh switch is disposed between an end of the second integration module and an input of the compensation module, the eighth switch is disposed between an input of the capacitor array and an output of the compensation module, the fourth switch is disposed between an end of the capacitor array and an input of the eighth switch is disposed between an output of the fourth switch and an output of the compensation module, the thirteenth switch is arranged between one end of the third integration module and the third input end of the comparison unit, the fourteenth switch is arranged between one end of the storage capacitor and one end of the fourth integration module, the fifteenth switch is arranged between the input end of the third compensation module and one end of the fourth integration module, the sixteenth switch is arranged between one end of the fourth integration module and the output end of the third compensation module, the seventeenth switch is arranged between the fourth integration module and the third input end of the comparison unit, the other end of the first integration module is grounded, the other end of the second integration module is grounded, and the other end of the fourth integration module is grounded.
6. The analog-to-digital converter of claim 5, wherein in case the capacitor array completes the capacitor switching, the first switch is closed so that the first integrating module collects and integrates the residual voltage, and after the first integrating module completes the integration, the second switch and the seventh switch are closed so that the second compensating module generates the first order integrated voltage and provides the first order integrated voltage to the second integrating module, and after the second integrating module completes storing the first order integrated voltage, the eighth switch is closed so that the second integrating module provides the first order integrated voltage to the first input of the comparing unit.
7. The analog-to-digital converter of claim 5, wherein in case the capacitor array completes the capacitor switching, the fifth switch is closed so that the second integrating module collects and integrates the residual voltage, and after the second integrating module completes the integration, the third switch and the sixth switch are closed so that the second compensating module generates the first order integrated voltage and provides the first order integrated voltage to the first integrating module, and after the first integrating module completes storing the first order integrated voltage, the fourth switch is closed so that the first integrating module provides the first order integrated voltage to the first input of the comparing unit.
8. The analog-to-digital converter of claim 5, wherein after the first integration module or the second integration module completes integration, the ninth switch is closed so that the second compensation module generates the first order integrated voltage.
9. The analog-to-digital converter of claim 5, wherein after the second compensation module generates the first order integrated voltage, the tenth switch is closed so that the third integration module integrates the first order integrated voltage, after the third integration module completes integration, the eleventh switch and the sixteenth switch are closed so that the third compensation module generates the second order integrated voltage and provides the second order integrated voltage to the fourth integration module, and after the fourth integration module completes storing the second order integrated voltage, the seventeenth switch is closed so that the fourth integration module provides the second order integrated voltage to a third input of the comparison unit.
10. The analog-to-digital converter of claim 5, wherein after the second compensation module generates the first order integrated voltage, the fourteenth switch is closed so that the fourth integration module integrates the first order integrated voltage, after the fourth integration module completes integration, the twelfth switch and the fifteenth switch are closed so that the third compensation module generates the second order integrated voltage and provides the second order integrated voltage to the third integration module, and after the third integration module completes storing the second order integrated voltage, the thirteenth switch is closed so that the third integration module provides the second order integrated voltage to a third input of the comparison unit.
11. The analog-to-digital converter according to any one of claims 5-10, wherein the second, fourth and tenth switches are simultaneously switched, the third, sixth and fourteenth switches are simultaneously switched, the fourth and thirteenth switches are simultaneously switched, the eighth and seventeenth switches are simultaneously switched, the eleventh and sixteenth switches are simultaneously switched, and the twelfth and fifteenth switches are simultaneously switched.
12. An analog-to-digital converter according to claim 3, wherein the capacitance of the storage capacitor is the capacitance of the capacitor array.
13. An analog-to-digital converter according to claim 3, wherein the first compensation module, the second compensation module and the third compensation module each comprise: the circuit comprises a first operational amplifier, a first resistor and a second resistor, wherein one end of the first resistor is a signal input end, the other end of the first resistor is connected with the negative input end of the first operational amplifier and is provided with a first node, the positive input end of the first operational amplifier is grounded, one end of the second resistor is connected with the first node, and the other end of the second resistor is respectively connected with the output end of the first operational amplifier and is a signal output end.
14. The analog-to-digital converter of claim 1, wherein the capacitor array has two capacitor arrays, a first capacitor array and a second capacitor array, the first-order integrating unit has two capacitor arrays, a first-order integrating unit and a second first-order integrating unit, the second-order integrating unit has two capacitor arrays, the first-order integrating unit is connected to a first positive input terminal of the comparing unit, an upper plate of the first capacitor array is connected to a second positive input terminal of the comparing unit, the first second-order integrating unit is connected to a third positive input terminal of the comparing unit, the second first-order integrating unit is connected to a first negative input terminal of the comparing unit, an upper plate of the second capacitor array is connected to a second negative input terminal of the comparing unit, and the second-order integrating unit is connected to a third negative input terminal of the comparing unit, further comprising: the positive input end of the first compensation unit is respectively connected with a first integration module and a second integration module in the first-order integration unit, the positive output end of the first compensation unit is respectively connected with a first integration module and a second integration module in the first-order integration unit, the negative input end of the first compensation unit is respectively connected with a first integration module and a second integration module in the second first-order integration unit, the negative output end of the first compensation unit is respectively connected with a first integration module and a second integration module in the second first-order integration unit, the positive input end of the second compensation unit is connected with the upper polar plate of the first capacitor array, the positive output end of the second compensation unit is respectively connected with a third integration module and a fourth integration module in the first second-order integration unit, the negative input end of the second compensation unit is connected with the upper polar plate of the second capacitor array, the negative output end of the second compensation unit is respectively connected with the first integration module and the second integration module in the second first-order integration unit, the positive input end of the third compensation unit is respectively connected with a third integration module and a fourth integration module in the first second-order integration unit, the positive output end of the third compensation unit is respectively connected with a third integration module and a fourth integration module in the first second-order integration unit, the negative input end of the third compensation unit is respectively connected with a third integration module and a fourth integration module in the second-order integration unit, and the negative output end of the third compensation unit is respectively connected with a third integration module and a fourth integration module in the second-order integration unit.
15. The analog-to-digital converter of claim 14, wherein the first compensation unit, the second compensation unit, and the third compensation unit each comprise: the circuit comprises a first operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein one end of the first resistor is a positive signal input end, the other end of the first resistor is connected with the positive input end of the first operational amplifier and is provided with a first node, one end of the second resistor is connected with the first node, the other end of the second resistor is respectively connected with the positive output end of the first operational amplifier and is a positive signal output end, one end of the third resistor is a negative signal input end, the other end of the third resistor is connected with the negative input end of the first operational amplifier and is provided with a second node, one end of the fourth resistor is connected with the second node, and the other end of the fourth resistor is respectively connected with the negative output end of the first operational amplifier and is a negative signal output end.
16. The analog-to-digital converter of claim 1, wherein the first integration module, the second integration module, the third integration module, and the fourth integration module are each capacitors.
17. The analog-to-digital converter of claim 16, wherein the capacitance of the first integration module, the capacitance of the second integration module, the capacitance of the third integration module, and the capacitance of the fourth integration module are each the capacitance of the capacitor array.
18. A processor comprising an analog-to-digital converter according to any of claims 1-17.
19. An electronic device comprising an analog-to-digital converter according to any of claims 1-17 or a processor according to claim 18.
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