CN114172512A - Multi-channel oversampling noise shaping successive approximation type analog-digital converter and conversion method - Google Patents

Abstract

The application discloses a multi-channel oversampling noise shaping successive approximation type analog-to-digital converter and a conversion method, and the converter comprises a sampling switch group, a multi-stage integrator and a comparator, wherein the sampling switch group is connected with an input analog signal one by one correspondingly, the multi-stage integrator is connected with the sampling node, and a feedback circuit for noise shaping successive approximation is arranged between the output end of the comparator and the sampling node; the Sar ADC and the operational amplifier are multiplexed, the circuit complexity and the area are reduced by k times, the cost is reduced, the consistency of performance among multiple channels is better by using the same capacitor array, the operational amplifier, the comparator and the multiple channels, the consistency of the performance of a multi-channel sampling system is ensured, the characteristics of low power consumption and high performance are achieved, and a plurality of application scenes are met.

Description

Multi-channel oversampling noise shaping successive approximation type analog-digital converter and conversion method

Technical Field

The invention relates to the technical field of analog circuits, in particular to an analog-to-digital converter, and particularly relates to a multi-channel oversampling noise shaping successive approximation type analog-to-digital converter and a conversion method.

Background

An analog-to-digital converter, or ADC for short, generally refers to an electronic component that converts an analog signal into a digital signal. A typical analog-to-digital converter converts an input voltage signal into an output digital signal. Since digital signals do not have practical significance per se, only one relative magnitude is represented. Therefore, any analog-to-digital converter needs a reference analog quantity as a conversion standard, and a common reference standard is the maximum convertible signal size. Application scenarios such as multi-signal acquisition, measurement, monitoring and the like require a multi-channel analog-to-digital converter (ADC). The multichannel ADC can be implemented by a single chip scheme, or can measure signals by multiple chips. A single chip multi-channel scheme is generally the preferred choice in terms of cost and performance consistency. Conventional high-precision ADCs typically employ a delta-sigma architecture. The architecture is an oversampling architecture ADC, and multiple active integrators are generally used to implement noise-shaping (noise-shaping), so as to effectively suppress quantization noise power within a signal bandwidth. Integrators have a memory effect and cannot be used directly for multiplexing, i.e. one ADC is required for each signal channel. While the successive approximation type (SAR) ADC is a Nyquist ADC whose output codeword is only related to the current conversion result. The framework can be conveniently used for multiplexing, and can be used for periodically switching among a plurality of channels to complete the acquisition task of multiple signals. However, the architecture has the disadvantage of being limited by the digital-to-analog converter (DAC) matching accuracy, which is typically limited to 10 to 12 bits in effective accuracy.

A Noise-Shaping progressive-successive-approximation (Noise-Shaping SAR) analog-to-digital converter (ADC) is an emerging ADC architecture with low power consumption and high precision. The hybrid architecture combines the respective advantages of two ADCs in a balanced manner: the low power consumption characteristic of the charge redistribution SAR ADC and the high precision characteristic of the noise shaping. Through the quantization of the multi-bit SAR ADC, a part of signal-to-noise ratio is obtained in a linear mode; this reduces the noise shaping requirements and thus avoids the need for higher loop filter orders and/or higher oversampling ratios as required by conventional delta-sigma ADCs. By reducing the number of integrators used and the operating frequency of the circuit, the architecture can achieve the advantages of higher performance and lower power consumption. However, the architecture has a memory effect inside the circuit due to the integrator, and is also not a nyquist property, so that the architecture cannot be directly used for a multiplexing scene.

Disclosure of Invention

In order to solve the problems in the prior art mentioned in the background art, the application provides a multi-channel oversampling noise shaping successive approximation type analog-to-digital converter and a conversion method, which are used for reducing the complexity of the whole circuit of a multi-channel ADC, reducing the circuit area and improving the accuracy and consistency of signal conversion.

In order to achieve the purpose, the technical scheme adopted by the application is as follows:

the multi-channel oversampling noise shaping successive approximation type analog-to-digital converter comprises a sampling switch group, a multi-stage integrator and a comparator, wherein the sampling switch group is connected with an input analog signal one by one correspondingly, the multi-stage integrator is connected with the sampling node, and a feedback circuit for noise shaping successive approximation is arranged between the output end of the comparator and the sampling node;

the successive approximation feedback circuit comprises a digital circuit control unit, a mismatch error shaping unit, a feedback switch group and a capacitor array, wherein the digital circuit control unit comprises an SAR logic module and a time sequence generation module which are used for controlling the sampling switch group, the feedback switch group, the mismatch error shaping unit, the multistage integrator and the comparator; the mismatch error shaping unit comprises DWA modules and MES modules, and a multichannel multiplexing controller (MUX) used for controlling and selecting any DWAk in the DWA modules and any MESk in the MES modules; the capacitor array is connected with a reference voltage through the feedback switch group, and the reference voltage is composed of Vrefp, Vcm and Vrefn, wherein Vrefp + Vrefn =2 Vcm. It should be noted that the setting is only one of the options, and those skilled in the art can freely define the setting without affecting the technical implementation as long as the requirement of performing successive progressive comparison is met, and the setting of the reference voltage should not be understood as a limitation in the quantization process of the present application.

As a preferred arrangement mode of the present application, the capacitor array includes a first capacitor array and a second capacitor array, the feedback switch group includes a first feedback switch group and a second feedback switch group, and the first capacitor array is connected to the multi-channel multiplexing controller MUX through the first feedback switch group and receives a feedback signal of the MES module; and the second capacitor array is connected with the multichannel multiplexing controller MUX through a second feedback switch group and receives the feedback signal of the DWA module.

Still further preferably, the MES module further includes a first register for storing a connection mode between the first feedback switch group and the first capacitor array, where any channel needs to be configured.

And the DWA module also comprises a second register used for storing the connection mode of a second feedback switch group which needs to be configured for any channel and a second capacitor array.

In a preferred arrangement, the first capacitor array is a binary capacitor array, and the second capacitor array is an equal-capacity capacitor unit array.

As an arrangement manner that can be adopted by the present application, the multistage integrator is composed of a first integrator and a second integrator, the first integrator includes a first operational amplifier Amp1 and an integrating capacitor Cint1k, the negative electrodes of the integrating capacitors Cint1k are respectively communicated with the sampling nodes through a first path provided with a switch Phak and a second path composed of a switch Phs1 and a switch Phs1k which are arranged in series, and are communicated with a + input pin of the first operational amplifier Amp1 through a switch Phs1k, a-input pin of the first operational amplifier Amp1 is connected with Vcm, and the output end of the first operational amplifier Amp1 is communicated with the positive electrode of the integrating capacitor Cint1k through another independent switch Phs1 k;

the second integrator comprises a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is communicated with the positive electrode of the integrating capacitor Cint1k through another switch Phak, is communicated with the output end of the first operational amplifier Amp1 through a switch Phs2k and a switch Phs2 which are connected in series, is also communicated with the + input pin of the second operational amplifier Amp2 through the switch Phs2k, the-input pin of the second operational amplifier Amp2 is connected with Vcm, the output end of the second operational amplifier Amp2 is connected with the inverting input end of the comparator through another switch Phak, and the non-inverting input end of the comparator is connected with Vcm. It should be noted that the above two-stage integrator configuration is only one optional preferred configuration scheme of the multiple-stage integrator, and according to the above disclosed technical content and the given technical teaching of the multiple-stage integrator configuration, a person skilled in the art may optionally select a configuration architecture of a three-stage integrator or a four-stage integrator according to actual requirements and processing residual capacitances on the capacitance array after each sampling to reduce the overall error.

In order to better implement analog-to-digital conversion, the present application further provides an available multichannel analog-to-digital conversion method, which is specifically implemented by using the above multichannel oversampling noise shaping successive approximation analog-to-digital converter, and specifically includes:

STP100, sampling step: during first sampling, the feedback switch group connects the lower electrode plate of the capacitor array to a Vcm point; the digital circuit control unit sends a sampling signal to trigger any one of sampling switches connected with a to-be-sampled analog input signal Vink to be switched on, and the analog signal enters an analog-to-digital converter;

STP200, successive progression steps: each gradual progression comprises the following steps:

STP210, step of comparison: comparing the voltage V of the capacitor array by a comparator_DACThe sum of the first integrator output voltage Vout1 and the second integrator output voltage Vout2 and the common-mode voltage Vcm, and output a result 1 or 0;

STP220, step of feedback: the result of the comparator 500 is fed back to an SAR logic module in the digital circuit control unit 600, and simultaneously, the result is respectively input into DWA1 and MES1 for noise shaping, and the SAR logic module changes the state that the lower electrode plates of the capacitor array are all connected to a Vcm point by a feedback switch group according to an output result 1 or 0, so that the value input into the comparator 500 after the Vink +1 performs the sampling is closer to the common-mode voltage Vcm;

STP230, step of integration: after repeating the steps STP100-STP200 for multiple times, the first integrator integrates the residues on the capacitor array and stores the residues on the integrating capacitor Cint1k, and the second integrator integrates the charges on the sampling capacitor CS2 and stores the charges on the integrating capacitor Cint2 k;

and STP300, step of outputting: after the above steps STP100 to STP200 are cycled within the conversion period T set by the timing generation module, the values of the inverting input terminal and the non-inverting input terminal of the comparator tend to be equal and the final output is obtained, wherein k e [1,2,3 … … k ], and the period T is set by the timing generation module.

Has the advantages that:

1. the Sar ADC and the operational amplifier are multiplexed, the circuit complexity and the area are reduced by k times, and the cost is reduced.

2. The same capacitor array, operational amplifier and comparator are used, the performance consistency among multiple channels is good, and the consistency of the performance of a multi-channel sampling system is guaranteed.

3. The method has the characteristics of low power consumption and high performance, and meets a plurality of application scenes.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is an overall framework diagram of the present invention.

Fig. 2 is a circuit diagram of fig. 1.

FIG. 3 is a schematic diagram of the operation of a single conversion (shown as the kth channel).

Fig. 4 is a timing diagram of the present invention.

In the figure: 100-a sampling switch group; 200-a sampling node; 300-a first integrator; 400-a second integrator; 500-a comparator; 600-a digital circuit control unit; 700-mismatch error shaping unit; 800-1-a first feedback switch group; 800-2-a second feedback switch group; 900-1-a first capacitor array; 900-2-second capacitor array.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it should be noted that the terms "first", "second", and the like in the description of the present application are used for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Example 1:

referring to fig. 1 and 2, the multi-channel oversampling noise-shaping successive approximation analog-to-digital converter includes a sampling switch group 100 connected to an input analog signal one by one, a multi-stage integrator connected through a sampling node 200, and a comparator 500, where a feedback circuit for noise-shaping successive approximation is provided between an output end of the comparator 500 and the sampling node 200;

the successive approximation feedback circuit comprises a digital circuit control unit 600, a mismatch error shaping unit 700, a feedback switch group and a capacitor array, wherein the digital circuit control unit 600 comprises an SAR logic module and a time sequence generation module which are used for controlling the sampling switch group 100, the feedback switch group, the mismatch error shaping unit 700, the multistage integrator and the comparator 500; the mismatch error shaping unit 700 comprises a DWA module and an MES module, and a multichannel multiplexing controller MUX for controlling and selecting any one DWAk of the DWA module and any one MESk of the MES module; the capacitor array is connected with a reference voltage through the feedback switch group, and the reference voltage is composed of Vrefp, Vcm and Vrefn, wherein Vrefp + Vrefn =2 Vcm.

The working principle is as follows:

as shown in fig. 2, for convenience of illustration, the circuit diagram shown in this embodiment is a single-ended implementation, and the actual circuit is a differential circuit; in addition, under the teaching and teaching of the present embodiment, the architecture disclosed in the present embodiment can also be extended to more integrators, for example, a three-stage or four-stage integrator is also a conventional transformation or selection, which is not described herein. When the whole analog-to-digital converter ADC is used for sampling, voltages on a capacitor array of a CDAC (capacitive DAC) and a multi-stage integrator are accumulated and input into the comparator 500 for comparison, the compared values are subjected to noise shaping through the DWA module and the MES module respectively, the successive progressive input into the comparator 500 is realized through overturning the capacitor array for cycle comparison, and finally Dout is output, so that the purpose of accurate conversion is achieved.

Has the advantages that:

compared with the existing delta-sigma architecture ADC and Nyquist ADC, the analog-to-digital converter provided by the embodiment can multiplex the whole digital circuit control unit 600 and the CDAC, so that the circuit complexity is obviously reduced, the circuit area can be reduced by K times (where K is the number of successive progressions) on the premise of multiplexing the capacitor array of the CDAC, and the manufacturing investment cost on the premise of not influencing the actual signal conversion precision is greatly reduced. The multi-channel multiplexing controller MUX control employed in this embodiment has four MUX modules, as shown in FIG. 2, MUX1a and MUX1b for controlling the DWA module (Data-Weighted Averaging), and MUX2a and MUX2b for controlling the MES module (Mismatch Error sharing). In this embodiment, the MESk indicates k sets of MES (MES 1, MES2, MES3, MES4 … … MESk), and DWAk indicates k sets of DWA (DWA 1, DWA2, DWA3, DWA4 … … DWAk), so that when multiplexing the same capacitor array, multiple channels can ensure the consistency of performance among the multiple channels, and simultaneously can ensure the consistency of performance of a sampling system.

Example 2:

as shown in fig. 1 to fig. 4 in the specification, this embodiment further refines the circuit structure based on the foregoing embodiment 1, and specifically includes the following steps: the capacitor array comprises a first capacitor array 900-1 and a second capacitor array 900-2, the feedback switch group comprises a first feedback switch group 800-1 and a second feedback switch group 800-2, and the first capacitor array 900-1 is connected with the multichannel multiplexing controller MUX through the first feedback switch group 800-1 and receives a feedback signal of the MES module; the second capacitor array 900-2 is connected to the multichannel multiplexing controller MUX through the second feedback switch group 800-2 and receives the feedback signal of the DWA module. The MES module further comprises a first register for storing the connection mode of the first feedback switch group 800-1 and the first capacitor array 900-1 for any channel configuration.

And the DWA module also comprises a second register used for storing the connection mode of the second feedback switch group 800-2 and the second capacitor array 900-2 which are needed to be configured by any channel. The first capacitor array 900-1 is a binary capacitor array, and the second capacitor array 900-2 is an array of equal-capacitance capacitor cells.

As an arrangement manner that can be adopted by the present application, the multistage integrator is composed of a first integrator 300 and a second integrator 400, the first integrator 300 includes a first operational amplifier Amp1 and an integrating capacitor Cint1k, the negative electrodes of the integrating capacitors Cint1k are respectively communicated with the sampling node 200 through a first path provided with a switch Phak and a second path composed of a switch Phs1 and a switch Phs1k which are arranged in series, and are communicated with the + input pin of the first operational amplifier Amp1 through a switch Phs1k, the-input pin of the first operational amplifier Amp1 is connected with Vcm, and the output end of the first operational amplifier Amp1 is communicated with the positive electrode of the integrating capacitor Cint1k through another independent switch Phs1 k;

the second integrator 400 comprises a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is communicated with the positive electrode of the integrating capacitor Cint1k through another switch Phak, is communicated with the output end of the first operational amplifier Amp1 through a switch Phs2k and a switch Phs2 which are connected in series, is further communicated with the + input pin of the second operational amplifier Amp2 through the switch Phs2k, the-input pin of the second operational amplifier Amp2 is connected with Vcm, the output end of the second operational amplifier Amp2 is connected with the inverting input end of the comparator 500 through another switch Phak, and the non-inverting input end of the comparator 500 is connected with Vcm. It should be noted that the above two-stage integrator configuration is only one optional preferred configuration scheme of the multiple-stage integrator, and according to the above disclosed technical content and the given technical teaching of the multiple-stage integrator configuration, a person skilled in the art may optionally select a configuration architecture of a three-stage integrator or a four-stage integrator according to actual requirements and processing residual capacitances on the capacitance array after each sampling to reduce the overall error.

The most significant advantage of adopting the above structure is that the plurality of channels can multiplex the CDAC, the first operational amplifier Amp1, the second operational amplifier Amp2, the comparator 500, the SAR logic module and the timing generation module, and the second feedback switch group 800-2 for controlling the inversion of the second capacitor array 900-2, and the first feedback switch group 800-1 for controlling the first capacitor array 900-1, compared with the existing multiple ADC architecture arrangements, the structure can realize sequential or periodic conversion in the conversion process of the multi-channel analog signal, and in the conversion process of a certain channel signal, the capacitor array with the most occupied area is structurally shared, so that the consistency of conversion performance can be maintained among a plurality of different channels, and different errors caused by different capacitor arrays are avoided, so that the conversion result among the multi-channel signals adopts the same architecture, but there is significant variability due to the difference in the capacitor arrays; furthermore, the performance consistency of the multi-channel sampling system can be ensured.

As shown in fig. 4, in the Clks1 phase (in particular, Vin1 is an analog signal input), the whole ADC is sampled, then the phase switch Pha1 is turned on, the voltage across the Cint11 and Cint21 integrating capacitors and the sampled voltage across the capacitor array are summed, and since phase Pha1 is in the on state, the voltage is directly input to the inverting input terminal of the comparator 500. The comparator 500 compares the sampling voltage input by the inverting input terminal with the common mode voltage Vcm at the forward input terminal at this time, and outputs the comparison result (1 or 0) at this time, so that the DWA1 controls the second feedback switch group 800-2 to disconnect the common mode voltage Vcm, and turn on the reference voltage Vrefp or Vrefn, thereby implementing the turnover of the second capacitor array 900-2; similarly, the first feedback switch group 800-1 is controlled by the MES1 module to disconnect the common mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, so as to turn over the first capacitor array 900-1, and finish a quantization after finishing a capacitor turning over, and the above steps are repeated, so that the turning over of the capacitor array realizes successive comparison of the successively progressive input comparator 500, and thus after completing the conversion with each successive transition, a final output Dout is generated after finishing the quantization of the (i + j) bit. It is worth to be noted that, in phase Phs1 and Phs2, the capacitor arrays (specifically, the residual capacitors of the first capacitor array 900-1 and the second capacitor array 900-2) are integrated in phase Phs11 at Cint11, in phase Phs21 at Cint21, in the same way, in phase Phs1k at Cint1k, in phase Phs2k at Cint2k, so that the residual of different channels can be stored on different capacitors to form noise shaping of each channel, after the integration is completed, the voltages of the residual of the capacitor arrays on the corresponding integrating capacitors are accumulated through capacitive coupling, so as to be ready for the next noise shaping inspiration, further, under the teaching of the above principle, only one operational amplifier (here, the first operational amplifier Amp1 and/or the second operational amplifier Amp2 are respectively) is shared, as shown in fig. 2, in the same way, in the Phak phase, the voltages on the CInt1k and Cint2k integrating capacitors and the sampled voltages on the capacitor arrays (specifically first capacitor array 900-1 and second capacitor array 900-2) are summed and input to comparator 500. And meanwhile, a corresponding DWAk module and a corresponding MESk module are selected corresponding to the k channel, and each channel is operated circularly, so that high-precision quantification of each channel signal can be completed.

Although according to the above-mentioned structure of sampling, integration, comparison and noise shaping, in order to implement high-precision quantization of the output signal, it is necessary to arrange separate DWAk (specifically including DWA1, DWA2, DWA3, DWA4 … … DWAk) and MESk module (specifically including MES1, MES2, MES3, MES4 … … MESk) for each channel, respectively, so as to avoid generating more noise/error due to error mixing between multiple channels caused by residual capacitance when performing multi-channel conversion, thereby reducing quantization precision. In order to realize the premise of high-precision quantization output between multi-channel signal conversion, the DWA module and the MES module cannot be multiplexed, and only in this way, the in-band mismatch error can be restrained as much as possible, so that high linearity is realized. Because the logic circuits are simple logic circuits, especially when DWA digits are low and MES digits are high, the logic circuits can be used for realizing the DWA and the MES, even if DWA modules and MES modules are not multiplexed, the overhead is not high, and compared with the technical effect that multichannel accurate quantization output can be met, the added DWA modules and MES modules have negligible cost. In this sense, the technical effect obtained by the improvement of its architecture is significant.

Example 3:

in order to better implement analog-to-digital conversion, this embodiment provides an available multichannel analog-to-digital conversion method, which is specifically implemented by using the above multichannel oversampling noise shaping successive approximation analog-to-digital converter, and specifically includes:

STP100, sampling step: during first sampling, the feedback switch group connects the lower electrode plate of the capacitor array to a Vcm point; the digital circuit control unit 600 sends a sampling signal to trigger any one of the sampling switch groups to be connected with a sampling switch Clksk of an analog input signal Vink to be sampled to be conducted, and the analog signal enters an analog-to-digital converter;

STP200, successive progression steps: each gradual progression comprises the following steps:

STP210, step of comparison: the voltage V of the capacitor array is compared by a comparator 500_DACThe sum of the output voltage Vout1 of the first integrator 300 and the output voltage Vout2 of the second integrator 400 and the common-mode voltage Vcm, and output the result 1 or 0;

STP220, step of feedback: the result of the comparator 500 is fed back to an SAR logic module in the digital circuit control unit 600, and simultaneously, the result is respectively input into DWA1 and MES1 for noise shaping, and the SAR logic module changes the state that the lower electrode plates of the capacitor array are all connected to a Vcm point by a feedback switch group according to an output result 1 or 0, so that the value input into the comparator 500 after the Vink +1 performs the sampling is closer to the common-mode voltage Vcm;

STP230, step of integration: after repeating the steps STP100-STP200 for multiple times, the first integrator (300) integrates the residues on the capacitor array and stores the residues on the integrating capacitor Cint1k, and the second integrator (400) integrates the charges on the sampling capacitor CS2 and stores the charges on the integrating capacitor Cint2 k;

and STP300, step of outputting: after the above steps STP100 to STP200 are cycled within the transition period T set by the timing generation module, the values of the inverting input terminal and the non-inverting input terminal of the comparator (500) tend to be equal to each other and the final output is obtained, wherein k e [1,2,3 … … k ].

Referring to fig. 3 of the specification, taking k =1 as an example, the analog signal input terminal Vin1 provides an analog signal, the switches Clks1 are turned on, and the sampling state is entered, where Vtotal = V is a voltage at the inverting input terminal of the comparator 500_DAC+ Vout1+ Vout2 compares with the common mode voltage Vcm at the positive input terminal and outputs the comparison result; at this time, a first noise shaping and progressive step is carried out, the DWA1 used by a channel corresponding to the Vin1 controls the second feedback switch group 800-2 to cut off the common-mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, so that the second capacitor array 900-2 is turned over, and the specific configuration rule of turning over is determined according to the configuration stored in the second register; similarly, the MES1 module controls the first feedback switch group 800-1 to turn off the common mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, so as to flip the first capacitor array 900-1, where a specific configuration rule of the flipping is determined according to a configuration stored in the first register; and completing one-time quantization after one-time capacitance overturning. The Phs1 and Phs2 phases now integrate the residual capacitances on the capacitor arrays (specifically first capacitor array 900-1 and second capacitor array 900-2. it is worth noting that the phase Phs11 isBits are integrated over Cint 11; integration over Phs21 phase, Cint21, and similarly over Cint1k at Phs1k phase; the Phs2k phase is integrated over Cint2k, so that the residuals of different channels can be stored on different capacitors to form noise shaping for each channel. And accumulating the voltage of the residual error on the capacitor array on the corresponding integrating capacitor through capacitive coupling after the integration is finished, thereby preparing for next noise shaping. And repeatedly circulating the steps, and turning the capacitor array to realize successive comparison of the successively progressive input comparator 500, so that after the conversion is completed with each successive approximation, the final output Dout is generated after the quantization of the (i + j) bits is completed. It is worth mentioning that: the parameters of the sampling capacitor CS2 should be set/selected according to actual circuit requirements, especially the CDAC signal-to-noise ratio, and those skilled in the art can flexibly select the sampling capacitor CS2 in the prior art without departing from the present invention and simultaneously considering gradual and accurate quantization and satisfying the requirement of reducing quantization noise, and those skilled in the art may have various alternatives based on the disclosed analog-to-digital converter architecture according to the teachings of the present application, which are not described herein.

After one channel signal conversion is completed, the switch Clks1 is switched off, the switch Clks2 is switched on, the process is repeated to carry out the same conversion on the analog signal of the input signal Vin2, and the phase of Phs12 is integrated on Cint 12; integration over the Phs22 phase, Cint22, completes the progressive progression operation described above.

Similarly, the phase at Phs1k is integrated over Cint1 k; the phase Phs2K is integrated on Cint2K until the analog signals of the K channels are all subjected to accurate quantization conversion output sequentially or periodically. Thus, multi-channel analog signal conversion is realized, CDAC and SAR logic modules are fully shared, and the significant technical effect obtained by the CDAC and SAR logic modules is as described in the above embodiment and is not described in detail herein.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (7)

1. Multichannel oversampling noise shaping successive approximation type analog-to-digital converter, its characterized in that: the noise shaping circuit comprises a sampling switch group (100) which is correspondingly connected with an input analog signal one by one, a multi-stage integrator which is connected through a sampling node (200), and a comparator (500), wherein a feedback circuit for noise shaping gradual progress is arranged between the output end of the comparator (500) and the sampling node (200);

the successive approximation feedback circuit comprises a digital circuit control unit (600), a mismatch error shaping unit (700), a feedback switch group and a capacitor array, wherein the digital circuit control unit (600) comprises a SAR logic module and a time sequence generation module which are used for controlling the sampling switch group (100), the feedback switch group, the mismatch error shaping unit (700), a multi-stage integrator and a comparator (500); the mismatch error shaping unit (700) comprises DWA modules and MES modules, and a multi-channel multiplexing controller MUX for controlling and selecting any DWAk in the DWA modules and any MESk in the MES modules; the capacitor array is connected with a reference voltage through the feedback switch group, and the reference voltage is composed of Vrefp, Vcm and Vrefn, wherein Vrefp + Vrefn =2 Vcm.

2. The multi-channel oversampling noise-shaping successive approximation analog-to-digital converter of claim 1, wherein: the capacitor array comprises a first capacitor array (900-1) and a second capacitor array (900-2), the feedback switch group comprises a first feedback switch group (800-1) and a second feedback switch group (800-2), and the first capacitor array (900-1) is connected with the multi-channel multiplexing controller MUX through the first feedback switch group (800-1) and receives a feedback signal of the MES module; the second capacitor array (900-2) is connected with the multichannel multiplexing controller MUX through a second feedback switch group (800-2) and receives feedback signals of the DWA module.

3. The multi-channel oversampling noise-shaping successive approximation analog-to-digital converter of claim 2, wherein: the MES module further comprises a first register for storing the connection mode of a first feedback switch group (800-1) and a first capacitor array (900-1) of any channel to be configured.

4. The multi-channel oversampling noise-shaping successive approximation analog-to-digital converter according to claim 2 or 3, wherein: the DWA module also comprises a second register used for storing the connection mode of a second feedback switch group (800-2) which needs to be configured for any channel and a second capacitor array (900-2).

5. The multi-channel oversampling noise-shaping successive approximation analog-to-digital converter of claim 4, wherein: the first capacitor array (900-1) is a binary capacitor array, and the second capacitor array (900-2) is an array of equal-capacity capacitor units.

6. The multi-channel oversampling noise-shaping progressive analog-to-digital converter of claim 5, wherein: the multistage integrator is composed of a first integrator (300) and a second integrator (400), wherein the first integrator (300) comprises a first operational amplifier Amp1 and an integrating capacitor Cint1k, the negative electrodes of the integrating capacitors Cint1k are respectively communicated with the sampling nodes (200) through a first path provided with a switch Phak and a second path composed of a switch Phs1 and a switch Phs1k which are arranged in series, and are communicated with a + input pin of a first operational amplifier Amp1 through a switch Phs1k, an-input pin of the first operational amplifier Amp1 is connected with Vcm, and the output end of the first operational amplifier Amp1 is communicated with the positive electrode of the integrating capacitor Cint1k through another independent switch Phs1 k;

the second integrator (400) comprises a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is communicated with the positive electrode of the integrating capacitor Cint1k through another switch Phak, is communicated with the output end of the first operational amplifier Amp1 through a switch Phs2k and a switch Phs2 which are connected in series, is also communicated with the + input pin of the second operational amplifier Amp2 through the switch Phs2k, the-input pin of the second operational amplifier Amp2 is connected with Vcm, the output end of the second operational amplifier Amp2 is connected with the inverting input end of the comparator (500) through another switch Phak, and the non-inverting input end of the comparator (500) is connected with Vcm.

7. The multichannel analog-to-digital conversion method is characterized in that: the implementation of the multi-channel oversampling noise-shaping successive approximation analog-to-digital converter according to claim 6, specifically comprising:

STP100, sampling step: during first sampling, the feedback switch group connects the lower electrode plate of the capacitor array to a Vcm point; the digital circuit control unit (600) sends a sampling signal to trigger any sampling switch Clksk in the sampling switch group, which is connected with the analog input signal Vink to be sampled, to be conducted, and the analog signal enters the analog-to-digital converter;

STP200, successive progression steps: each gradual progression comprises the following steps:

STP210, step of comparison: comparing the voltage V of the capacitor array by a comparator (500)_DACThe sum of the output voltage Vout1 of the first integrator (300) and the output voltage Vout2 of the second integrator (400) and the common-mode voltage Vcm and outputting the result 1 or 0;

STP220, step of feedback: the result of the comparator (500) is fed back to an SAR logic module in a digital circuit control unit (600), and simultaneously, the result is respectively input into DWA1 and MES1 for noise shaping, and the SAR logic module changes the state that a feedback switch group connects the lower polar plate of a capacitor array to a Vcm point according to an output result 1 or 0, so that the value of the input comparator (500) is closer to a common-mode voltage Vcm after Vin2 performs the sampling;

STP230, step of integration: after repeating the steps STP100-STP200 for multiple times, the first integrator (300) integrates the residues on the capacitor array and stores the residues on the integrating capacitor Cint1k, and the second integrator (400) integrates the charges on the sampling capacitor CS2 and stores the charges on the integrating capacitor Cint2 k;

and STP300, step of outputting: after the above steps STP100 to STP200 are cycled within the transition period T set by the timing generation module, the values of the inverting input terminal and the non-inverting input terminal of the comparator (500) tend to be equal to each other and the final output is obtained, wherein k e [1,2,3 … … k ].

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