CN116366061A - Pipelined successive approximation analog-to-digital converter based on switched load capacitor - Google Patents
Pipelined successive approximation analog-to-digital converter based on switched load capacitor Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a pipeline successive approximation analog-to-digital converter based on a switched load capacitor. According to the invention, the switching load capacitance switching circuit is arranged to control switching by matching with a clock signal, so that the load capacitance in the residual error amplifier is controlled to be switched with the feedback capacitance, the quantization noise of the second-stage sub-analog-digital converter in the previous sampling period is extracted, and the first-order error feedback type noise shaping is realized through the residual error amplifier in the current sampling period, so that the precision influence caused by the unprocessed final-stage quantization noise in the traditional pipelined successive approximation analog-digital converter is reduced; the switching load capacitance switching circuit controls the switching through a clock signal, and compared with a mode of using an active circuit, the quantization noise of the second-stage sub-analog-digital converter is extracted, so that the overall power consumption of the circuit is effectively reduced, and meanwhile, the data conversion speed is improved.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, in particular to a pipeline successive approximation analog-to-digital converter based on a switched load capacitor, which relates to a noise shaping circuit and can be applied to a pipeline converter.
Background
In many application fields, the demand of analog-to-digital converters (ADCs) is increasing, and the analog-to-digital converters are widely applied to wireless charging, internet of things, automobile electronics, intelligent home and other applications, and bridge construction is realized for realizing various electrical functions by completing conversion from analog quantity to digital quantity. Analog-to-digital converters can be classified by type into Flash analog-to-digital converters, successive Approximation (SAR) analog-to-digital converters, pipelined (Pipeline) analog-to-digital converters, sigma-delta analog-to-digital converters. At present, in the application field of high-speed electrical equipment, a pipeline analog-to-digital converter with high speed and high power consumption is often combined with a successive approximation type analog-to-digital converter with low power consumption and low speed, and the pipeline successive approximation type analog-to-digital converter (Pipelined-SAR) combines the advantages of two basic structures.
The conventional Pipelined-SAR structure is usually formed by cascading multi-stage sub-ADCs through residual amplifiers, and compared with a serial successive approximation analog-to-digital converter, the Pipelined parallel structure can reduce the clock period for completing one-time data quantization, so that the conversion speed is improved. Each stage of sub-ADC architecture adopts a successive approximation analog-to-digital converter of a single comparator to replace the traditional multi-comparator Flash structure, and the overall power consumption can be greatly reduced by reducing the number of comparators. Meanwhile, a capacitor array in the successive approximation analog-to-digital converter can replace a sample hold (S/H) circuit in a traditional pipeline, so that static power consumption is reduced, and meanwhile, the introduction of an active circuit is avoided, so that the performance under various process angles, power supply voltage and temperature (PVT) is relatively constant.
However, in terms of accuracy, the Pipelined-SAR is affected not only by the residual amplifier gain error in the pipeline, but also by the quantization result from comparator offset in the SAR. The integrated circuit center of Australian university improves accuracy by applying the oversampling and noise shaping technique of Sigma-delta analog-to-digital converter to the Pipelined-SAR to achieve noise suppression. The disadvantage is that additional active circuitry is introduced, increasing power consumption while also reducing speed.
Disclosure of Invention
In order to solve the problems or the shortcomings, the invention provides a Pipelined successive approximation analog-to-digital converter based on a switching load capacitor, which utilizes sequential logic to control the switching of the load capacitor and an amplifier feedback capacitor, and sends a post-stage quantization noise signal stored on a previous period load capacitor back to an operational amplifier through the feedback capacitor after switching to form first-order noise shaping, so that the influence of second-stage quantization noise on the precision of the Pipelined-SAR analog-to-digital converter is inhibited, and the effective digit is improved. The switching load capacitor avoids using an active circuit to extract noise signals, has the characteristics of low power consumption, high speed and the like, realizes high precision, and effectively solves the problems existing in the prior art.
A pipeline successive approximation analog-to-digital converter based on a switched load capacitor adopts a fully differential structure, and comprises a first-stage sub-analog-to-digital converter, a residual amplifier, a second-stage sub-analog-to-digital converter, a digital code value output circuit and a switched load capacitor switching circuit as shown in figure 1.
The first-stage sub analog-digital converter samples an input analog signal, converts the analog signal into a digital signal, and consists of a capacitor array type digital-analog converter, a dynamic comparator and a successive approximation logic circuit.
The first-stage sub analog-digital converter is provided with two output ends, the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit, and the residual signal of the upper polar plate of the capacitor array type digital-analog converter flows into the residual amplifier through the switch S2.
The working principle is described below with reference to fig. 1 and 2: the first-stage sub-analog-digital converter firstly enters a sampling stage, an input signal Vin is sampled through a switch S1, at the moment, S1 is closed, and S2 is opened; in the quantization process, namely in the process of converting an analog signal into a digital signal by a first-stage sub-analog-digital converter, at the moment, a switch S1 is opened, a switch S2 is opened, an analog signal output by a capacitor array type digital-analog converter is sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signal from the capacitor array type digital-analog converter, the analog signal starts to be compared and output a high-level or low-level analog signal, the output analog signal flows to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-analog converter to switch so as to convert the next data; after quantization is completed, namely the first-stage sub-analog-digital converter completes the conversion process of an analog signal to a digital signal, when residual voltage of the first-stage sub-analog-digital converter begins to be amplified, the switch S1 is opened, the switch S2 is closed, the upper polar plate of the capacitor array type digital-analog converter stores the residual signal of the current period, and the output signal is received by the input end of the residual amplifier through the switch S2.
The residual amplifier adopts a closed loop switch capacitor structure and consists of an operational amplifier, a feedback capacitor and a load capacitor, and the gain of the residual amplifier is the ratio of the total capacitance of a capacitor array in the first-stage sub analog-digital converter to the feedback capacitor; the negative input end of the operational amplifier is connected with the upper polar plate of the first-stage sub analog-digital converter through a switch S2, the positive input end of the operational amplifier is connected with the ground, and the output end of the operational amplifier is connected with the upper polar plate of the second-stage sub analog-digital converter through a switch S3; capacitor C f1 A capacitor C connected across the negative input and output of the operational amplifier f2 One end is grounded, and the other end is connected with the output end of the operational amplifier. Capacitor C f1 And C f2 The switching circuit of the switching load capacitor controls the opening and closing of the switch by utilizing time sequence, thereby realizing C in the residual amplifier f1 And C f2 As a swap of the load capacitance and the feedback capacitance, a swap load capacitance switching circuit is provided on the feedback path and the output of the residual amplifier.
When the switch S2 is closed, the input signal of the operational amplifier is the residual signal stored in the upper polar plate after the quantization of the first-stage sub analog-digital converter is completed, and the residual signal is amplified to the reference voltage of the second-stage sub analog-digital converter.
When the switch S3 is closed, the output signal of the operational amplifier is sampled by the second-stage sub-analog-to-digital converter for the second-stage sub-analog-to-digital converter to start conversion of the analog signal to the digital signal.
The second-stage sub-analog-digital converter consists of a capacitor array type digital-analog converter, a dynamic comparator and a successive approximation logic circuit; the input end of the second-stage sub-analog-digital converter samples residual voltage of the first-stage sub-analog-digital converter amplified by the residual amplifier; the output end of the second-stage sub-A/D converter is only one, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit.
The working principle is described below with reference to fig. 1 and 2: the second-stage sub-analog-digital converter firstly enters a quantization stage, at the moment, a switch S3 is opened, and the conversion process from an analog signal to a digital signal is started; the analog signals output by the capacitor array type digital-to-analog converter are sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signals from the capacitor array type digital-to-analog converter, the analog signals begin to be compared and output high-level or low-level analog signals, the output signals flow to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-to-analog converter to switch so as to convert the next data; after the quantization process is finished, at this time, the switch S3 is closed, and a sampling stage is entered, and the output signal amplified by the residual amplifier is sampled.
The switching load capacitance switching circuit is arranged on a feedback path and an output end of the residual amplifier, and the switching load capacitance and the feedback capacitance of the residual amplifier are exchanged by utilizing the opening and closing of the time sequence control switch. The basic principle is that the quantization noise of the second-stage sub-analog-digital converter of the previous period stored on the load capacitor is transmitted to the input end of the residual amplifier for processing by the upper polar plate of the feedback capacitor through the exchange of the capacitor positions, so that the first-order error feedback type noise shaping is realized, and finally, a new signal processed by the noise transfer function is collected on the load capacitor of the current period, thereby improving the precision of the whole circuit.
Referring to fig. 3-6, the switching load capacitance switching circuit includes two sampling periods, C, within a complete cycle f1 And C f2 The working states of the capacitors differ by one sampling period according to the floating-switching to the load capacitor position at the feedback capacitor and sampling the output signal of the residual amplifier together with the second-stage sub-A/D converterThe load capacitor operates in a sequence of switching to the feedback capacitor position, which is involved in the quantization process of the second-stage sub-analog-to-digital converter.
Referring to fig. 2, during one sampling period, the switched load capacitance switching circuit switches the control capacitance C f1 、C f2 Exchange once, after two sampling periods, capacitor C f1 、C f2 Returning to the initial position; according to the basic principle of the pipeline successive approximation analog-to-digital converter structure, the first-stage sub analog-to-digital converter works according to the sequence of sampling/holding-quantizing-residual amplifier amplifying residual voltage, and the second-stage sub analog-to-digital converter does not need to sample an input signal, but samples an output signal of the residual amplifier, and only works according to the sequence of quantizing-sampling/holding;
the input end of the digital code value output circuit receives digital signals output by the first-stage sub-analog-digital converter and the second-stage sub-analog-digital converter, an inter-stage redundancy structure is adopted, code value integration is carried out through digital logic, a 10-bit digital code value is finally output, the actual effective digit is improved to 12.55 bits as shown in fig. 8, and the effectiveness of the invention in improving the precision of the pipelined successive approximation analog-digital converter is also proved.
Further, as a preferable scheme, the sampling switch S1 of the first-stage sub-analog-digital converter is a gate voltage bootstrap circuit (Bootstrapped Switch), so that the influence of an input signal on the on-resistance of the switch is reduced, and the linearity of the sampling signal is improved; meanwhile, the capacitor array type digital-to-analog converter adopts a lower polar plate for sampling, so that the influence of charge injection in a switch channel on sampling signals is reduced when a control switch is opened; considering that the method is applied to the high-speed field, the capacitor array weight of the first-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the dynamic comparator of the first-stage sub analog-digital converter is added with a current injection circuit based on a charge pump structure, so that offset self-correction of the comparator is carried out, and the error of offset of the dynamic comparator of the first-stage sub analog-digital converter on signal conversion from analog quantity to digital quantity is reduced; the successive approximation logic circuit of the first-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization can be reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
Further, as a preferable scheme, an operational amplifier in the residual amplifier adopts a folded cascode structure to provide an output signal with a large swing range; meanwhile, an operational amplifier in the residual amplifier further improves open loop Gain by adopting a Gain-Boost technology (Gain-Boost), so that the influence of non-ideal factors on closed loop Gain precision is reduced.
Further, as a preferable scheme, the capacitor array type digital-to-analog converter of the second-stage sub-analog-to-digital converter adopts upper polar plate sampling, compared with lower polar plate sampling, the influence of parasitic capacitance at the lower polar plate on the capacitance weight can be reduced, and the quantization precision is improved. Considering that the method is applied to the high-speed field, the capacitor array weight of the second-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the resolution requirement of the dynamic comparator of the second-stage sub-analog-digital converter is higher, so that the speed of the dynamic comparator for carrying out one-time analog signal comparison is improved by adopting a structure with a pre-amplifier; the successive approximation logic circuit of the second-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization is reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
Further, as shown in fig. 3, a switched load capacitance switching circuit is preferably arranged between the residual amplifier and the second-stage sub-analog-digital converter, and the switches Sw1-Sw8 and S3 are connected with the capacitance C with equal magnitude f1 、C f2 Constructing; wherein the switches Sw1-Sw4 and the capacitor C f1 Connected to Sw5-Sw8 and capacitor C f2 Connected with the switch S3 and connected with the capacitor C f1 Upper electrode plate of (C) and capacitor C f2 Is arranged on the upper polar plate of the upper polar plate. The timing sequence of the switches Sw1-Sw8, as shown in FIG. 8, finally realizes the effect of suppressing the quantization noise of the second-stage sub-analog-digital converter, and improves the overall accuracy of the circuit.
In summary, the load capacitor switching circuit controls the load capacitor and the feedback capacitor in the residual amplifier to exchange, extracts the quantization noise of the second-stage sub-analog-digital converter in the previous sampling period, and realizes the first-order error feedback type noise shaping through the residual amplifier in the current sampling period, thereby reducing the precision influence caused by the unprocessed final-stage quantization noise in the traditional pipelined successive approximation analog-digital converter. The switch of the switch load capacitance switch circuit is controlled by a clock signal, the quantization noise of the second-stage sub-analog-digital converter is extracted, and compared with the mode of using an active circuit, the speed of the pipeline successive approximation analog-digital converter for completing one-time data conversion is improved while the overall power consumption of the circuit is effectively reduced.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a schematic diagram of a switched load capacitance switching circuit of the present invention;
FIG. 3 is a schematic diagram of state (b) of the switched load capacitance switching circuit flow diagram of the present invention;
FIG. 4 is a schematic diagram of state (a) of the switched load capacitance switching circuit flow diagram of the present invention;
FIG. 5 is a schematic diagram of state (c) of the switched load capacitance switching circuit flow diagram of the present invention;
FIG. 6 is a schematic diagram of state (d) in the flow chart of the switched load capacitance switching circuit of the present invention;
FIG. 7 is a timing diagram of the switches Sw1-8 in the switched load capacitance switching circuit of the present invention;
fig. 8 is a schematic diagram of a prior-simulated FFT analysis spectrum of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
The pipeline successive approximation analog-to-digital converter based on the switched load capacitor adopts a fully differential structure (shown in fig. 1) and comprises a first-stage sub-analog-to-digital converter, a residual amplifier, a second-stage sub-analog-to-digital converter, a switched load capacitor switching circuit and a digital output circuit.
The first-stage sub analog-digital converter samples an input analog signal, converts the analog signal into a digital signal, and consists of a capacitor array type digital-analog converter, a dynamic comparator and a successive approximation logic circuit. The capacitor array type digital-to-analog converter is composed of a capacitor array and a control switch. The first-stage sub analog-digital converter is provided with two output ends, the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit, and the residual signal of the upper polar plate of the capacitor array type digital-analog converter flows into the residual amplifier through the switch S2.
The specific working principle is described below with reference to fig. 1 and 2, where the first-stage sub-analog-to-digital converter first enters a sampling stage, samples an input signal Vin through a switch S1, and at this time S1 is closed and S2 is opened; in the quantization process, namely in the process of converting an analog signal into a digital signal by a first-stage sub-analog-digital converter, at the moment, a switch S1 is opened, a switch S2 is opened, an analog signal output by a capacitor array type digital-analog converter is sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signal from the capacitor array type digital-analog converter, the analog signal starts to be compared and output a high-level or low-level analog signal, the output signal flows to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-analog converter to switch so as to convert the next data; after quantization is completed, namely the first-stage sub-analog-digital converter completes the conversion process of an analog signal to a digital signal, when residual voltage of the first-stage sub-analog-digital converter begins to be amplified, the switch S1 is opened, the switch S2 is closed, the upper polar plate of the capacitor array type digital-analog converter stores the residual signal of the current period, and the output signal is received by the input end of the residual amplifier through the switch S2.
The sampling switch S1 of the first-stage sub-analog-digital converter is a grid voltage bootstrap circuit (Bootstrapped Switch), so that the influence of an input signal on the on-resistance of the switch is reduced, and the linearity of a sampling signal is improved; meanwhile, the capacitor array type digital-to-analog converter adopts a lower polar plate for sampling, so that the influence of charge injection in a switch channel on sampling signals is reduced when a control switch is opened; considering that the method is applied to the high-speed field, the capacitor array weight of the first-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the dynamic comparator of the first-stage sub analog-digital converter is added with a current injection circuit based on a charge pump structure, so that offset self-correction of the comparator is carried out, and the error of offset of the dynamic comparator of the first-stage sub analog-digital converter on signal conversion from analog quantity to digital quantity is reduced; the successive approximation logic circuit of the first-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization can be reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
The residual amplifier adopts a closed loop switch capacitor structure and is composed of an operational amplifier, a feedback capacitor and a load capacitor, and the gain of the residual amplifier is the ratio of the total capacitance of a capacitor array in the first-stage sub analog-digital converter to the feedback capacitor. When the switch S2 is closed, the input signal of the operational amplifier is a residual signal stored in the upper polar plate after the quantization of the first-stage sub analog-digital converter is completed, and the residual signal is amplified to the reference voltage of the second-stage sub analog-digital converter; when the switch S3 is closed, the output signal is sampled by the second-stage sub-analog-to-digital converter for the second-stage sub-analog-to-digital converter to start conversion of the analog signal to the digital signal.
The operational amplifier adopts a folding cascode structure to provide an output signal with a large swing range; meanwhile, the operational amplifier further adopts a Gain-Boost technology (Gain-Boost) to further Boost open-loop Gain, so that the influence of non-ideal factors on the precision of closed-loop Gain is reduced.
The second-stage sub-analog-digital converter consists of a capacitor array type digital-analog converter, a dynamic comparator and a successive approximation logic circuit; the input end of the second-stage sub-analog-digital converter samples residual voltage of the first-stage sub-analog-digital converter amplified by the residual amplifier; the output end of the second-stage sub-A/D converter is only one, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit.
The specific working principle is described below with reference to fig. 1 and 2: the second-stage sub-analog-digital converter firstly enters a quantization stage, at the moment, a switch S3 is opened, and the conversion process from an analog signal to a digital signal is started; the analog signals output by the capacitor array type digital-to-analog converter are sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signals from the capacitor array type digital-to-analog converter, the analog signals begin to be compared and output high-level or low-level analog signals, the output signals flow to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-to-analog converter to switch so as to convert the next data; after the quantization process is finished, at this time, the switch S3 is closed, and a sampling stage is entered, and the output signal amplified by the residual amplifier is sampled.
The capacitor array type digital-to-analog converter of the second-stage sub-analog-to-digital converter adopts the upper polar plate for sampling, compared with the lower polar plate for sampling, the influence of parasitic capacitance at the lower polar plate on the capacitance weight can be reduced, and the quantization precision is improved; considering that the method is applied to the high-speed field, the capacitor array weight of the second-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the resolution requirement of the dynamic comparator of the second-stage sub-analog-digital converter is higher, so that the speed of the dynamic comparator for carrying out one-time analog signal comparison is improved by adopting a structure with a pre-amplifier; the successive approximation logic circuit of the second-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization can be reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
The switching load capacitance switching circuit is arranged on the feedback path and the output end of the residual amplifier, and the opening and closing of the switch are controlled by utilizing time sequence, so that the capacitance C is realized f1 And C f2 As a capacitive load capacitance in exchange for a feedback capacitance. The basic principle is that the quantization noise of the second-stage sub-analog-digital converter of the previous period stored on the load capacitor is transmitted to the input end of the residual amplifier for processing by the upper polar plate of the feedback capacitor through the exchange of the capacitor positions, so that the first-order error feedback type noise shaping is realized, and finally, a new signal processed by the noise transfer function is collected on the load capacitor of the current period, thereby improving the precision of the whole circuit.
The switching load capacitance switching circuit of the present embodiment has switches Sw1-Sw8, S3 and capacitance C of equal magnitude f1 、C f2 Constitution (as shown in fig. 3); wherein the switches Sw1-Sw4 and the capacitor C f1 Connected with Sw5-Sw8 and capacitor C f2 Connected, switchS3 is connected with capacitor C f1 Upper electrode plate of (C) and capacitor C f2 Is arranged on the upper polar plate of the upper polar plate. The specific time sequence of the switches Sw1-Sw8 of the switched load capacitance switching circuit is shown in FIG. 7, and two sampling periods of the pipelined successive approximation analog-to-digital converter are one complete working period of the switched load capacitance switching circuit. On the first time to be exchanged, the switches Sw1, sw3, sw5, sw6, sw7, sw8 are open, and Sw2, sw4 are closed; at the first switching, the switches Sw1, sw3, sw5, sw6, sw8 are closed, and Sw2, sw4, sw7 are opened; in the second standby exchange, the switches Sw1, sw2, sw3, sw4, sw5, sw7 are opened, and Sw6, sw8 are closed; at the second switching, the switches Sw1, sw2, sw4, sw5, sw7 are closed and Sw3, sw6, sw8 are opened.
Referring to fig. 3-6, the switching load capacitance switching circuit includes two sampling periods, C, within a complete cycle f1 And C f2 The working states of the capacitors differ by one sampling period, and the capacitors are all operated according to the sequence of floating at the feedback capacitor, switching to the position of the load capacitor, sampling the output signal of the residual amplifier together with the second-stage sub-analog-digital converter, participating in the quantization process of the second-stage sub-analog-digital converter at the load capacitor, switching to the position of the feedback capacitor. Finally, the suppression effect on the quantization noise of the second-stage sub-analog-digital converter is realized, and the overall accuracy of the circuit is improved.
Referring to FIG. 2, the capacitance C of the switched load capacitance switching circuit is switched over during one sampling period f1 、C f2 Exchange once, after two sampling periods, capacitor C f1 、C f2 Returning to the initial position; according to the basic principle of the pipeline successive approximation analog-digital converter structure, the first-stage sub analog-digital converter works according to the sequence of sampling/holding-quantizing-residual voltage amplifying by the residual voltage amplifier, and the second-stage sub analog-digital converter does not need to sample an input signal, but samples an output signal of the residual voltage amplifying, and only works according to the sequence of quantizing-sampling/holding.
In particular, referring to fig. 2, the switched load capacitance switching circuit can be divided into four states:
(a) First time to be exchanged: referring to FIG. 4, at this time, switch S1 is closed,S2 is opened, the first-stage sub-analog-digital converter is in a sampling/quantizing stage, the switch S3 is opened, and the second-stage sub-analog-digital converter is in a quantizing stage. Switches Sw1 and Sw3 of the switching load capacitance switching circuit are opened, sw2 and Sw4 are closed, and capacitance C f1 At the load capacitor, the quantization noise of the second stage sub-analog-digital converter is stored, the switches Sw5-Sw8 are opened, the capacitor C f2 Is positioned at the feedback capacitor and is in a floating state, and is ready for the first exchange.
(b) First exchange: referring to fig. 3, at this time, the switches S1 are opened and S2 are closed, the first-stage sub-analog-digital converter sends the residual signal to the residual amplifier for amplification, the switch S3 is closed, and the second-stage sub-analog-digital converter samples the output signal of the residual amplifier. Switches Sw1 and Sw3 of the switching load capacitance switching circuit are closed, sw2 and Sw4 are opened, and capacitance C f1 The second-stage sub-analog-digital converter is positioned at the feedback capacitor and takes part in amplifying the first-stage residual signal by the residual amplifier, meanwhile, the quantization noise of the second-stage sub-analog-digital converter sampled in the state to be exchanged is also sent to the input end of the residual amplifier to form first-stage error feedback type noise shaping, the switches Sw5 and Sw7 are opened, the switches Sw6 and Sw8 are closed, and the capacitor C is provided with a first-stage error feedback type noise shaping circuit f2 At the load capacitor, a participating residual amplifier amplifies the residual signal of the first stage sub-analog-to-digital converter.
(c) Second time to be exchanged: referring to fig. 5, at this time, the switches S1 are closed and S2 are opened, the first-stage sub-analog-digital converter is in the sampling/quantization phase, the switch S3 is opened, and the second-stage sub-analog-digital converter is in the quantization phase. The switches Sw1-Sw4 of the switched load capacitance switching circuit are opened, capacitance C f1 At the feedback capacitor, in a floating state, the switches Sw5, sw7 are opened, sw6, sw8 are closed, and the capacitor C f2 The quantization noise of the second-stage sub-analog-digital converter is stored at the load capacitor, and the second exchange is prepared.
(d) Second exchange: referring to fig. 6, at this time, the switches S1 are opened and S2 are closed, the first-stage sub-analog-digital converter sends the residual signal to the residual amplifier for amplification, the switch S3 is closed, and the second-stage sub-analog-digital converter samples the output signal of the residual amplifier. Switches Sw1 and Sw3 of the switching load capacitance switching circuit are opened, sw2 and Sw4 are closed, and capacitance C f1 The residual amplifier is positioned at the load capacitor and is used for amplifying the residual signal of the first-stage sub-analog-digital converter, the switches Sw5 and Sw7 are closed, the switches Sw6 and Sw8 are opened, and the capacitor C f2 The second-stage sub-analog-digital converter is positioned at the feedback capacitor and participates in the residual amplifier to amplify the first-stage residual signal, and meanwhile, quantization noise of the second-stage sub-analog-digital converter sampled in the state to be exchanged is also sent to the input end of the residual amplifier to form first-stage error feedback type noise shaping.
The input end of the digital code value output circuit receives digital signals output by the first-stage sub-analog-digital converter and the second-stage sub-analog-digital converter, an inter-stage redundancy structure is adopted, code value integration is carried out through digital logic, a 10-bit digital code value is finally output, the actual effective digit is improved to 12.55 bits as shown in fig. 8, and the effectiveness of the invention in improving the precision of the pipelined successive approximation analog-digital converter is also proved.
After FFT conversion is carried out on an output codeword under the condition of TT Corner@65 ℃ under the power supply voltage of 1.8V, 1024 sampling points are simulated, the acquired signal spectrum is shown in figure 8, the pipelined successive approximation analog-to-digital converter based on the switched load capacitor achieves 77.30dB of signal-to-noise-distortion ratio (SNDR) under the condition of 8 times of oversampling rate, the effective bit number is about 12.55, and the SFDR achieves 90.81dB. Compared with the SNDR without using a switched load capacitance switching circuit, the SNDR with the switching circuit has the advantages that the SNDR is improved by 15.14dB, and the effective digit is improved by 2.5 digits. The embodiment effectively improves the precision, and verifies the feasibility of the circuit structure through simulation.
According to the embodiment, the quantization noise of the second-stage sub-analog-digital converter in the previous sampling period is extracted through the switched load capacitance switching circuit, so that the first-order error feedback type noise shaping is realized, and the influence on precision caused by the unprocessed final-stage quantization noise in the traditional pipelined successive approximation analog-digital converter is reduced; the switching load capacitance switching circuit controls switching through a clock signal, extracts quantization noise of the second-stage sub-analog-digital converter, avoids using an additional active circuit to extract noise signals, improves the speed of the whole circuit, and reduces power consumption; the structure integrates the advantages of the pipelined successive approximation analog-to-digital converter and the noise shaping structure, and can meet the parameter requirements of high speed, high precision and low power consumption.
Claims (7)
1. A pipeline successive approximation analog-to-digital converter based on a switched load capacitor is characterized in that: the full-differential structure is adopted, and the full-differential structure comprises a first-stage sub-analog-digital converter, a residual error amplifier, a second-stage sub-analog-digital converter, a digital code value output circuit and a switching load capacitance switching circuit;
the first-stage sub analog-to-digital converter consists of a capacitor array type digital-to-analog converter, a dynamic comparator and a successive approximation logic circuit; sampling the input analog signal and converting the analog signal into a digital signal;
the first-stage sub analog-digital converter is provided with two output ends, the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit, and the residual signal of the upper polar plate of the capacitor array type digital-analog converter flows into the residual amplifier through the switch S2;
the specific working flow is as follows: the first-stage sub-analog-digital converter firstly enters a sampling stage, an input signal Vin is sampled through a switch S1, at the moment, S1 is closed, and S2 is opened; in the quantization process, namely in the process of converting an analog signal into a digital signal by a first-stage sub-analog-digital converter, at the moment, a switch S1 is opened, a switch S2 is opened, an analog signal output by a capacitor array type digital-analog converter is sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signal from the capacitor array type digital-analog converter, the analog signal starts to be compared and output a high-level or low-level analog signal, the output analog signal flows to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-analog converter to switch so as to convert the next data; after quantization is finished, namely the first-stage sub-analog-digital converter finishes the conversion process of an analog signal to a digital signal, when the residual voltage of the first-stage sub-analog-digital converter begins to be amplified, a switch S1 is opened, a switch S2 is closed, the upper polar plate of the capacitor array type digital-analog converter stores the residual signal of the current period, and the output signal is received by the input end of the residual amplifier through the switch S2;
the residual amplifier adopts a closed loop switch capacitor structure and consists of an operational amplifier, a feedback capacitor and a load capacitor, and the gain of the residual amplifier is the ratio of the total capacitance of a capacitor array in the first-stage sub analog-digital converter to the feedback capacitor; the negative input end of the operational amplifier is connected with the upper polar plate of the first-stage sub analog-digital converter through a switch S2, the positive input end of the operational amplifier is connected with the ground, and the output end of the operational amplifier is connected with the upper polar plate of the second-stage sub analog-digital converter through a switch S3; capacitor C f1 A capacitor C connected across the negative input and output of the operational amplifier f2 One end of the amplifier is grounded, and the other end of the amplifier is connected with the output end of the operational amplifier; capacitor C f1 And capacitor C f2 The switching circuit of the switching load capacitor controls the opening and closing of the switch by utilizing time sequence, thereby realizing C in the residual amplifier f1 And C f2 As the exchange of the load capacitance and the feedback capacitance, the switch circuit of the exchange load capacitance is arranged on the feedback path and the output end of the residual amplifier;
when the switch S2 is closed, the input signal of the operational amplifier is a residual signal stored in the upper polar plate after the quantization of the first-stage sub analog-digital converter is completed, and the residual signal is amplified to the reference voltage of the second-stage sub analog-digital converter;
when the switch S3 is closed, the output signal of the operational amplifier is sampled by the second-stage sub-analog-digital converter and is used for the second-stage sub-analog-digital converter to start the conversion from the analog signal to the digital signal;
the second-stage sub-analog-digital converter consists of a capacitor array type digital-analog converter, a dynamic comparator and a successive approximation logic circuit; the input end of the second-stage sub-analog-digital converter samples residual voltage of the first-stage sub-analog-digital converter amplified by the residual amplifier; only one output end of the second-stage sub-analog-digital converter is provided, and the converted digital signal flows into the digital code value output circuit through the successive approximation logic circuit;
the specific working flow is as follows: the second-stage sub-analog-digital converter firstly enters a quantization stage, at the moment, a switch S3 is opened, and the conversion process from an analog signal to a digital signal is started; the analog signals output by the capacitor array type digital-to-analog converter are sent into a dynamic comparator, after the input end of the dynamic comparator receives the analog signals from the capacitor array type digital-to-analog converter, the analog signals begin to be compared and output high-level or low-level analog signals, the output signals flow to a successive approximation logic circuit, and the successive approximation logic circuit guides the control switch of the capacitor array type digital-to-analog converter to switch so as to convert the next data; after the quantization process is finished, at the moment, the switch S3 is closed, a sampling stage is carried out, and the output signal amplified by the residual error amplifier is sampled;
the switching load capacitance switching circuit is arranged on a feedback path and an output end of the residual amplifier, and the opening and closing of the switch are controlled by utilizing time sequence, so that a capacitance C in the residual amplifier is realized f1 And C f2 As a capacitive load capacitance exchange with a feedback capacitance; the basic principle is that the quantization noise of the second-stage sub-analog-digital converter of the previous period stored on the load capacitor is transmitted to the input end of the residual amplifier for processing by the upper polar plate of the feedback capacitor through the exchange of the capacitor positions, so that the first-order error feedback type noise shaping is realized, and finally, a new signal processed by the noise transfer function is collected on the load capacitor of the current period, thereby improving the precision of the whole circuit;
the switching load capacitance switch circuit comprises two sampling periods in one complete period, C f1 And C f2 The working states of the capacitors differ by one sampling period, namely the capacitors are floated and switched to the position of the load capacitor at the feedback capacitor, and the output signals of the residual amplifier are sampled together with the second-stage sub-analog-digital converter, and the capacitors participate in the quantization process of the second-stage sub-analog-digital converter at the load capacitor and are switched to the position of the feedback capacitor to work; in one sampling period, the switching load capacitance switching circuit controls the capacitance C through the switch f1 、C f2 Exchange once, after two sampling periods, capacitor C f1 、C f2 Returning to the initial position; the first-stage sub-analog-digital converter works according to the sequence of sampling/holding-quantizing-residual voltage amplifying by the residual amplifier, and the second-stage sub-analog-digital converter does not need to sample an input signal, but samples an output signal of the residual amplifier, and only works according to the sequence of quantizing-sampling/holding;
the input end of the digital code value output circuit receives digital signals output by the first-stage sub-digital converter and the second-stage sub-digital converter, adopts an inter-stage redundancy structure, integrates code values through digital logic, and finally outputs a 10-bit digital code value.
2. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the sampling switch S1 of the first-stage sub-analog-digital converter is a grid voltage bootstrap circuit, so that the influence of an input signal on the on-resistance of the switch is reduced, and the linearity of a sampling signal is improved; meanwhile, the capacitor array type digital-to-analog converter adopts a lower polar plate for sampling, so that the influence of charge injection in a switch channel on sampling signals is reduced when a control switch is opened.
3. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the capacitor array weight of the first-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the dynamic comparator of the first-stage sub analog-digital converter is added with a current injection circuit based on a charge pump structure, so that offset self-correction of the comparator is carried out, and the error of offset of the dynamic comparator of the first-stage sub analog-digital converter on signal conversion from analog quantity to digital quantity is reduced; the successive approximation logic circuit of the first-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization is reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
4. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the operational amplifier adopts a folding cascode structure to provide an output signal with a large swing range; meanwhile, the operational amplifier further improves open loop Gain by adopting a Gain-Boost technology.
5. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the capacitor array type digital-to-analog converter of the second-stage sub-analog-to-digital converter adopts an upper polar plate for sampling so as to reduce the influence of parasitic capacitance at a lower polar plate on the capacitance weight and improve the quantization precision.
6. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the capacitor array weight of the second-stage sub-analog-digital converter is set to be non-binary, so that the establishment speed is improved, and the quantization time is shortened; the dynamic comparator of the second-stage sub-analog-digital converter adopts a structure with a pre-amplifier, so that the comparison speed of analog signals is improved; the successive approximation logic circuit of the second-stage sub-analog-digital converter adopts a quasi-static LATCH structure, and the time required by the successive approximation logic circuit in one-time quantization is reduced by a positive feedback latching mode, so that the overall speed of the circuit is improved.
7. The switched-load capacitor based pipelined successive approximation analog-to-digital converter of claim 1, wherein: the switching load capacitance switching circuit consists of switches Sw1-Sw8 and S3 and a capacitor C with the same size f1 、C f2 Constitute, wherein the switches Sw1-Sw4 and the capacitor C f1 Connected to Sw5-Sw8 and capacitor C f2 Connected with the switch S3 and connected with the capacitor C f1 Upper electrode plate of (C) and capacitor C f2 Is arranged on the upper polar plate of the upper polar plate.
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