CN113746481B - Pipelined successive approximation analog-to-digital converter - Google Patents

Pipelined successive approximation analog-to-digital converter Download PDF

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CN113746481B
CN113746481B CN202111066435.2A CN202111066435A CN113746481B CN 113746481 B CN113746481 B CN 113746481B CN 202111066435 A CN202111066435 A CN 202111066435A CN 113746481 B CN113746481 B CN 113746481B
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stage
triode
digital converter
successive approximation
residual
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CN113746481A (en
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江文宁
诸嫣
陈知行
马许愿
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University of Macau
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The application provides a pipeline successive approximation analog-to-digital converter, and relates to the field of analog-to-digital converters. Comprising the following steps: n-stage successive approximation analog-digital converter and N-1 residual difference amplifiers, N is the integer greater than or equal to 3, each residual difference amplifier is the residual difference amplifier of open loop structure respectively. The i-th stage successive approximation analog-to-digital converter includes: the device comprises an ith capacitor array and an ith comparator, wherein i is any integer between 2 and N-1. The method and the device can avoid high power consumption and simultaneously have higher conversion precision and conversion rate.

Description

Pipelined successive approximation analog-to-digital converter
Technical Field
The present application relates to the field of analog-to-digital converters, and in particular, to a pipelined successive approximation analog-to-digital converter.
Background
With the continuous improvement of the requirements of the fields of measurement and control systems, digital image acquisition, wireless communication and the like for sampling precision and effectiveness, the development of Analog-to-digital converter (Analog-to-digital converter) is promoted. The analog-to-digital converter is typically located at the input end of the device, and converts the sampled analog voltage signal into a digital signal representing a voltage value with a certain proportion, so that the conversion accuracy and performance of the analog-to-digital converter have great influence on the reliability of subsequent devices.
Common ADCs include Pipeline ADCs (pipelined analog-to-digital converters), SAR (successive approximation register ) ADCs, flash ADCs, and the like. The Pipeline ADC adopts a full parallel structure, so that the conversion speed is high, but the power consumption is high and the precision is low; the SAR ADC needs to perform multiple comparisons in each period, so that the conversion accuracy is high, but the conversion speed is slower.
In recent years, a Pipeline SAR (successive approximation type) ADC combining a Pipeline ADC and a SAR ADC has made great progress in terms of high speed and high accuracy, and is a research hot spot in recent years. However, in the existing multistage pipeline successive approximation type analog-digital converter circuit, under the scene of high speed and high resolution, the number and performance requirements for the residual error amplifier are still high, the power consumption of the residual error amplifier part occupies a large proportion in the whole power consumption of the ADC, and the residual error amplifier is used as a closed loop operational amplifier, and a very high open loop gain is required to be designed, so that the power consumption of the ADC is increased.
Disclosure of Invention
The purpose of the application is to provide a pipeline successive approximation analog-to-digital converter, which is used for solving the problems of low residual voltage amplifying speed and higher overall power consumption of a circuit in a high-speed high-resolution scene of the existing pipeline analog-to-digital converter.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
the embodiment of the application provides a pipeline successive approximation analog-to-digital converter, which comprises:
n-stage successive approximation analog-digital converter and N-1 residual difference amplifiers, N is the integer greater than or equal to 3, each residual difference amplifier is the residual difference amplifier of open loop structure respectively.
The i-th stage successive approximation analog-to-digital converter includes: an ith capacitor array and an ith comparator, i being any integer between 2 and N-1;
the input end of the ith capacitor array is electrically connected with the output end of the ith-1 residual error amplifier to receive the voltage signal amplified by the ith-1 residual error amplifier, and the output end of the ith capacitor array is electrically connected with the positive input end of the ith residual error amplifier and the positive input end of the ith comparator to convert the amplified voltage signal and output the converted voltage signal to the ith residual error amplifier; the output end of the ith level comparator is electrically connected with the input end of the ith level capacitor array;
the first-stage successive approximation analog-to-digital converter comprises: a first stage capacitor array and a first stage comparator;
the input end of the first-stage capacitor array is used for being connected with an input voltage signal, the output end of the first-stage capacitor array is electrically connected with the positive input end of the first residual error amplifier and the positive input end of the first-stage comparator, and the output end of the first-stage comparator is electrically connected with the input end of the first-stage capacitor array;
the nth stage successive approximation analog-to-digital converter includes: an nth stage capacitor array and an nth stage comparator;
the input end of the N-th stage capacitor array is electrically connected with the output end of the N-1 th residual amplifier, the output end of the N-th stage capacitor array is electrically connected with the positive input end of the N-th stage comparator, and the input end of the N-th stage comparator is electrically connected with the input end of the N-th stage capacitor array.
In an alternative embodiment, the residual amplifier includes: the first triode, the second triode, the third triode and the fourth triode;
the first end of the first triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the first triode is used for outputting residual current of the positive electrode, and the third end of the first triode is connected with the third end of the second triode;
the first end of the second triode is used for accessing an input voltage signal, and the second end of the second triode is used for accessing a direct current source after the bias of the current source is regulated;
the first end of the third triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the third triode is used for being connected with a direct current source after the bias of the current source is regulated, and the third end of the third triode is connected with the third end of the fourth triode;
the first end of the fourth triode is used for being connected with an input voltage signal, and the second end of the fourth triode is used for outputting residual current of the negative electrode.
In an alternative embodiment, the residual amplifier further includes: a fifth transistor and a sixth transistor;
the first end of the fifth triode is connected with the second end of the second triode, the second end of the fifth triode is connected with the third end of the second triode, and the third end of the fifth triode is connected with the third end of the sixth triode;
the first end of the sixth triode is connected with the second end of the third triode, the second end of the sixth triode is connected with the third end of the third triode, and the third end of the sixth triode is connected with the third end of the fifth triode.
In an alternative embodiment, the residual amplifier further includes: an inverter, a first switch, and a second switch;
one end of the inverter is electrically connected with the second switch and receives the driving signal, and the other end of the inverter is electrically connected with the first switch.
In an alternative embodiment, the residual amplifier further includes: a seventh transistor and an eighth transistor;
the first end of the seventh triode is connected with the first end of the eighth triode;
the third end of the eighth triode is connected with the second end of the second triode;
the third end of the eighth triode is connected with the second end of the third triode.
In an alternative embodiment, the residual amplifier further includes: the first capacitor, the third switch, the first resistor, the second capacitor, the fourth switch and the second resistor;
one end of the first capacitor is electrically connected with one end of the third switch, and the other end of the third switch is respectively connected with the first resistor and the second end of the first triode;
one end of the second capacitor is electrically connected with one end of the fourth switch, and the other end of the fourth switch is respectively connected with the first resistor and the second end of the first triode.
In an alternative embodiment, the ith stage successive approximation analog-to-digital converter further comprises: an i-th stage reset circuit;
one end of the ith reset circuit is electrically connected with the ith comparator, the other end of the ith reset circuit is electrically connected with the ith residual error amplifier and the (i+1) th capacitor array of the (i+1) th successive approximation analog-to-digital converter, and is used for receiving a driving signal through the ith comparator, inputting the driving signal to the ith residual error amplifier and the (i+1) th capacitor array, and receiving the driving signal from the reset circuit of the (i-1) th successive approximation analog-to-digital converter by the ith capacitor array and transmitting the driving signal to the ith comparator;
the first stage successive approximation analog-to-digital converter further comprises: a first stage reset circuit;
one end of the first-stage reset circuit is electrically connected with the first-stage comparator, and the other end of the first-stage reset circuit is electrically connected with the first residual error amplifier and the second-stage capacitor array of the second-stage successive approximation analog-to-digital converter.
In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: a clock generation circuit and a sampling switch;
one end of the sampling switch is used for accessing the input voltage signal, and the other end of the sampling switch is electrically connected with the input end of the first-stage capacitor array;
the clock generating circuit is electrically connected with the sampling switch and the first-stage capacitor array respectively.
In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: a bias circuit;
the bias circuit is respectively connected with each residual difference amplifier and is used for outputting bias voltage. In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: a detuning and gain calibration circuit;
the offset and gain calibration circuit is respectively connected with each comparator and each residual amplifier in each level of successive approximation analog-to-digital converter and is used for outputting calibration signals to each level of comparator and each level of residual amplifier to perform offset and gain calibration.
The beneficial effects of the embodiment of the application are that:
by adopting the pipeline successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter is adopted at each stage of the pipeline analog-to-digital converter to perform multi-bit conversion, so that the power consumption of the analog-to-digital converter is reduced and the number of the rear-end residual difference amplifiers is reduced in a high-speed high-resolution scene. Meanwhile, the residual error amplifier adopts an open loop structure, so that the power consumption of the residual error amplifier in closed loop operation due to open loop gain is avoided.
Further, the residual amplifier adopts an open loop structure, residual current is directly converted into output voltage through a resistor load, a capacitive negative feedback structure of the residual amplifier with a closed loop structure is omitted, the amplifying speed is improved, and the power consumption of the analog-to-digital converter is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a pipelined analog-to-digital converter according to the present disclosure;
FIG. 2 is a schematic diagram illustrating a capacitance arrangement of an i-th stage successive approximation analog-to-digital converter of the pipeline analog-to-digital converter according to the present application;
FIG. 3 is a schematic diagram of a residual amplifier with an open loop structure of a pipelined analog-to-digital converter according to the present disclosure;
FIG. 4 is a graph of the output spectrum of the pipelined successive approximation analog-to-digital converter proposed herein;
fig. 5 is a DNL/INL simulation result of the pipeline successive approximation analog-to-digital converter proposed in the present application.
Icon: 10-a pipeline successive approximation analog-to-digital converter; a 100-sample switch; 101-a first-stage successive approximation analog-to-digital converter; 1011-a first stage capacitor array; 1012-a first stage comparator; 1013-a first stage reset circuit; 102-a first residual amplifier; 103-ith stage successive approximation analog-to-digital converter; 1031-ith stage of capacitor array; 1032-i-th stage comparators; 1033-ith stage of reset circuit; 104-ith residual amplifier; 105-Nth stage successive approximation analog-to-digital converter; 1051-nth stage capacitor array; 1052-nth stage comparators; 106-a bias circuit; 107-offset and gain calibration circuitry; 108-a clock generation circuit; 20-residual amplifier; 201-positive electrode circuit of residual difference amplifier; negative pole circuit of 202-residual amplifier.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
The pipelined analog-to-digital converter structure has great demands in high-speed high-resolution application, the traditional pipelined analog-to-digital converter has great power consumption when carrying out multi-bit quantization, and meanwhile, the power consumption generated by the residual amplifier with the closed-loop structure accounts for great proportion of the power consumption of the whole analog-to-digital converter. In order to improve the conversion speed of the analog-to-digital converter and reduce the power consumption, the application provides a pipeline successive approximation analog-to-digital converter, wherein each stage of the pipeline analog-to-digital converter adopts the successive approximation analog-to-digital converter to carry out multi-bit conversion, so that the power consumption of the analog-to-digital converter is reduced, and the number of the rear-end residual difference amplifiers is reduced. Meanwhile, the application also provides a residual error amplifier with an open loop structure, which has higher amplifying speed and lower power consumption compared with a residual error amplifier with a closed loop structure.
A pipelined successive approximation analog-to-digital converter provided by embodiments of the present application is explained below in connection with a number of specific application examples.
The application provides a pipelined successive approximation analog-to-digital converter comprising: n-stage successive approximation analog-digital converter and N-1 residual difference amplifiers, N is the integer greater than or equal to 3, each residual difference amplifier is the residual difference amplifier of open loop structure respectively. For convenience of description, in fig. 1, N is taken as 3 for illustration.
Fig. 1 is a schematic structural diagram of a pipelined successive approximation analog-to-digital converter provided in the present application. As shown in fig. 1, the i-th stage successive approximation analog-to-digital converter 103 of the pipelined successive approximation analog-to-digital converter 10 includes:
the ith stage capacitive array 1031 and the ith stage comparator 1032, i is any integer between 2 and N-1. In the example of fig. 1, i is 2. The input end of the i-th stage capacitor array 1031 is electrically connected to the i-1 th residual amplifier, i.e., the output end of the first residual amplifier 102, so as to receive the voltage signal amplified by the i-1 th residual amplifier, i.e., the first residual amplifier 102, the output end of the i-th stage capacitor array 1031 is electrically connected to the positive input end of the i-th residual amplifier 104 and the positive input end of the i-th stage comparator 1032, so as to convert the amplified voltage signal and output the converted voltage signal to the i-th residual amplifier 104, and the output end of the i-th stage comparator 1032 is electrically connected to the input end of the i-th stage capacitor array 1031.
In the present embodiment, the analog-to-digital conversion process of the i-th stage successive approximation analog-to-digital converter 103 is: the (i-1) -th residual amplifier, i.e. the residual voltage amplified by the first residual amplifier 102, is input to the capacitor array top plate of the ith stage capacitor array 1031 for fixingThe ith comparator 1032 compares the reference voltage signal V input to the ith capacitive array 1031 ref And the magnitude of the voltage signal amplified by the i-1 th residual amplifier, i.e., the first residual amplifier 102, if the voltage signal amplified by the i-1 th residual amplifier, i.e., the first residual amplifier 102, is greater than the reference voltage signal V ref The ith comparator outputs a logic high level "1" and inputs to the capacitor array top plate of the ith capacitor array 1031 to be fixed, otherwise the ith comparator outputs a logic low level "0" and inputs to the capacitor array top plate of the ith capacitor array 1031 to be fixed. Subsequently, the reference voltage signal V is changed ref To V ref And/2, performing the next comparison, wherein the comparison process is continued to the lowest order. After the conversion is finished, outputting an ith stage analog-to-digital conversion result D outi And is secured to the top plate of the capacitive array of the ith stage of capacitive array 1031. Then, input voltage signal V ini And the i-th level analog-to-digital conversion result D outi I.e., the i-th stage residual voltage signal, is transmitted to the i-th residual amplifier. Wherein, the input voltage signal V of the ith successive approximation analog-to-digital converter ini Is 1/2 of the input voltage signal of the i-1 th stage successive approximation analog-to-digital converter, namely the input voltage signal V of the i-1 th stage successive approximation analog-to-digital converter ini Is V (V) ini-1 /2。
Optionally, the first stage successive approximation analog-to-digital converter 101 comprises: a first stage capacitor array 1011 and a first stage comparator 1012. The input end of the first stage capacitor array 1011 is used for accessing an input voltage signal, the output end of the first stage capacitor array 1011 is electrically connected with the positive input end of the first residual error amplifier 102 and the positive input end of the first stage comparator 1012, and the output end of the first stage comparator 1012 is electrically connected with the input end of the first stage capacitor array 1011.
The first-stage successive approximation analog-to-digital converter 101 performs an analog-to-digital conversion process of: input voltage signal V sampled by sampling switch 100 in Is input to the top plate of the first stage capacitor array 1011, which also inputs a reference voltage signal V ref The first stage comparator 1012 compares the reference voltage signal V input to the first stage capacitor array 1011 ref And input voltage signal V in If the magnitude of the input voltage signal V in The amplified voltage signal is greater than the reference voltage signal V ref The first stage comparator outputs a logic high level "1" and inputs to the capacitor array top plate of the first stage capacitor array 1011 to be fixed, otherwise, the first stage comparator outputs a logic low level "0" and inputs to the capacitor array top plate of the first stage capacitor array 1011 to be fixed. Subsequently, the reference voltage signal V is changed ref To V ref And/2, performing the next comparison, wherein the comparison process is continued to the lowest order. After the conversion is finished, a first-stage analog-to-digital conversion result D is obtained out1 And is fixed to the capacitor array top plate of the first stage capacitor array 1011. Then, input voltage signal V in And the first-stage analog-to-digital conversion result D out1 The difference of (a) is transmitted to the first stage residual voltage signal to the first residual amplifier 102. Wherein, the input voltage signal V of the first-stage successive approximation analog-to-digital converter in Input voltage signal V sampled by sampling switch 100 in The same applies.
Optionally, the nth stage successive approximation analog-to-digital converter 105 includes: an nth stage capacitor array 1051 and an nth stage comparator 1052. The input end of the nth stage capacitor array 1051 is electrically connected to the N-1 th residual amplifier, i.e., the output end of the ith residual amplifier 104 in fig. 1, the output end of the nth stage capacitor array 1051 is electrically connected to the positive input end of the nth stage comparator 1052, and the input end of the nth stage comparator 1052 is electrically connected to the input end of the nth stage capacitor array 1051.
The N-th successive approximation analog-to-digital converter 105 performs an analog-to-digital conversion process of: the N-1 th residual amplifier, i.e. the i-th residual amplifier 104 in the figure, inputs the amplified residual voltage to the capacitor array top plate of the N-th capacitor array 1051 for fixation, and the N-th comparator 1052 compares the reference voltage signal V input to the N-th capacitor array 1051 ref And the N-1 th residual amplifier, i.e. the size of the voltage signal amplified by the ith residual amplifier 104 in the figure, if the N-1 th residual amplifier, i.e. the voltage signal amplified by the ith residual amplifier 104 in the figure, is greater than the reference voltage signal V ref The N-th comparator outputs a logic high powerFlat "1" and input to the capacitor array top plate of the nth stage capacitor array 1051, otherwise, the nth stage comparator outputs a logic low level "0" and input to the capacitor array top plate of the nth stage capacitor array 1051. Subsequently, the reference voltage signal V is changed ref To V ref And/2, performing the next comparison, wherein the comparison process is continued to the lowest order. After the conversion is finished, the N-th level analog-to-digital conversion result D is output outN And is fixed to the capacitor array top plate of the nth stage capacitor array 1051. Wherein, the input voltage signal V of the Nth stage successive approximation analog-to-digital converter inN Is 1/2 of the input voltage signal of the N-1 stage successive approximation analog-to-digital converter, namely the input voltage signal V of the N stage successive approximation analog-to-digital converter inN Is V (V) inN-1 /2。
After the multi-stage analog-to-digital conversion is completed, a first-stage analog-to-digital conversion result D out1 Analog-to-digital conversion result D from N-th stage outN To output the addition result D out . Wherein the bit number of any stage of analog-digital conversion result is set to be the result bit number D out I.e. the requirements for accuracy and speed are approximately equally distributed.
Alternatively, as shown in fig. 2, the capacitance sizes of any one stage of the capacitor array of the N-stage successive approximation analog-to-digital converter are arranged in an exponential power of 2. Taking an i-th-stage successive approximation analog-to-digital converter as an example, setting the reference capacitance as C ui The size of the capacitor array at any stage is respectively: 8C (8C) ui 、4C ui 、2C ui 、C ui 、C dumi . Wherein C is dumi Is a weighted capacitance.
The multistage pipeline successive approximation analog-digital converter adopted in the embodiment adopts the successive approximation analog-digital converter at each stage of the pipeline analog-digital converter, reduces the power consumption of the analog-digital converter in a high-speed high-resolution scene, and reduces the number of residual difference amplifiers at the rear end. The residual difference amplifier connected with the rear end of each stage of successive approximation type analog-digital converter adopts an open loop structure, so that the amplification speed is improved, and the power consumption of the analog-digital converter is reduced.
With continued reference to fig. 1, the i-th stage successive approximation analog-to-digital converter 103 further includes: first, thei-stage reset circuit 1033. One end of the ith reset circuit 1033 is electrically connected with the ith comparator 1032, and the other end of the ith reset circuit 1033 is electrically connected with the ith residual error amplifier 104 and the (i+1) th capacitor array of the (i+1) th successive approximation analog-to-digital converter for receiving the driving signal phi via the ith comparator 1032 Ci And inputs a driving signal phi to the ith residual amplifier 104 and the (i+1) th stage capacitor array RAi Drive signal phi RAi-1 Is received by the i-th stage capacitive array 1031 from the reset circuit of the i-1-th stage successive approximation analog-to-digital converter and passed to the i-th stage comparator 1032. As shown in fig. 1, the first-stage successive approximation analog-to-digital converter 101 further includes: a first stage reset circuit 1013. One end of the first-stage reset circuit 1013 is electrically connected to the first-stage comparator 1012, and the other end of the first-stage reset circuit 1013 is electrically connected to the first residual amplifier 102 and the second-stage capacitor array of the second-stage successive approximation analog-to-digital converter.
In the first-stage successive approximation analog-to-digital converter 101, the first-stage reset circuit 1013 is configured to transmit a clock signal, and mainly includes two aspects: on the one hand receive the clock signal phi via the first stage capacitor array 1011 C1 On the other hand according to the received clock signal phi C1 Transmitting a driving signal phi RA1 The second stage capacitor array and the first residual amplifier 102 to the second stage successive approximation analog-to-digital converter drive the second stage successive approximation analog-to-digital converter and the first residual amplifier 102 to start working.
In the i-th successive approximation analog-to-digital converter 103, the i-th reset circuit is configured to transmit a clock signal, and mainly includes two aspects: on the one hand, receives the driving signal phi generated by the i-1-stage reset circuit RAi-1 I.e. phi in figure 1 RA1 Clock signal Φ via an ith stage of capacitive array Ci On the other hand according to the received clock signal phi Ci Transmitting a driving signal phi RAi The i+1th stage capacitor array and the i residual amplifier 104 to the i+1th stage successive approximation analog-to-digital converter drive the i+1th stage successive approximation analog-to-digital converter and the i residual amplifier 104 to start working.
Nth stage successive approximation analog-to-digital converter105, the N-1 th stage reset circuit generates a driving signal phi RAN-1 I.e. phi in figure 1 RAi Clock signal Φ via N-th stage capacitor array CN The Nth stage successive approximation analog-to-digital converter is driven to start working.
In this embodiment, the reset circuit realizes the transition and transfer of the clock signal, so as to drive the sequential operation of the whole pipeline successive approximation analog-digital converter.
Optionally, as shown in fig. 1, the pipelined successive approximation analog-to-digital converter further includes: clock generation circuit 108 and sampling switch 100. One end of the sampling switch 100 is used for accessing an input electrical signal V in The other end of the sampling switch 100 is electrically connected to the input of the first stage capacitor array 1011. The clock generation circuit 108 is electrically connected to the sampling switch 100 and the first stage capacitor array 1011, respectively.
The clock generation circuit 108 is used for generating clock signals, and driving different components of the pipeline successive approximation analog-to-digital converter to work in different time periods, so that asynchronous logic of the circuit is realized.
The sampling switch 100 is used for inputting an electrical signal V in Sampling is performed on the clock signal phi generated by the clock generation circuit 108 S When the value is "1", the sampling switch 100 is closed to input the electric signal V in The top plate of the capacitor array input to the first stage capacitor array 1011 is fixed.
With continued reference to fig. 1, the pipelined successive approximation analog-to-digital converter further includes: a bias circuit 106. The bias circuit 106 is connected to each residual amplifier, and is configured to output bias voltages to the seventh triode and the eighth triode, so as to maintain stability of the seventh triode and the eighth triode.
As shown in fig. 1, the pipelined successive approximation analog-to-digital converter further includes: an offset and gain calibration circuit 107. The circuit is respectively connected with each comparator and each residual amplifier in each level of successive approximation analog-to-digital converter and is used for outputting a calibration signal to each level of comparator and each level of residual amplifier to perform offset and gain calibration.
The function of the mismatch and gain calibration circuit 107 includes two aspects: in one aspect of the present invention,for the first-stage analog-to-digital conversion result D out1 Analog-to-digital conversion result D from N-th stage outN Output results of (a) are combined to output a digital conversion result D out . Wherein the digital conversion result D out The more bits, the more accurate the result. On the other hand, the offset and gain calibration circuit 107 is configured to perform the first-stage analog-to-digital conversion according to the first-stage analog-to-digital conversion result D out1 Analog-to-digital conversion result D from N-th stage outN And (3) sending a calibration signal to each level of successive approximation analog-to-digital converter, and adjusting the offset voltage of each level of successive approximation analog-to-digital converter.
The residual amplifier having the open loop structure will be described below.
Alternatively, as shown in fig. 3, the residual amplifier 20 having an open loop structure includes: the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4. Wherein the first end of the first triode M1 is used for being connected with a fixed voltage signal V of an upper polar plate of a higher-stage capacitor array ip The second end of the first triode M1 is used for outputting residual current of the positive electrode, and the third end of the first triode M1 is connected with the third end of the second triode. The first end of the second triode M2 is used for connecting the input voltage signal V in The second end of the second triode M2 is connected with a direct current source after the bias of the current source is regulated. A first end of the triode M3 is used for being connected with a fixed voltage signal V of an upper polar plate of the upper-stage capacitor array ip The second end of the third triode M3 is used for being connected with a direct current source after the bias of the current source is regulated, and the third end of the third triode M3 is connected with the third end of the fourth triode. The first end of the fourth triode M4 is used for accessing the input voltage signal V in The second end of the fourth triode M4 is used for outputting residual current of the negative electrode.
Optionally, the residual amplifier 20 having the open loop structure further includes: a fifth transistor M5 and a sixth transistor M6. The first end of the fifth triode M5 is connected with the second end of the second triode M2, the second end of the fifth triode M5 is connected with the third end of the second triode M2, and the third end of the fifth triode M5 is connected with the third end of the sixth triode M6. The first end of the sixth triode M6 is connected with the second end of the third triode M3, the second end of the sixth triode M6 is connected with the third end of the third triode M3, and the third end of the sixth triode M6 is connected with the third end of the fifth triode M5.
In the present embodiment, since the differential design is adopted in the circuit of the residual amplifier 20, the transistors of the residual amplifier 20 are arranged in a bilateral symmetry manner, and the positive electrode circuit 201 of the residual amplifier comprises a first transistor M1, a second transistor M2, a fifth transistor M5, a seventh transistor M7, and a first resistor R O1 Third switch S r3 And a first capacitor C S1 . The negative electrode circuit 202 of the residual amplifier comprises a third transistor M3, a fourth transistor M4, a sixth transistor M6, an eighth transistor M8, and a second resistor R O2 Fourth switch S r4 And a second capacitor C S2 . In addition, in the residual amplifier 20, the signal input terminal is defined as a first terminal of a triode, the upper terminal is defined as a second terminal in the figure, and the lower terminal is defined as a third terminal.
The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 together form a transconductance with negative feedback, and an input voltage V is input in And fixed voltage signal V of upper polar plate of upper stage capacitor array ip The difference, i.e., the residual voltage, is converted to residual current. The transconductance part adopts a current negative feedback structure, namely a fifth triode M5 and a sixth triode M6, and is used for realizing small output equivalent impedance at the source ends of the second triode M2 and the third triode M3.
In the embodiment, a transconductance structure with current negative feedback is adopted, so that linearity of a residual voltage-residual current conversion process of the residual amplifier is greatly improved. In addition, the current negative feedback structure formed by the second triode and the third triode also enables the residual error amplifier in the embodiment to be stable under different input signals.
Optionally, the residual amplifier 20 further includes: inverter, first switch S r1 And a second switch S r2 . One end of the inverter is respectively connected with the second switch S r2 Electrically connected toAnd receiving the driving signal, the other end of the inverter and the first switch S r1 And (5) electric connection.
The differential amplifier 20 in the present embodiment adopts a dynamic operation process, and the second switch S is used when the differential amplifier 20 is operated r2 Closing, driving signal Φ RA Through a second switch S r2 Is input to the residual amplifier 20, and drives the residual amplifier 20 to amplify the residual voltage signal. After the amplification is finished, a second switch S r2 Open, first switch S r1 Closing, the residual amplifier 20 receives the drive signal Φ after phase inversion by the inverter RA The residual amplifier 20 stops operating.
In the present embodiment, a first switch S is used r1 And a second switch S r2 And the inverter and the residual amplifier realize a dynamic working mode, and the dynamic working mode can effectively reduce the power consumption of the residual amplifier, thereby reducing the total power consumption of the pipeline successive approximation analog-digital converter.
Optionally, the residual amplifier further includes: seventh transistor M7 and eighth transistor M8. The first end of the seventh triode M7 is connected with the first end of the eighth triode M8, the third end of the eighth triode M8 is connected with the second end of the second triode M2, and the third end of the eighth triode M8 is connected with the second end of the third triode M3.
It can be seen that the second terminals of the seventh transistor M7 and the eighth transistor M8 are connected to a dc current source, and in order to make the operating states of the seventh transistor M7 and the eighth transistor M8 amplifying the voltages more stable, the first terminals of the seventh transistor M7 and the eighth transistor M8 are connected to a bias voltage. After the voltage bias of the direct current source is regulated, the seventh triode M7 and the eighth triode M8 transmit the direct current source biased by the regulated current source to the second triode M2 and the third triode M3 to supply power for the residual amplifier.
In the present embodiment, the seventh transistor M7 and the eighth transistor M8 of the residual amplifier 20 use the applied bias voltage to adjust the dc current source, so that the residual amplifier stably operates in the amplifying state.
Optionally, the residual amplifier further includes: first oneCapacitor C S1 Third switch S r3 A first resistor R O1 A second capacitor C S2 Fourth switch S r4 A second resistor R O2 . First capacitor C S1 One end of (a) is connected with a third switch S r3 Is electrically connected with one end of a third switch S r3 The other end of (a) is respectively connected with the first resistor R O1 And the second end of the first triode M1 is connected. Second capacitor C S2 One end of (a) is connected with a fourth switch S r4 Is electrically connected with one end of a fourth switch S r4 Respectively with the other end of the second resistor R O2 And the second end of the fourth triode M4 is connected.
Wherein the third switch and the fourth switch control the driving signal phi S1 And phi is S2 ，Φ S1 And phi is S2 Equivalent to the driving signal phi input to the residual amplifier 20 RA . After the first triode M1 and the fourth triode M4 output residual current, a resistor load, namely a first resistor R O1 And a second resistor R O2 Converting residual current into positive residual voltage V OP And negative electrode residual voltage V ON And store to the first capacitor C S1 And a second capacitor C S2 Is a kind of medium. First capacitor C S1 And a second capacitor C S2 The difference between the voltage signals is the residual amplified signal.
In the embodiment, the residual amplifier adopts a differential circuit design to convert the positive residual voltage V OP And negative electrode residual voltage V ON The difference between the two outputs is used as a residual amplified signal, so that errors are avoided. In addition, the residual amplifier in the embodiment adopts an open loop structure, and residual current is directly converted into output voltage through a resistor load, so that a capacitive negative feedback structure of the residual amplifier with a closed loop structure is omitted, the amplifying speed is improved, and the power consumption of the analog-to-digital converter is reduced.
Fig. 4 is a graph of an output spectrum of a pipelined successive approximation analog-to-digital converter according to the present application. The pipelined analog-to-digital converter adopts a 28nm standard CMOS process for circuit design and performs flow verification. The whole circuit works under 1V source voltage, the sampling frequency is 1GS/s, the input signal amplitude is 1.2Vpp-diff, and the power consumption of the pipeline successive approximation analog-digital converter is 7.6mW. When the input frequency is 495.19MHz, the test results in a pipeline successive approximation analog-to-digital converter output spectrogram (down-conversion extraction 225 times) as shown in FIG. 4. Through calculation of fig. 4, the signal-to-noise and distortion ratio (SNDR) ratio of the pipeline successive approximation analog-to-digital converter provided by the application is 60dB, the quality factor reaches 9.3fJ/conv. -step, and the highest energy efficiency and quality factor under the same speed and signal-to-noise ratio index are realized.
Fig. 5 is a DNL/INL simulation result of the pipeline successive approximation analog-to-digital converter proposed in the present application. The result obtained by inputting a sinusoidal signal, converting the ADC for millions of times and counting the code density output by the ADC is shown.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (8)

1. A pipelined successive approximation analog-to-digital converter comprising:
n-stage successive approximation analog-digital converter and N-1 residual difference amplifiers, N is an integer greater than or equal to 3, each residual difference amplifier is a residual difference amplifier with an open loop structure;
the i-th stage successive approximation analog-to-digital converter includes: an ith capacitor array and an ith comparator, i being any integer between 2 and N-1;
the input end of the ith capacitor array is electrically connected with the output end of the ith-1 residual error amplifier to receive the voltage signal amplified by the ith-1 residual error amplifier, and the output end of the ith capacitor array is electrically connected with the positive input end of the ith residual error amplifier and the positive input end of the ith comparator to convert the amplified voltage signal and output the converted voltage signal to the ith residual error amplifier; the output end of the ith stage comparator is electrically connected with the input end of the ith stage capacitor array;
the first-stage successive approximation analog-to-digital converter comprises: a first stage capacitor array and a first stage comparator;
the input end of the first-stage capacitor array is used for being connected with an input voltage signal, the output end of the first-stage capacitor array is electrically connected with the positive input end of the first residual error amplifier and the positive input end of the first-stage comparator, and the output end of the first-stage comparator is electrically connected with the input end of the first-stage capacitor array;
the nth stage successive approximation analog-to-digital converter includes: an nth stage capacitor array and an nth stage comparator;
the input end of the N-th stage capacitor array is electrically connected with the output end of the N-1 th residual amplifier, the output end of the N-th stage capacitor array is electrically connected with the positive input end of the N-th stage comparator, and the input end of the N-th stage comparator is electrically connected with the input end of the N-th stage capacitor array;
the residual amplifier includes: the first triode, the second triode, the third triode and the fourth triode;
the first end of the first triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the first triode is used for outputting residual current of the positive electrode, and the third end of the first triode is connected with the third end of the second triode;
the first end of the second triode is used for being connected with an input voltage signal, and the second end of the second triode is used for being connected with a direct current source after the bias of the current source is regulated;
the first end of the third triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the third triode is used for being connected with a direct current source after the bias of the current source is regulated, and the third end of the third triode is connected with the third end of the fourth triode;
the first end of the fourth triode is used for being connected with an input voltage signal, and the second end of the fourth triode is used for outputting residual current of the negative electrode;
the residual amplifier further includes: the first capacitor, the third switch, the first resistor, the second capacitor, the fourth switch and the second resistor; wherein the residual amplifier is a single-stage transconductance amplifier;
one end of the first capacitor is electrically connected with one end of the third switch, and the other end of the third switch is respectively connected with the first resistor and the second end of the first triode;
one end of the second capacitor is electrically connected with one end of the fourth switch, and the other end of the fourth switch is respectively connected with the second resistor and the second end of the fourth triode.
2. The pipelined successive approximation analog-to-digital converter of claim 1, wherein the residual amplifier further comprises: a fifth transistor and a sixth transistor;
the first end of the fifth triode is connected with the second end of the second triode, the second end of the fifth triode is connected with the third end of the second triode, and the third end of the fifth triode is connected with the third end of the sixth triode;
the first end of the sixth triode is connected with the second end of the third triode, the second end of the sixth triode is connected with the third end of the third triode, and the third end of the sixth triode is connected with the third end of the fifth triode.
3. The pipelined successive approximation analog-to-digital converter of claim 2, wherein the residual amplifier further comprises: an inverter, a first switch, and a second switch;
one end of the inverter is electrically connected with the second switch and receives a driving signal, and the other end of the inverter is electrically connected with the first switch.
4. A pipelined successive approximation analog-to-digital converter as claimed in claim 3 wherein the residual amplifier further comprises: a seventh transistor and an eighth transistor;
the first end of the seventh triode is connected with the first end of the eighth triode;
the third end of the eighth triode is connected with the second end of the second triode;
and the third end of the eighth triode is connected with the second end of the third triode.
5. The pipelined successive approximation analog-to-digital converter according to any one of claims 1-4, wherein the i-th stage successive approximation analog-to-digital converter further comprises: an i-th stage reset circuit;
one end of the ith level reset circuit is electrically connected with the ith level comparator, the other end of the ith level reset circuit is electrically connected with the ith residual error amplifier and the (i+1) th level capacitor array of the (i+1) th level successive approximation analog-to-digital converter, and is used for receiving a driving signal through the ith level comparator, inputting the driving signal to the ith residual error amplifier and the (i+1) th level capacitor array, and receiving the driving signal from the reset circuit of the (i-1) th level successive approximation analog-to-digital converter by the ith level capacitor array and transmitting the driving signal to the ith level comparator;
the first stage successive approximation analog-to-digital converter further comprises: a first stage reset circuit;
one end of the first-stage reset circuit is electrically connected with the first-stage comparator, and the other end of the first-stage reset circuit is electrically connected with the first residual error amplifier and the second-stage capacitor array of the second-stage successive approximation analog-to-digital converter.
6. The pipelined successive approximation analog-to-digital converter according to any one of claims 1-4, further comprising: a clock generation circuit and a sampling switch;
one end of the sampling switch is used for accessing the input voltage signal, and the other end of the sampling switch is electrically connected with the input end of the first-stage capacitor array;
the clock generation circuit is electrically connected with the sampling switch and the first-stage capacitor array respectively.
7. The pipelined successive approximation analog-to-digital converter according to any one of claims 1-4, further comprising: a bias circuit;
the bias circuit is respectively connected with each residual difference amplifier and is used for outputting bias voltage.
8. The pipelined successive approximation analog-to-digital converter according to any one of claims 1-4, further comprising: a detuning and gain calibration circuit;
the offset and gain calibration circuit is respectively connected with each comparator and each residual error amplifier in the successive approximation analog-to-digital converter of each stage and is used for outputting calibration signals to the comparators of each stage and the residual error amplifiers of each stage to perform offset and gain calibration.
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