CN114172516A

CN114172516A - Split assembly line-successive approximation type analog-to-digital converter

Info

Publication number: CN114172516A
Application number: CN202111329120.2A
Authority: CN
Inventors: 叶凡; 曹越峰; 张淑敏; 赵雨桐; 陈迟晓; 任俊彦; 许俊; 马顺利
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2022-03-11

Abstract

The invention discloses a split type assembly line-successive approximation type analog-digital converter. The analog-to-digital converter circuit consists of a coarse successive approximation analog-to-digital converter, an encoder, a digital calibration module and two symmetrical half channels; each half-channel circuit comprises a first-stage fine successive approximation type analog-to-digital converter, a dynamic amplifier and a second-stage successive approximation type analog-to-digital converter; the rough analog-to-digital converter samples an input signal and generates an output code value through the quantization of the first-stage converter; the encoder encodes the output and controls the capacitor array of the first-stage converter of the two half channels to turn over; generating a first-stage residue, amplifying the first-stage residue by a dynamic amplifier, sampling the first-stage residue by a second-stage converter, and generating respective second-stage output digital code values; the front and the back two stages work in a pipeline mode; the outputs of the first and second stages of the two half-channels are passed through a digital calibration module to obtain the output of the entire ADC. The invention has low power consumption, high efficiency and low hardware overhead.

Description

Split assembly line-successive approximation type analog-to-digital converter

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a split type assembly line-successive approximation type analog-digital converter with a single rough double-fine structure.

Background

With the increasing data requirements, high speed and high resolution analog to digital converters are indispensable. The Pipeline-successive approximation type analog-to-digital converter (Pipeline-SAR ADC) is more energy-saving than the traditional Pipeline ADC, and is better than the SAR ADC in the aspects of speed, resolution and linearity, so that the Pipeline-successive approximation type analog-to-digital converter has great advantages in the field of high-performance high-speed high-resolution ADCs.

As process nodes continue to advance, high performance ADC designs are increasingly relying more on various correction techniques to correct errors and improve performance. The Split ADC (Split-ADC) architecture is a physical architecture with low hardware overhead, low power consumption cost, easy digital modeling, and can achieve good digital background correction. Fig. 1 shows a schematic diagram of a Split-ADC architecture, where an ADC is divided into two half channels to obtain two half channels for sampling the same signal, where each half channel has half of the passive part capacitance and half of the active part transconductance of the original ADC, and thus each half channel is half of the original ADC in terms of area and power consumption overhead, so that the total area and power consumption are substantially the same as those of the original ADC. The final output result of the Split-ADC is obtained by averaging the quantization results of the two half channels, so that the noise performance is consistent with that of the original ADC. Fig. 2 shows an implementation of a pipeline-SAR ADC under a conventional Split architecture.

The core idea of the correction method based on Split-ADC is that the basic mathematical property of linearity, namely an approximate expression of translation invariance:

h(x+Δ)＝h(x)+c， (1)

as a judgmentAnd judging whether the quantization transfer function of the other channel is a straight line or not. For the two half-channels, each with a corrected overall transfer function h_A(. and h)_B(. cndot.). Equation (1) can then be indirectly implemented by the following relationship:

h_A(x)-h_B(x)＝a， (2)

h_A(x+Δ)-h_B(x)＝b， (3)

it can be seen that satisfying both (2) and (3) is equivalent to satisfying (1). These two equations represent: in two half channels A and B of the Split-ADC, if the channel A works in two modes, the mode I is normal sampling x, and the mode II is sampling x + delta; while the B channel is always sampled normally. In the error extraction manner described above, the quantized difference a, b of the two channels is always two constants independent of the input signal, which can indicate that A, B channels are linear. Obviously, the judgment condition is irrelevant to the specific structure of the ADC, so that the method has universality, can be popularized to various different ADC design and correction structures, and has good popularization significance. This calibration concept makes it practical to implement two different headroom curves for the ADC at the same input. The switching of the two curves is controlled by the pseudo-random number PN. Fig. 3 shows the difference between these two different margin curves for a 3-bit ADC. Conventionally, to generate two different margin curves, extra analog injection is performed during ADC sampling according to PN.

High precision ADCs require large capacitor arrays and long voltage settling times, which places limits on the speed of the ADC. The Coarse-Fine architecture ADC consists of a Coarse-type Coarse ADC and a Fine ADC. During sampling, the input signal is sampled by the Coarse ADC and the Fine ADC simultaneously. After sampling is finished, the Coarse ADC quantizes the MSBs of the input signals, the quantization result generated quickly controls the high-order turnover of the capacitor array of the Fine ADC, and then the Fine ADC continues to finish low-order quantization. Because the sampling capacitance of the Coarse ADC is far smaller than that of the Fine ADC, the voltage establishment time is obviously shortened, the noise requirement on the comparator is also obviously reduced, and the working speed of the ADC can be further increased.

In addition, the traditional pipeline-SAR ADC relies on a high-performance Operational Transconductance Amplifier (OTA) in a switched capacitor circuit to accurately amplify the margin, and the power consumption is high. Compared with the prior art, the dynamic amplifier without direct current power consumption has a remarkable advantage, but the required multiple requirement of the interstage margin amplification is difficult to achieve due to the low gain.

Disclosure of Invention

The invention aims to provide a split type assembly line-successive approximation type analog-to-digital converter with a single rough double-fine structure, which is low in power consumption and high in efficiency.

The Split type assembly line-successive approximation type analog-digital converter provided by the invention is based on a Split-ADC (analog-digital converter) framework and has a single coarse and double fine structure; the whole circuit is composed of a shared Coarse successive approximation analog-to-digital converter (Coarse Sub-ADC), an Encoder (Encoder), a digital Calibration module (Calibration) and two completely symmetrical half channels (CHA, CHB), as shown in FIG. 4. Wherein:

the shared rough successive approximation analog-to-digital converter comprises a sampling capacitor array with a small capacitance value, a comparator with high noise and low power consumption and successive approximation logic with high speed; the capacitance value of the capacitor array, the noise of the comparator, the power consumption and the like only need to meet the minimum requirement of the ADC resolution. The input signal is quantized by the shared coarse analog-to-digital converter to generate an output code value D_R。

-said two fully symmetrical half-channel (CHA, CHB), each half-channel circuit comprising: a first-stage fine successive approximation type analog-to-digital converter (ADC) with large capacitance, a gain-boosted Dynamic Amplifier (DA) and a second-stage successive approximation type analog-to-digital converter (ADC); wherein, the sampling of the first-stage fine successive approximation type analog-to-digital converter with large capacitance and the sampling of the shared rough successive approximation type analog-to-digital converter sample the input signal at the same time, but do not compare and quantize, but wait for the output result D of the encoder_A/B1And directly overturning the capacitor array, after the overturning is finished and the establishing precision of the margin voltage reaches the requirement of the half-channel ADC, amplifying the margin signal by the gain-boosted Dynamic Amplifier (DA), and enabling the amplified signal to pass through the half-channel ADCThe second stage successive approximation analog to digital converter samples the quantization and generates a second stage digital code value.

In the invention, the resolution of the first-stage fine successive approximation type analog-to-digital converter with large capacitance is the same as that of the shared rough successive approximation type analog-to-digital converter, but the circuit only comprises a sampling capacitor array with larger capacitance value, and the capacitance value of the array is determined by the noise limit required by the resolution of the half-channel ADC.

The input of the encoder is the output code value D of the shared rough successive approximation analog-to-digital converter_RAnd 4 control signals PN _ A, PN _ B, SHUFF _ A, SHUFF _ B of 1-bit, wherein PN _ A, PN _ B controls the margin pattern of the two fully symmetric half-channels (CHA, CHB), respectively. Outputting code D with 6-bit first stage_RFor example, the two residual modes are encoded by:

the PN controls the margin mode selection of the two fully symmetric half-channels CHA, CHB. If PN _ A/B is 0, the encoder works in an NRM mode, namely the original output code value is not modified, the CHA capacitor array and the CHB capacitor array are directly controlled to overturn by using the original output code value, the ADC normally quantizes the input signal Vin, and the margin curve is the same as that of the traditional ADC; if PN _ a/B is 1, the encoder operates in the DRM mode, re-encodes the original output code value, and the generated capacitor array inversion control signal translates the margin curve up and down, so that the ADC quantizes Vin + Δ or Vin- Δ.

The SHUFF controls the last bit capacitive link mode of the first-stage sub-ADC in the two fully symmetric half-channels CHA, CHB, in the manner shown in fig. 4. If SHUFF _ A/B is equal to 0, D is obtained from formula (1)_A/B1Directly controlling the turning of the capacitor array to enable the first stage in the two symmetrical half channels to generate respective residual signals, and if SHUFF _ A/B is equal to 1, obtaining D from formula (1)_A/B1The last two values in the capacitor array are equal, and the weight represents the minimum weight 1 and the second minimum weightThe inverse of the capacitances of weight 2 are interchanged.

The digital calibration module adopts a calibration mode based on a split analog-to-digital converter, and mainly completes calibration based on the split analog-to-digital converter through an adaptive filter: the working process comprises the following steps: inputting digital output code values generated by two channels and a control signal PN _ A, PN _ B, SHUFF _ A, SHUFF _ B, adjusting the weight corresponding to each bit output through an adaptive filter, and compensating non-ideal factors existing in the channels; when the output obtained by subtracting the transfer functions of the two channels is expected to be 0, the transfer functions of the two channels become the same linear function, and thus the calibration of the system is completed.

The split type assembly line-successive approximation type analog-digital converter comprises the following working procedures: the shared rough successive approximation analog-to-digital converter samples input signals, carries out first-stage quantization and generates output code values; the encoder encodes the output according to the pseudo-random numbers PN and SHUFF selected by the control mode, and the generated new code value directly controls the turnover of the capacitor arrays of the two half channels (CHA, CHB); two half channels (CHA, CHB) sample input signals, but do not quantize, but directly generate respective first-stage margins after the output of an encoder controls the capacitor array to turn over; the residual information is amplified by a gain-boosted Dynamic Amplifier (DA) and sampled by a second-stage successive approximation analog-to-digital converter, so that respective second-stage output digital code values are generated; the front and the back two stages work in a pipeline mode; after data synchronization, the output code values of the first and second stages of the two half-channels are subtracted and input to a digital Calibration module (Calibration) for digital background Calibration of the ADC, and the output code values are summed and divided by 2 to be used as the output of the entire ADC.

Further, the gain-boosted dynamic amplifier of the present invention, as shown in fig. 6, includes a common mode level detection module, and an input pair transistor M_N1、M_N2、M_P5And M_P6Cross-coupled load tube M_N3And M_N4Tail current tube M_N0A load capacitor C_1N、C_1PAnd C_2N、C_2P7 control switches S₀-S₆(ii) a Wherein, the pair of tubes M_N1、M_N2、M_P5And M_P6The grids are respectively connected with differential input signals; m_N1、M_N2Source and tail current tube M_N0Is connected to the drain of, M_N0Is switched by the switch S₀Control is connected to ground, M_N0The grid of the dynamic amplifier circuit is connected with bias voltage to control the tail current of the dynamic amplifier circuit; m_N1、M_N2Drain and M of_N3、M_N4Source stage, capacitive load C_2NAnd C_2PTop plate and switch S₁、S₂Connected to a power source; c_2NAnd C_2PThe bottom polar plate is connected to the ground; m_N3、M_N4Are respectively connected to M_N4、M_N3The source stage of (1) forming a cross-coupled connection; m_N4、M_N3The source level of the dynamic amplifier is the output end of the dynamic amplifier, the detection end of the common mode level detection module and the input geminate transistor M_P5And M_P6Are connected via a switch S₃、S₄And a load capacitor C_1N、C_1PThe top pole plate is connected with the switch S₅、S₆Is connected with a power supply; c_1NAnd C_1PThe bottom polar plate is connected to the ground; input pair pipe M_P5And M_P6Is connected to a power supply.

Further, the gain-boosted dynamic amplifier, operating in open loop, has two operating phases: reset phi_RSTAnd amplifying phi_AMPWherein in the reset phase, the switch S₁-S₆Closure, S₀Disconnected, loaded capacitance C_1N、C_1PAnd C_2N、C_2PAll the top plate terminals of the switch are charged to the power supply, and in the amplifying phase, the switch S₁、S₂、S₅、S₆Breaking, S₀、S₃、S₄Closed, input pair of tubes M_N1、M_N2、M_P5And M_P6Receiving input signal, detecting the change of output end common mode voltage by common mode level detecting module, when the output end common mode voltage drops to the set common mode voltage, the switch S₃、S₄Disconnected, loaded capacitance C_1N、C_1PThe voltage on the top plate is the output.

Further, the gain-boosted dynamic amplifier, wherein the load capacitor C_1N、C_1P、C_2N、C_2PThe value of which comprises the parasitic capacitance and the actual capacitance of the connected node, wherein C_1N、C_1PThe sampling capacitor of the next stage ADC is also included.

Different from the traditional method for realizing two margin modes by injecting analog quantity, the invention uses the encoder to encode the output code value of the coarse analog-to-digital converter, directly leads the fine first-stage analog-to-digital converter to obtain two different margin curves and carries out digital input on the offset. In addition, the speed of the coarse analog-to-digital converter is increased, and the time consumption required by the first-stage quantization is effectively reduced.

The foregoing generally describes the features and technical advantages of the present invention, and the following will take a 200MS/s sampling rate, 14bit resolution, Pipelined-SAR ADC based on Split-ADC architecture as an example to more clearly illustrate the concepts of the present invention.

Drawings

Fig. 1 is a schematic diagram of a split adc architecture.

Fig. 2 is a schematic diagram of a conventional split adc-based calibration architecture.

FIG. 3 is a schematic diagram of two margin modes of a 3-bit ADC based on a split ADC calibration method.

Fig. 4 is a schematic diagram of a split-type pipeline-successive approximation type analog-to-digital converter with a single coarse and double fine structure according to the present invention.

FIG. 5 is a schematic diagram of a manner of controlling a 6-bit capacitor array by PN and SHUFF signals.

Fig. 6 is a schematic diagram of a gain-boosted dynamic amplifier.

FIG. 7 is an example of a 200MS/s14-bit Pipelined SAR ADC and its timing diagram.

Detailed Description

The following describes a split-type pipeline-successive approximation type analog-to-digital converter with a single coarse and double fine structure according to the present invention with reference to the accompanying drawings. It is to be noted that the pipeline-successive approximation type analog-to-digital converter provided by the present invention may have many different indexes and performance implementation manners, and the gain-boosted dynamic amplifier and the digital injection margin encoding manner in the present invention may have various application scenarios. The following embodiments are merely exemplary of the present invention, which is provided to illustrate the formation and use of the present invention, and not to limit the present invention.

The split type assembly line-successive approximation type analog-digital converter with the single coarse and double fine structures and the internal module circuit thereof have the advantages that one implementation example is a two-stage pipeline-SAR ADC with the sampling rate of 200MS/s and the 14-bit resolution. According to the requirement of the Split-ADC architecture, a single channel of the ADC is Split into two half channels A and B, and the front and rear two stages work in a pipeline mode, and the specific implementation mode is shown in FIG. 7. In this example, the supply voltage is 0.9V, and the actual amplification of the gain-boosted dynamic amplifier is 16 times.

In this example, the first stage is a 6-bit resolution SAR ADC. The Coarse Sub-ADC has a capacitor array, a comparator and a successive approximation logic circuit, and the first stage analog-to-digital converters of CHA and CHB have only a capacitor array. Phi_SPhase, three capacitor arrays simultaneously sampling the input signal, CK₁Comparator clock for Coarse Sub-ADC; the coder receives an external control signal PN _ A/B, SHUFF _ A/B, and after a Ready signal comes, the output code of the 6-bit of the Coarse Sub-ADC is coded by the coder to respectively control the first-stage capacitor arrays of the CHA and the CHB to overturn. During this time, the gain-boosted dynamic amplifier is at Φ_RST. After the residual amount is produced, the dynamic amplifier enters phi_AMPStarting to perform margin amplification and simultaneously performing second-stage ADC sampling, CK₂Is the clock signal of the second stage comparator. CHA and CHB each have different control signals PN and SHUFF, and randomly have different margin patterns for implementing digital calibration. The front and rear stages in each channel work in a pipeline mode, and high speed can be achieved.

Although the present invention and its advantages have been described in detail, it should be understood that the scope of the invention is not limited to the particular embodiments of the methods and steps described in the specification, and that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A Split type assembly line-successive approximation type analog-to-digital converter is characterized by being based on a Split-ADC (analog-to-digital converter) architecture and having a single coarse and double fine structure; the whole circuit consists of a shared coarse successive approximation analog-to-digital converter, an encoder, a digital calibration module and two completely symmetrical half channels (CHA, CHB), wherein:

the shared rough successive approximation analog-to-digital converter comprises a sampling capacitor array, a comparator and successive approximation logic; the capacitance value of the capacitor array, the noise of the comparator, the power consumption and the like meet the minimum requirement of the resolution of the ADC; the input signal is quantized by the shared coarse analog-to-digital converter to generate an output code value D_R；

-said two fully symmetrical half-channel (CHA, CHB), each half-channel circuit comprising: the system comprises a first-stage fine successive approximation type analog-to-digital converter (ADC), a gain-boosted Dynamic Amplifier (DA) and a second-stage successive approximation type analog-to-digital converter (ADC); wherein, the sampling of the first-stage fine successive approximation type analog-to-digital converter and the sampling of the shared rough successive approximation analog-to-digital converter sample the input signal at the same time, but do not compare and quantize, but wait for the output result of the encoder_DA/B1The capacitor array is directly turned over, after the turning is finished and the building precision of the residual voltage meets the requirement of the half-channel ADC, the gain-boosted Dynamic Amplifier (DA) amplifies the residual signal, the amplified signal is sampled and quantized by the second-stage successive approximation analog-to-digital converter, and a second-stage digital code value is generated;

the input of the encoder is the output code value D of the shared rough successive approximation analog-to-digital converter_RAnd 4 control signals PN _ A, PN _ B, SHUFF _ A, SHU of 1-bitFF _ B, wherein PN _ A, PN _ B controls the margin patterns of the two fully symmetric half-channels (CHA, CHB), respectively;

the digital calibration module adopts a calibration mode based on the split analog-to-digital converter and completes calibration based on the split analog-to-digital converter through an adaptive filter: the working process comprises the following steps: inputting digital output code values generated by two channels and a control signal PN _ A, PN _ B, SHUFF _ A, SHUFF _ B, adjusting the weight corresponding to each bit output through an adaptive filter, and compensating non-ideal factors existing in the channels; when the output obtained by subtracting the transfer functions of the two channels is expected to be 0, the transfer functions of the two channels become the same linear function, and thus the calibration of the system is completed.

2. The split pipelined-successive approximation analog-to-digital converter of claim 1, wherein the first stage fine successive approximation analog-to-digital converter has the same resolution as the shared coarse successive approximation analog-to-digital converter, but the circuit includes only one sampling capacitor array, and the capacitance of the capacitor array is determined by the noise limit required by the resolution of the half-channel ADC.

3. The split pipelined-successive approximation analog-to-digital converter of claim 1, wherein for a first stage of 6-bit output code D in the encoder_RThe coding modes of the two residual modes are as follows:

。

4. the split pipelined-successive approximation analog-to-digital converter of claim 3, wherein in the encoder, PN controls the margin mode selection of the two fully symmetric half-channels CHA, CHB; if PN _ A/B is 0, the encoder works in an NRM mode, namely the original output code value is not modified, the CHA capacitor array and the CHB capacitor array are directly controlled to overturn by using the original output code value, the ADC normally quantizes the input signal Vin, and the margin curve is the same as that of the traditional ADC; if PN _ a/B is 1, the encoder operates in the DRM mode, re-encodes the original output code value, and the generated capacitor array inversion control signal translates the margin curve up and down, so that the ADC quantizes Vin + Δ or Vin- Δ.

5. The split pipelined-successive approximation analog-to-digital converter of claim 3, wherein in the encoder, SHUFF controls the last bit capacitive link mode of the first stage sub-ADC in the two fully symmetric half-channels CHA, CHB; if SHUFF _ A/B is equal to 0, D is obtained from formula (1)_A/B1Directly controlling the turning of the capacitor array to enable the first stage in the two symmetrical half channels to generate respective residual signals, and if SHUFF _ A/B is equal to 1, obtaining D from formula (1)_A/B1And at the last two code value exchange positions, the last two values in the capacitor array are equal, and the weights represent the turning modes of the capacitors with the minimum weight 1 and the second minimum weight 2 to exchange with each other.

6. The split pipeline-successive approximation type analog-to-digital converter according to claim 5, wherein the work flow is as follows: the shared rough successive approximation analog-to-digital converter samples input signals, carries out first-stage quantization and generates output code values; the encoder encodes the output according to the pseudo-random numbers PN and SHUFF selected by the control mode, and the generated new code value directly controls the turnover of the capacitor arrays of the two half channels (CHA, CHB); two half channels (CHA, CHB) sample input signals, but do not quantize, but directly generate respective first-stage margins after the output of an encoder controls the capacitor array to turn over; the residual information is amplified by a gain-boosted Dynamic Amplifier (DA) and sampled by a second-stage successive approximation analog-to-digital converter, so that respective second-stage output digital code values are generated; the front and the back two stages work in a pipeline mode; after data synchronization, the output code values of the first and second stages of the two half channels are subtracted and input into a digital calibration module for digital background calibration of the ADC, and the output code values are summed and divided by 2 to be used as the output of the whole ADC.

7. The split pipeline-successive approximation type analog-to-digital converter according to any one of claims 1 to 6, wherein the gain-boosted dynamic amplifier comprises a common mode level detection module, an input pair transistor M_N1、M_N2、M_P5And M_P6Cross-coupled load tube M_N3And M_N4Tail current tube M_N0A load capacitor C_1N、C_1PAnd C_2N、C_2P7 control switches S₀-S₆(ii) a Wherein:

geminate transistors M_N1、M_N2、M_P5And M_P6The grids are respectively connected with differential input signals; m_N1、M_N2Source and tail current tube M_N0Is connected to the drain of, M_N0Is switched by the switch S₀Control is connected to ground, M_N0The grid of the dynamic amplifier circuit is connected with bias voltage to control the tail current of the dynamic amplifier circuit; m_N1、M_N2Drain and M of_N3、M_N4Source stage, capacitive load C_2NAnd C_2PTop plate and switch S₁、S₂Connected to a power source; c_2NAnd C_2PThe bottom polar plate is connected to the ground; m_N3、M_N4Are respectively connected to M_N4、M_N3The source stage of (1) forming a cross-coupled connection; m_N4、M_N3The source level of the dynamic amplifier is the output end of the dynamic amplifier, the detection end of the common mode level detection module and the input geminate transistor M_P5And M_P6Are connected via a switch S₃、S₄And a load capacitor C_1N、C_1PThe top pole plate is connected with the switch S₅、S₆Is connected with a power supply; c_1NAnd C_1PThe bottom polar plate is connected to the ground; input pair pipe M_P5And M_P6Is connected to a power supply.

8. The split pipelined-successive approximation analog-to-digital converter of claim 7, wherein the gain-boosted dynamic amplifier is a dynamic amplifierThe circuit operates open-loop, having two operating phases: reset phi_RSTAnd amplifying phi_AMPWherein:

in the reset phase, switch S₁-S₆Closure, S₀Disconnected, loaded capacitance C_1N、C_1PAnd C_2N、C_2PAll the top plate terminals of the switch are charged to the power supply, and in the amplifying phase, the switch S₁、S₂、S₅、S₆Breaking, S₀、S₃、S₄Closed, input pair of tubes M_N1、M_N2、M_P5And M_P6Receiving input signal, detecting the change of output end common mode voltage by common mode level detecting module, when the output end common mode voltage drops to the set common mode voltage, the switch S₃、S₄Disconnected, loaded capacitance C_1N、C_1PThe voltage on the top plate is the output.

9. The split pipelined-successive approximation analog-to-digital converter of claim 8, wherein in the gain-boosted dynamic amplifier, the load capacitor C is_1N、C_1P、C_2N、C_2PThe value of which comprises the parasitic capacitance and the actual capacitance of the connected node, wherein C_1N、C_1PThe sampling capacitor of the next stage ADC is also included.