CN115801003B

CN115801003B - Multi-step analog-to-digital converter and implementation method thereof

Info

Publication number: CN115801003B
Application number: CN202310089393.7A
Authority: CN
Inventors: 唐希源; 王宗楠
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2023-02-09
Filing date: 2023-02-09
Publication date: 2023-04-21
Anticipated expiration: 2043-02-09
Also published as: CN115801003A

Abstract

The invention discloses a multi-step analog-to-digital converter and an implementation method thereof, which are used for carrying out structural improvement on an incremental scaling analog-to-digital converter, and adopting a noise shaping successive approximation type analog-to-digital converter to carry out fine quantization of the analog-to-digital converter; comprising the following steps: a multi-bit digital ramp analog-to-digital converter with digital prediction, a multi-bit multi-stage noise shaping successive approximation analog-to-digital converter, and a configurable floating voltage domain amplifier. The invention adopts a working mode of sampling for multiple times and converting for one time, configures the quantization process of the analog-to-digital converter into coarse quantization for one time and then carries out fine quantization for multiple times; the multi-step analog-to-digital converter has high energy efficiency and high precision, medium input bandwidth and low data output delay, and can be suitable for various application scenes of the Internet of things.

Description

Multi-step analog-to-digital converter and implementation method thereof

Technical Field

The invention belongs to the technical field of integrated circuit design, relates to an analog-to-digital converter integrated circuit design technology, and particularly relates to a multi-step analog-to-digital converter structure with high energy efficiency and high precision and an implementation method thereof.

Background

In recent years, the emerging application fields such as the internet of things and the like put more stringent requirements on the precision and the energy efficiency of analog-to-digital converters (ADCs). Particularly in applications of mobile terminal devices, the energy-efficient successive approximation analog-to-digital converter (sar adc) is limited by thermal noise of the comparator, which tends to reduce the accuracy of the whole system, while the high-accuracy Sigma-delta adc consumes a large amount of energy, which causes a bottleneck to the endurance time of the battery of the device. Meanwhile, the Sigma-DeltaADC requires a complex digital processing circuit, and long data delay causes that the Sigma-DeltaADC cannot obtain a quantization result of an input analog signal in real time, so that the Sigma-DeltaADC is not beneficial to integration in a system. In order to solve the problem that it is difficult to achieve both high precision and high energy efficiency in ADC, some new ADC structures such as a scaling analog-to-digital converter (Zoom ADC) and a noise shaping successive approximation type analog-to-digital converter (noiseshapingsar ADC) have been proposed by designers in recent years.

The ZoomADC is a multi-step analog-to-digital converter, which adopts SARADC with low power consumption in a first stage and adopts a high-precision Sigma-Delta ADC in a second stage, and performs first-step coarse quantization and second-step fine quantization on a sampled input signal respectively. After the coarse quantization is finished, the reference level range of the second-stage Sigma-DeltaADC is adjusted according to the coarse quantization result of the first-stage SARADC, so that the input signal falls in the reduced reference level range, the size of the input signal of the loop filter in the Sigma-DeltaADC is greatly reduced, the power consumption of the loop filter is further reduced, and the fine quantization of high energy efficiency is realized. However, in order to realize high precision, the traditional ZoomADC needs a high oversampling rate, so that the second level Sigma-DeltaADC performs multiple conversions, but each conversion damages the residual voltage value stored on the first level SARADC, and the residual voltage can be recovered by resampling.

The existing Noiseshapin SARADC uses low-power SARADC as a quantizer of a Sigma-DeltaADC, and the characteristic that SARADC can perform multi-bit quantization is utilized, so that the oversampling rate is greatly reduced, and the input bandwidth and the applicability of the system are improved. However, the existing Noiseshapin SARADC generally needs a higher-order loop filter at a lower oversampling rate to meet the requirement of high precision because of no coarse quantization of the first stage, and hardware overhead and design complexity are remarkably improved.

Therefore, the ADC which can be applied to the emerging application fields such as the Internet of things and the like and has high energy efficiency and high precision is designed.

Disclosure of Invention

Aiming at the problems existing in the prior art, the invention provides a high-energy-efficiency high-precision multi-step analog-to-digital converter and an implementation method thereof, and the proposed multi-step analog-to-digital converter circuit is a novel incremental scaling analog-to-digital converter (Incremental ZoomADC) circuit, which adopts a noise shaping successive approximation type analog-to-digital converter (Noiseshapin SARADC) to carry out second-stage fine quantization in a scaling type analog-to-digital converter (Zoom ADC), and the designed analog-to-digital converter adopts a working mode of one-sampling multi-conversion, so that the high-energy-efficiency and high-precision can be considered, and the circuit also has medium input bandwidth and low data output delay and can be suitable for various application scenes of the Internet of things.

The present invention defines the following term names and corresponding english names:

an incremental scaling analog-to-digital converter (encrementalzoom adc);

noise shaping successive approximation type analog-to-digital converter (Noiseshapin SARADC)

A digital ramp analog-to-digital converter (digital slopeadc);

MSB (MostSignificantBit);

LSB (Least Significant Bit );

the invention provides a multi-step analog-to-digital converter, which structurally adopts Noiseshapin SARADC to make fine quantization in a ZoomADC system, and provides a method for performing primary sampling in the ZoomADC system, then performing primary coarse quantization, and then performing multiple fine quantization conversion to achieve the effect of performing primary sampling and multiple conversion. Thereby improving the quantization precision of the ZoomADC system and reducing the power consumption of a fine quantization stage in the ZoomADC system. The invention designs a novel Noiseshapin SARADC implementation mode, which can reduce the hardware cost and the power consumption of NoiseShapingSAR ADC. The invention adopts a multi-order digital prediction technology on the basis of the digital slopeADC, and designs the digital slopeADC with the multi-order digital prediction technology, thereby reducing the capacitance switching power consumption in the digital slopeADC. The invention improves based on the floating voltage domain amplifier, designs the configurable floating voltage domain amplifier, can configure the floating voltage domain amplifier according to different amplifier noise requirements, and reduces the power consumption of the floating voltage domain amplifier.

The technical scheme of the invention is as follows:

a multi-step analog-to-digital converter, namely an incremental scaling analog-to-digital converter; the invention improves the ADC structure in the form of an incremental scaling type analog-to-digital converter, and the main improvement is to adopt Noise Shaping SAR ADC for fine quantization of the ADC in the form. The incremental scaling analog-to-digital converter of the present invention comprises: a multi-bit digital slopeadc with digital prediction, a multi-bit multi-order noiseshapingsar adc, and a configurable floating voltage domain amplifier; taking a multi-bit digital slopeADC with digital prediction as a first stage of an ADC system, and performing first-step coarse quantization; the multi-bit multi-order Noiseshapin SARADC is used as a second stage of the ADC system, and the second step of fine quantization is performed; a configurable floating voltage domain amplifier is embedded in the second stage for removing sampling noise and signal amplification between coarse quantization and fine quantization. Wherein,,

the digital slopeADC with digital prediction and the Noiseshapin SARADC with multiple bits and multiple steps share the same digital-to-analog converter (DAC) component, the DAC component is formed by connecting two parts of capacitor array top plates adopting different coding modes, the two parts are respectively used for the two ADCs correspondingly, the two parts are called coarse quantization DAC corresponding to the digital slopeADC, and the two parts are called fine quantization DAC corresponding to the Noiseshapin SARADC.

In specific implementation, the multi-bit digital slopeADC with digital prediction is a 6-bit digital slopeADC with 2-order digital prediction; the multi-bit, multi-order NS-SARADC is a 7-bit, 2-order NS-SARADC.

The following describes the components in the incremental scaling analog-to-digital converter system according to the present invention in detail:

A. a multi-bit digital slopeadc with digital prediction;

in specific implementation, the invention designs and adopts Digital Slope ADC with second-order digital prediction to carry out coarse quantization, wherein the method comprises four parts of a sampling circuit, a coarse quantization DAC, a comparator and digital logic, the digital logic part is added with the digital predictor (such as a first-order, second-order or multi-order digital predictor) of the invention on the basis of the digital logic of the traditional digital slope ADC, and the coarse quantization DAC part in the digital slope ADC with the multi-order digital prediction adopts thermometer coding for adapting to the multi-order digital predictor.

After the sampling circuit finishes sampling the input signal, the digital slopeADC with the digital prediction at a plurality of bits starts to perform coarse quantization, and the process is as follows: firstly, performing second-order digital prediction on the sampled input signal by using the result of the last two times of coarse quantization, wherein the result of the first and the zeroth times of coarse quantization is considered to be zero, so that the second-order digital prediction of the first and the second times of coarse quantization can also be performed, and after the prediction result is obtained, the prediction result is firstly applied to a coarse quantization DAC; subsequent coarse quantization proceeds on the basis of the prediction result; the voltage on the top polar plate of the DAC is compared with zero by a comparator, a predicted result is changed into one LSB according to the compared result, namely 1 unit capacitor in the coarse quantization DAC is switched, the comparison is repeated once per cycle, and after a few cycles, the compared result of the comparator is turned over (for example, the compared result of the comparator is always positive in the previous cycles, the current compared result is turned negative, namely, the turning over occurs), and the current coarse quantization result is stopped and obtained.

Through analysis and simulation, in an ADC system with the oversampling rate of 8, the coarse quantization of the analog-to-digital converter can be completed by switching 6 unit capacitors at most, namely 6 periods after the prediction result is applied to the coarse quantization DAC by adopting the 6-bit digital slopeADC with the second-order digital prediction. Compared with the prior ZoomADC which adopts SARADC for coarse quantization, all capacitors in the coarse quantization DAC need to be switched once and the switching direction is variable; in the implementation of the invention, the digital slopeADC is improved by combining with the second-order digital prediction, digital Slope ADC with the second-order digital prediction only needs to switch the capacitor corresponding to the input signal, and the switching number and the switching power consumption of the coarse quantization DAC are greatly reduced.

B. Multi-bit, multi-order Noiseshapin SARADC

In specific implementation, the invention designs and adopts the second-order Noiseshapin SARADC to carry out fine quantization, wherein the fine quantization DAC, the comparator, the loop filter and the digital logic are included, the loop filter part adopts the invention to put forward a novel loop filter implementation mode, and the fine quantization DAC part adopts binary coding.

After the coarse quantization is finished, the top electrode plates of the coarse quantization DAC and the fine quantization DAC are both provided with coarse quantized residual voltages; firstly amplifying the residual voltage and adding the output voltage of the loop filter in the fine quantization process, adding the output voltage to the input comparator to be compared with zero, switching one capacitor in the fine quantization DAC according to the comparison result, repeating the process of amplifying, comparing and switching again once in each period, and switching 7 capacitors in the fine quantization DAC in turn from large to small after 7 periods, so as to finish the fine quantization. Each time the fine quantization is completed, a loop filter update is triggered.

The loop filter is a multi-order FIR filter (Finite Impulse Response, finite length unit impulse response filter), a second-order FIR filter can be adopted, and the implementation mode provided by the invention is as follows: the input of the loop filter after the last fine quantization and the last fine quantization is extracted and stored on two delay capacitors through a dynamic buffer: the delay capacitor 1 and the delay capacitor 2 respectively store the single-period delay of the last input signal of the loop filter and the double-period delay of the last input signal of the loop filter in the fine quantization of the time. The output of the loop filter is obtained by using the voltage values stored in the delay capacitor 1 and the delay capacitor 2 during the current fine quantization: the two capacitors are connected in series through the capacitor, so that addition between single-period delay and double-period delay of two input signals on the loop filter can be realized, when the addition is performed, the single-period delay of the last input signal of the loop filter is multiplied by a coefficient 2, the coefficient is realized by splitting the delay capacitor which stores the single-period delay of the last input signal of the loop filter into two parts, and then the two parts of capacitors are connected in series, and the final addition result is the output of the loop filter.

Two capacitors connected in series are connected to the output end of the configurable floating voltage domain amplifier in a capacitor stacking mode, and the addition of the output result of the loop filter and the output result of the configurable floating voltage domain amplifier is realized in the fine quantization process.

When the loop filter is updated after the fine quantization is completed, the input signal of the loop filter in the present period is extracted by a buffer and stored in a third delay capacitor (delay capacitor 3), and a new loop filter output is obtained by using the voltage values stored in the delay capacitor 3 and the delay capacitor 1 in the next fine quantization. After the next fine quantization is completed, the buffer is used for extracting and storing the input signal of the loop filter in the period of the loop filter on the delay capacitor 2, and the voltage values stored on the delay capacitor 2 and the delay capacitor 3 are used for obtaining a new loop filter output in the next fine quantization, and so on.

Compared with the existing loop filter implementation mode, the implementation mode of the loop filter provided by the invention not only can achieve the noise shaping effects of high robustness and high precision, but also can easily expand the filter order to a higher order by only one buffer, thereby reducing the power consumption and hardware cost of the loop filter.

C. Configurable floating voltage domain amplifier design

The configurable floating voltage domain amplifier structure comprises a power supply capacitor, a load capacitor, an amplifying tube and a binary capacitor array; the power supply capacitor comprises a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor comprises a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor;

the working process of the incremental scaling analog-to-digital converter comprises the following steps: a sampling stage, a coarse quantization stage, a fine quantization stage and an update loop filter stage; the three stages of sampling stage, fine quantization stage and updating loop filter stage need the amplifier to have the same gain, but have different requirements on the noise level of the amplifier, wherein the sampling stage needs the least noise of the amplifier, and the updating loop filter stage is inferior, and the fine quantization stage can tolerate larger noise of the amplifier due to the noise shaping effect. The configurable floating voltage domain amplifier provided by the invention comprises the following components in operation:

in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added up by a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor is configured as a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;

in the fine quantization stage, the residual voltage is amplified to inhibit the noise of the comparator, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum and the noise is maximum;

in the loop filter updating stage, the residual voltage is amplified to inhibit loop filter noise and ensure charge conservation on a capacitor DAC, a power supply capacitor is configured to be added by a first part of power supply capacitor and a second part of power supply capacitor, and a load capacitor is configured to be added by a first part of load capacitor and a second part of load;

further, another additional binary capacitor array is added and connected in parallel with the supply capacitor for trimming the supply capacitor of the three-stage amplifier, and the gain of the amplifier is calibrated.

Compared with the prior art, the non-configurable amplifier is adopted, the design is required for meeting the minimum noise requirement, and the configurable floating voltage domain amplifier is used for configuring parameters of the floating voltage domain amplifier according to different noise requirements, so that the power consumption of the amplifier is lower, and the energy efficiency of an ADC system is improved.

The incremental scaling analog-to-digital converter configures the quantization process of the incremental ZoomADC into coarse quantization for multiple times and then fine quantization is carried out; the implementation method comprises the following steps:

1) Preparing a multi-bit digital slope ADC, comprising a sampling circuit, a DAC, a comparator and digital logic, and improving the structure based on Digital Slope ADC, wherein a multi-order digital prediction element is added to the digital logic in the digital slope ADC to prepare Digital Slope ADC with multi-bit digital prediction;

structurally coarsely quantizing Digital Slope ADC with multi-bit band multi-order digital prediction;

2) The preparation method comprises four parts of DAC, loop filter, comparator and digital logic, wherein the loop filter part adopts the novel loop filter implementation mode provided by the invention.

Performing fine quantization by using a multi-bit multi-order NS-SAR ADC;

3) The multi-bit digital slope analog-to-digital converter with digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter (DAC) component, and the component is formed by connecting two parts of capacitor array top polar plates adopting different coding modes; the digital-to-analog converter used for the digital slope analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used for the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;

4) Designing and preparing a configurable floating voltage domain amplifier, i.e. improving on the basis of the existing floating voltage domain amplifier; the power supply capacitor and the load capacitor of the floating voltage domain amplifier are divided into a plurality of parts, and control elements with various configurations are added into the digital logic part of the amplifier, so that the power supply capacitor configuration and the load capacitor configuration are carried out, the configurable property of the amplifier is increased, and the power supply capacitor and the load capacitor configuration are configured into different modes according to different noise requirements of the amplifier and different working stages.

The floating voltage domain amplifier is used for amplifying and sampling noise elimination between coarse quantization and fine quantization.

5) The Digital Slope ADC of the multi-bit band multi-order digital prediction is used as a first-stage ADC, the Noiseshapin SARADC of the multi-bit multi-order is used as a second-stage ADC, the first-stage ADC and the second-stage ADC are connected through a top polar plate of a DAC component, a configurable floating voltage domain amplifier is embedded in the second-stage ADC, and the second-stage ADC is arranged between the DAC and a loop filter, so that the improved IncrementalZoomADC is obtained.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides an incremental scaling analog-to-digital converter, which adopts multi-bit multi-order Noiseshapin SARADC to carry out fine quantization in a Zoom ADC.

Compared with the traditional ZoomADC which can recover residual voltage by resampling after finishing each fine quantization, the incremental analog-digital converter provided by the invention can carry out multiple fine quantization without resampling after one coarse quantization, namely one sampling and multiple conversion, thereby saving a large amount of sampling operations, improving the input bandwidth of the system and greatly relieving the requirement on an input driving circuit.

Compared with the existing implementation method, the Noise Shaping SAR implementation method provided by the invention not only can realize a stable noise shaping effect, but also can reduce hardware cost and power consumption of the NS-SAR ADC.

The digital slopeADC with the multi-order digital prediction technology provided by the invention can reduce the capacitance switching power consumption in the existing digital slopeADC.

Compared with the existing floating voltage domain amplifier, the configurable floating voltage domain amplifier provided by the invention can be configured into a plurality of modes according to different amplifier noise requirements, and the power consumption of the floating voltage domain amplifier is reduced.

Drawings

FIG. 1 is a schematic diagram of an incremental scaling analog-to-digital converter according to the present invention;

wherein,,

is an input signal; />

Sampling the input signal when the sampling signal is set high; />

For coarse quantization signal, coarse quantization is carried out when the signal is set high; />

For fine quantization signal, fine quantization is carried out when the signal is set high; />

And resetting the system when the reset signal is set high.

Fig. 2 is a timing diagram illustrating the operation of the incremental scaling analog-to-digital converter according to the present invention.

Fig. 3 is a schematic circuit diagram of an incremental scaling analog-to-digital converter according to the present invention.

Fig. 4 is a schematic diagram illustrating an operation of the incremental scaling analog-to-digital converter according to the present invention.

Fig. 5 is a schematic diagram illustrating the operation of a loop filter in an incremental scaling analog-to-digital converter according to the present invention.

Fig. 6 is a circuit diagram of a configurable floating voltage domain amplifier in an ADC of the present invention.

Detailed Description

The invention is further illustrated by the following detailed description in conjunction with the accompanying drawings, which do not limit the scope of the invention in any way.

The incremental zoom ADC (analog-to-digital converter) provided by the invention comprises a coarse quantization ADC and a fine quantization ADC, wherein the implementation of the coarse quantization ADC is improved based on a digital slopeADC (digital slope analog-to-digital converter) and is designed into a multi-bit digital slopeADC with second-order digital prediction. The fine quantization ADC is realized by Noiseshapin SARADC, and the coarse quantization ADC and the fine quantization ADC share a capacitor (DAC). The incremental scaling type analog-to-digital converter structure provided by the invention not only has the technical advantages of high energy efficiency and multi-bit quantization of the Noiseshapin SARADC, but also utilizes the coarse quantization and reference level range adjustment technology in the ZoomADC, and can meet the high-precision requirement of analog-to-digital conversion without a high-order loop filter.

As shown in fig. 1 and fig. 2, in the implementation of the incremental zoom adc of the present invention, the first stage is a 6-bit digital slopeadc for coarse quantization, the second stage is a 7-bit noiseshapingsar adc for fine quantization, and a floating voltage domain amplifier for inter-stage signal amplification and sampling noise cancellation. The DigitalSlopeADC and the NoiseShapingSARADC share one DAC component. In the one-time complete analog-to-digital conversion process of the incremental ZoomADC, firstly, the digital SlopeADC is used for inputting signals

Sampling and eliminating sampled noise by using a floating voltage domain amplifier, then performing first coarse quantization on the sampled input signal by using a digital sample ADC, performing inter-stage amplification by using the floating voltage domain amplifier after coarse quantization is finished, and performing 4 times of fine quantization by using a Noiseshapin SARADC, thereby realizing multiple times of fine quantization conversion after one time of sampling. The process is repeated eight times, 8 times of sampling, 8 times of coarse quantization and 32 times of fine quantization are carried out, 32 quantization results are obtained, and the 32 quantization results are processed by a sampling filter to obtain a result of analog-to-digital conversion.

The circuit and the working process of the ADC system are shown in fig. 3 and 4, and the whole ADC system comprises the following 4 working stages:

1) Sampling:

at the position of

When the voltage is high, the sampling switch is closed to connect the bottom plate of the DAC to the input signal>

On top plate to common mode level +.>

On the amplifier and the capacitor->

Resetting. At->

Time->

Is set to low level, the DAC top pole plate switch is opened, the input signal is input +>

And first sampling noise->

Is fixed on the DAC and triggers the amplifier to begin amplifying. At->

Time of day

Is set low, sampling switch and capacitor +.>

Is opened, will->

To->

Time varying input signal

And first sampling noise->

Amplifying and sampling to capacitance +.>

And the sampling of the input signal and the elimination of sampling noise are completed.

2) Coarse quantization stage:

after sampling, firstly, according to the coarse quantization result of the last two sampling periods

And->

Second-order prediction is carried out on the input signal value of the sampling period, and the prediction result is +.>

And switching the bottom plate voltage of the unit capacitor corresponding to the number of the predicted results in the DAC. And triggering a comparator to compare the voltages of the top electrode plates of the DAC, and switching the voltages of the bottom electrode plates of one unit capacitor in the DAC according to the comparison result in each conversion period. When the comparison of a plurality of conversion periods and the inversion of the comparison result are detected, the comparison is performed again, the compensation capacitance of 0.5 unit capacitance in the DAC is switched, the coarse quantization is completed, and the coarse quantization result of the sampling period is obtained>

。

3) Fine quantization stage

In each conversion period of the fine quantization stage, firstly triggering an amplifier to amplify the residual voltage on the top polar plate of the DAC, and superposing the amplified signal on a noise elimination capacitor

And input into a comparator after passing through an FIR filter, and switch the bottom polar plate of the corresponding bit in the DAC according to the comparison resultThe voltage completes one conversion period, and the process is repeated for 7 times to complete one fine quantization.

4) Loop filter update phase

The loop filter is implemented by a second-order FIR filter, in the first embodiment shown in FIG. 5

In the sub-fine quantization, the capacitance in the filter is +.>

And->

The feedback signal after the last fine quantization is stored>

Capacitance->

And->

The feedback signal after the last fine quantization is stored>

Capacitance +.>

And->

Connected in parallel and with a capacitance->

And->

Reverse series connection to obtain +.>

Is provided. Complete->

After secondary fine quantization, a primary FIR filter needs to be updated, an amplifier is triggered to amplify the residual voltage on a DAC top polar plate after the fine quantization is finished, and the amplified signal is overlapped with a capacitor>

And the feedback signal after the fine quantization is finished is obtained after the FIR filter>

It is stored in capacitor +.>

And->

On, a cyclic shift operation of the capacitor is performed, using the capacitor +.>

And->

Replacement capacitor->

And->

Is (are) capacitance->

And->

Replacement capacitor->

And->

Is (are) capacitance->

And->

Replacement capacitor->

And->

The position of (2) can be completed>

And updating the secondary loop filter. In the next refinement, i.e. +.>

In the case of sub-fine quantization, the first->

The output value of the feedback of the FIR filter after the second update is updated to +.>

Complete->

The feedback signal after sub-fine quantization is stored in the capacitor +.>

And->

And again cyclically moving the capacitance position. And repeating the operation of saving the feedback signal and the capacitance shift after each fine quantization is completed, so that the second-order FIR filter can be updated.

After the loop filter is updated, the voltage of the DAC bottom polar plate corresponding to the fine quantization ADC is reset.

In the 4 operating phases of the ADC system of the invention, the amplifier is used in the sampling phase, the fine quantization phase and the loop filter update phase, the amplifier of the invention is implemented with a configurable floating voltage domain amplifier structure as shown in fig. 6, in which the supply capacitance

Comprising a first part of the supply capacitance->

Second part supply capacitor->

And a third part supply capacitance->

Three parts, load capacitance->

Then contain the first partial load capacitance +.>

And a second partial load capacitance->

Two parts. In the sampling phase the amplifier is most sensitive to noise, so the supply capacitor is configured to +.>

The load capacitance is configured as +.>

The power consumption of the amplifier is maximum and the noise is minimum; in the fine quantization stage, the noise of the amplifier is shaped to tolerate larger noise, so the supply capacitor is configured to +>

The load capacitance is configured as +.>

The power consumption of the amplifier is minimum and the noise is maximum; during the loop filter update phase, the amplifier has moderate noise and power consumption, and the supply capacitor is configured to

The load capacitance is configured as +.>

. An additional binary capacitor array is added and connected in parallel with the power supply capacitor for fine-tuning the power supply capacitor size of the three-stage amplifier, the gain of the amplifier is calibrated, and the gain of the amplifier can meet the design requirement after one factory calibration.

It should be noted that the purpose of the disclosed embodiments is to aid further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.

Claims

1. A multi-step analog-to-digital converter is characterized in that the structure of an incremental scaling analog-to-digital converter is improved, and a noise shaping successive approximation type analog-to-digital converter (Noise Shaping SAR ADC) is adopted for fine quantization of the analog-to-digital converter; comprising the following steps: a multi-bit digital ramp analog-to-digital converter (digital slopeADC) with digital prediction, a multi-bit multi-order noise shaping successive approximation analog-to-digital converter, and a configurable floating voltage domain amplifier; realizing one-time sampling and multiple conversion, namely performing one-time coarse quantization after one-time sampling, and performing multiple-time fine quantization conversion;

the multi-bit digital slope analog-to-digital converter with digital prediction is used as a first stage of the multi-step analog-to-digital converter and is used for performing first-step coarse quantization; the multi-bit multi-order noise shaping successive approximation type analog-to-digital converter is used as a second stage of the multi-step analog-to-digital converter and is used for performing second-step fine quantization; a configurable floating voltage domain amplifier embedded in the second stage for removing sampling noise and performing signal amplification between coarse quantization and fine quantization;

the multi-bit digital slope analog-to-digital converter with digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter component, and the component is formed by connecting two parts of capacitor array top polar plates adopting different coding modes; the digital-to-analog converter used for the digital slope analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used for the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;

A. the digital ramp type analog-to-digital converter with digital prediction comprises: a sampling circuit section, a coarse quantization digital-to-analog converter section, a comparator section, and a digital logic section; wherein the digital logic portion incorporates a multi-order digital predictor; the coarse quantization digital-to-analog converter part adopts thermometer coding;

B. the multi-bit multi-order noise shaping successive approximation type analog-to-digital converter comprises a fine quantization digital-to-analog converter part, a comparator part, a loop filter part and a digital logic part; wherein the loop filter part adopts a novel loop filter; the fine quantization digital-to-analog converter part adopts binary coding;

the novel loop filter is a multi-order finite length unit impulse response filter, and the order of the filter can be expanded to a higher order by only one buffer; the method specifically comprises the following steps:

extracting and storing the input of the loop filter after the last fine quantization and the last fine quantization are completed on two delay capacitors, wherein the two delay capacitors respectively store single-period delay of the last input signal of the loop filter and double-period delay of the last input signal of the loop filter;

the output of the loop filter at the current fine quantization is obtained by using the voltage values stored on the two delay capacitors: the two capacitors are connected in series through the capacitor, the single-period delay and the double-period delay of the two input signals on the loop filter are added, the single-period delay of the last input signal of the loop filter is multiplied by a set coefficient, the delay capacitor which holds the single-period delay of the last input signal of the loop filter is split, and the capacitors are connected in series; the addition result is the output of the loop filter;

C. the configurable floating voltage domain amplifier structure comprises a power supply capacitor, a load capacitor, an amplifying tube and a binary capacitor array; the power supply capacitor comprises a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor comprises a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor;

the configurable floating voltage domain amplifier can be configured with noise of different sizes while realizing gains of the same size at different stages of the working process of the incremental scaling analog-to-digital converter; the configurable floating voltage domain amplifier, in operation, comprises:

in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added up by a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor is configured to be added by the first partial load capacitor, the second partial load capacitor and the noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;

in the loop filter updating stage, loop filter noise is suppressed by amplifying the residual voltage, and conservation of charge of a capacitor in the digital-to-analog converter is ensured, a power supply capacitor is configured to be added by a first part of power supply capacitor and a second part of power supply capacitor, and a load capacitor is configured to be added by a first part of load capacitor and a second part of load.

2. The multi-step analog-to-digital converter of claim 1, wherein the multi-bit band digitally predicted digital ramp analog-to-digital converter is a 6-bit band 2-order digital prediction; the multi-bit, multi-order noise shaping successive approximation analog-to-digital converter is 7 bits, 2 orders.

3. A method for realizing a multi-step analog-to-digital converter is characterized by designing a multi-step analog-to-digital converter, namely an incremental scaling analog-to-digital converter, configuring the quantization process of the analog-to-digital converter into one-time sampling, performing one-time coarse quantization, and performing multiple-time fine quantization, namely one-time sampling and multiple-time conversion, wherein repeated sampling is not needed between the fine quantization; the implementation method comprises the following steps:

1) Preparing a multi-bit digital slope type analog-to-digital converter with digital prediction;

the structure of the digital slope analog-to-digital converter is improved, and a multi-order digital prediction element is added to a digital logic part in the digital slope analog-to-digital converter to prepare the digital slope analog-to-digital converter with multi-bit digital prediction, wherein the digital slope analog-to-digital converter comprises a sampling circuit, a digital-to-analog converter, a comparator and digital logic and is used for coarse quantization;

2) Preparing a multi-bit and multi-step noise shaping successive approximation type analog-to-digital converter for fine quantization, wherein the multi-bit and multi-step noise shaping successive approximation type analog-to-digital converter comprises a digital-to-analog converter, a loop filter, a comparator and a digital logic part; wherein the loop filter part adopts a novel loop filter; the novel loop filter specifically comprises:

3) The multi-bit digital slope analog-to-digital converter with digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter component, and the component is formed by connecting two parts of capacitor array top polar plates adopting different coding modes; the digital-to-analog converter used for the digital slope analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used for the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;

4) Designing and preparing a configurable floating voltage domain amplifier; the method is used for amplifying and sampling noise elimination between coarse quantization and fine quantization;

an improvement over existing floating voltage domain amplifiers; the power supply capacitor and the load capacitor of the floating voltage domain amplifier are divided into a plurality of parts, and a plurality of configuration control elements are added into the digital logic part of the amplifier, so that the configuration of the power supply capacitor and the load capacitor is carried out, the configurable property of the amplifier is increased, and the power supply capacitor and the load capacitor are configured into different modes in different working stages according to different noise requirements of the amplifier;

5) Connecting a digital slope analog-to-digital converter with multi-bit and multi-order digital prediction and a multi-bit and multi-order noise shaping successive approximation analog-to-digital converter through a top polar plate of a digital-to-analog converter component; the configurable floating voltage domain amplifier is embedded in the multi-bit and multi-order noise shaping successive approximation type analog-digital converter and is arranged between the digital-analog converter and the loop filter, so that the improved incremental scaling type analog-digital converter is obtained.

4. A method for implementing a multi-step analog-to-digital converter as defined in claim 3, wherein after the sampling circuit samples the input signal, the multi-bit digital ramp analog-to-digital converter with digital prediction performs a coarse quantization process comprising:

firstly, performing second-order digital prediction on the sampled input signal by using the result of the previous two times of coarse quantization;

the result of the first and zeroth coarse quantization is zero;

after obtaining the prediction result, firstly applying the prediction result to a coarse quantization digital-to-analog converter;

coarse quantization is then performed: comparing the voltage on the top polar plate of the coarse quantization digital-to-analog converter with zero by using a comparator, and changing a prediction result by one LSB according to the comparison result, namely switching 1 unit capacitor in the coarse quantization digital-to-analog converter;

repeating the process of comparing and switching once in each period;

after a few periods, the comparison result of the comparator is overturned, the operation is stopped, and the result of the current coarse quantization is obtained.

5. The method of claim 4, wherein the top plates of the coarse digital-to-analog converter and the fine digital-to-analog converter are both coarse quantized residual voltages after coarse quantization.

6. The method of implementing a multi-step analog-to-digital converter of claim 5, wherein the residual voltage is first amplified and the output voltage of the loop filter during the current fine quantization is added, and the added input comparator is compared with zero;

switching one capacitor in the fine quantization digital-to-analog converter according to the comparison result;

repeating the process of amplifying, comparing and switching once in each period;

after a plurality of periods, the capacitance in the fine quantization digital-to-analog converter is sequentially switched from large to small, so that the fine quantization is completed;

the loop filter update is triggered after each fine quantization is completed.

7. A method of implementing a multi-step analog-to-digital converter as claimed in claim 3, wherein the configurable floating voltage domain amplifier is operative to include:

in the loop filter update phase, loop filter noise is suppressed and conservation of charge on the capacitor DAC is ensured by amplifying the residual voltage, the supply capacitor is configured as a first partial supply capacitor and a second partial supply capacitor added, and the load capacitor is configured as a first partial load capacitor and a second partial load added.

8. The method of implementing a multi-step analog-to-digital converter of claim 1, wherein two capacitors connected in series are connected to the output of the configurable floating voltage domain amplifier in a stacked manner to effect addition of the loop filter output result to the amplifier output result during the current fine quantization.

9. The method for implementing a multi-step analog-to-digital converter of claim 8, wherein when the loop filter is updated after the current fine quantization is completed, the buffer is used to extract and store the input signal of the loop filter in the present period onto the third delay capacitor, and the voltage values stored on the third delay capacitor and the first delay capacitor are used to obtain a new loop filter output in the next fine quantization; and after the next fine quantization is finished, the buffer is used for extracting and storing the input signal of the loop filter in the period of the loop filter on the second delay capacitor, and the voltage values stored on the second delay capacitor and the third delay capacitor are used for obtaining a new loop filter output in the next fine quantization.