JPH05183436A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the integrated circuit device. CONSTITUTION:Power supply switches 11, 12, 13 are respectively provided to function blocks 1, 2, 3 in one and same integrated circuit device. In the case of the mode using a signal processing circuit section 4 but not using a signal processing circuit section 5, a control circuit 10 closes the switches 11, 12 for the function blocks 1, 2 in the signal processing circuit section 4 to supply power to the blocks and opens the switch 13 of the function block 3 exclusive for the signal processing circuit section 5 to stop the power supply. Thus, useless power consumption is reduced to reduce the load of the power supply section, a battery of a small capacity or a small power supply circuit is used thereby miniaturizing the device applied with this integrated circuit device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device having two or more signal processing circuit units each composed of a plurality of functional blocks.

[0002]

2. Description of the Related Art In recent years, battery-powered small portable electronic devices such as so-called headphone stereo devices have become widespread, and in such small electronic devices, reduction of power consumption is an important issue. Has been done. This is because a small battery with a small capacity or a small power supply circuit can be used to further downsize an electronic device, or even when a battery of the same size is used, a long life is realized.

Various proposals have been made to reduce the power consumption. As specific examples thereof, low power consumption parts are used, or an automatic power-off function for automatically turning off the power after the operation is completed. It is possible to give it.

[0004]

By the way, in digital equipment such as a digital tape recorder,
Digital signal processing units generally consume less power, but
Power consumption tends to increase in the parts that handle analog signals, such as the / D converter, the D / A converter, and the analog amplifier, in order to ensure performance such as S / N and distortion. These parts include parts used and parts not used according to various operation modes of the device, and parts not used are
Usually, it is in a so-called no signal state, a stationary state, a standby state, or the like. However, even in such a state, there is a drawback that the power consumption of the portion handling the analog signal is relatively large.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an integrated circuit device capable of reducing power consumption.

[0006]

An integrated circuit device according to the present invention includes a signal processing circuit section including a plurality of functional blocks.
In the integrated circuit device, which has the above, these functional blocks are composed of a functional block shared by two or more signal processing circuit units and a dedicated functional block for each signal processing circuit unit. Has a power-on / off means for each block and is dedicated to the second signal processing circuit section in a mode in which the first signal processing circuit section is used and the second signal processing circuit section is not used. The above-mentioned problem is solved by turning off the power supply of the function block.

To turn on / off the power supply, a switch may be inserted and connected in series with the power supply line to turn on / off the switch, or the differential current sink current source of the operational amplifier may be turned off. Good. It is preferable that the functional block for turning off the power supply is applied to a portion that handles an analog signal with relatively high power consumption. Specifically, one of the plurality of signal processing circuit units is A /
The D conversion unit and the other one may be the D / A conversion unit.

[0008]

By turning off the power of the functional blocks that are not used in the same integrated circuit, unnecessary power consumption of the integrated circuit can be reduced.

[0009]

1 is a block circuit diagram showing a schematic configuration of an embodiment of an integrated circuit device according to the present invention. In FIG. 1, a plurality of functional blocks 1, 2 and 3 are provided inside the integrated circuit device. In the functional blocks 1 and 2, the first signal processing circuit unit 4 and in the functional blocks 2 and 3 are provided. Each of the second signal processing circuit units 5 is configured. That is, the functional block 1 is dedicated to the first signal processing circuit unit 4, the functional block 2 is shared by the first and second signal processing circuit units 4 and 5, and the functional block 3 is the second signal processing circuit unit. It is designed to be used exclusively by 5. The control circuit 10 controls on / off of the power-on / off switches 11, 12, and 13 provided in each of the functional blocks 1, 2, and 3.
3 is + B via these switches 11, 12 and 13.
It is connected to the power supply terminal 6.

As an integrated circuit device having such a structure,
For example, an A / D conversion / D / A conversion combined IC, an encoder / decoder combined IC, and the like are conceivable. The first signal processing circuit unit 4 is used as an A / D converter or an encoder, and a second signal processing circuit. The unit 5 is used as a D / A converter or a decoder. in this case,
When one circuit unit is being used, the other circuit unit is unnecessary, so that control is performed to turn off the power supply of an unnecessary functional block in the same IC.

That is, the control circuit 10 has a first
In the mode in which only the signal processing circuit unit 4 is used and the second signal processing circuit unit 5 is not used, the switch 13 of the functional block 3 dedicated to the second signal processing circuit unit 5 is used.
And turn off the power supply. Further, in the mode in which only the second signal processing circuit unit 5 is used and the first signal processing circuit unit 4 is not used, the control circuit 10 is
The switch 11 of the functional block 1 dedicated to the signal processing circuit section 4 is turned off to cut off the power supply.

As described above, even in the same IC, by cutting off the power supply to the functional blocks that are not used depending on the mode, the power consumption is reduced, and when applied to a portable small device, a small battery having a small capacity is used. It can be used, or can have a long battery life with the same battery capacity.

A concrete example of the switches 11, 12 and 13 will be described with reference to FIG. In the example of FIG. 2, an operational amplifier 21 (or a comparator or the like) is used as the functional block.
1, the difference between the respective inputs to the non-inverting input terminal 22 and the inverting input terminal 23 is amplified and taken out from the output terminal 24. A power supply control signal from the control circuit 10 or the like is supplied to the control terminal 25. When the power supply control signal is "H", the power is turned on, and when it is "L", the power is turned off. This power supply control signal is inverted by the inverter 26 and sent to the gate of a P-channel MOS (metal oxide semiconductor) transistor 27. The MOS transistor 27 is inserted and connected between the power supply terminal 28 and the operational amplifier 21, and the control terminal 2
The ON / OFF control is performed according to the power control signal from the control circuit 5 to control the supply / interruption of the power to the operational amplifier 21.

As described above, a method of turning on / off the differential current sink current source of the operational amplifier may be used instead of turning on / off the amplifier power supply by the switch (MOS transistor 27) inserted and connected in series. ..

Next, as another embodiment of the present invention, an A / D
A specific example in which the present invention is applied to an IC for both conversion and D / A conversion will be described with reference to FIG. This Figure 3
The so-called cascade integration type A / D converter configuration previously disclosed by the applicant of the present application in Japanese Patent Laid-Open No. 61-163723 and the like is the same as the D / A converter configuration using this A / D converter configuration. It shows a specific example incorporated in an integrated circuit.

In FIG. 3, the analog input terminal 31
An analog signal to be digitally converted is input to. This input analog signal is supplied to the selected terminal a of the changeover switch 34 via the input volume amplifier 32 and the emphasis amplifier 33. Changeover switch 34
The output signal from is supplied to the selected terminal a of the changeover switch 36, the analog output terminal 37, and the headphone volume variable resistor 38 via the LPF (low pass filter) amplifier 35. The output signal from the variable resistor 38 is taken out as a headphone amplifier output via the headphone output terminal 39.

Next, the output signal from the change-over switch 36 is sent to the inverter amplifier 43 through the resistor 41 in the integrator 40 and the sample-hold switch 42. An integrating capacitor 44 is connected between the input terminal and the output terminal of the amplifier 43 in the integrator 40, and the resistor 4
1. A resistor 45 is connected between the connection point of the switch 42 and the output terminal of the amplifier 43. Between the input terminal of the amplifier 43 and the negative power supply -V, for example, a series connection circuit of a switch 46 and a first reference current source 47, and a switch 48.
And a series connection circuit of the second reference current source 49 are connected in parallel. The ratio of the current I ₂ of the current I ₁ of the first reference current source 47 a second reference current source 49, typically 2 ⁿ (n
Is an integer) or 2 ⁿ -1. For example, I ₁ / I ₂ = 2 ⁸ = 256.

The output signal from the inverter amplifier 43 of the integrator 40 is supplied to comparators 51 and 52, which are differential amplifiers and the like. The comparator 51 has a first threshold V
_th1 and the second threshold value V _th2 are supplied to the comparator 52, respectively, and the comparison outputs from these comparators 51 and 52 are supplied to the control circuit 53. The digital output signal is output from the control circuit 53 to the output terminal 5
It is taken out via 4. The configuration described above is the configuration of a so-called cascade integration type A / D converter.

Further, a mode switching control signal or the like is supplied from the CPU (or so-called microcomputer) or the like to the control circuit 53 via the input terminal 56. From the control circuit 53, control signals for controlling the changeover switches 34, 36 and the switches 42, 46, 48, etc.,
The power ON / OFF control signal and the like as described above are output.

Next, the D / A converter is constructed by adding the following configuration in addition to the configuration of the A / D converter. First, a digital signal to be converted into an analog signal is supplied to the control circuit 55 via the digital input terminal 55. The output from the inverter amplifier 43 of the integrator 40 is sent to the inverter amplifier 63 via the resistor 61 in the deglitching sample hold circuit 60 and the sample hold switch 62. A holding capacitor 64 is connected between the input terminal and the output terminal of the amplifier 63 in the sample-hold circuit 60, and a resistor 61 is connected between the connection point of the resistor 61 and the switch 62 and the output terminal of the amplifier 63. 65 is connected.
The output from the inverter amplifier 63 of the deglitching sample hold circuit 60 is the de-emphasis amplifier 6
It is sent to the selected terminal b of the changeover switch 34 via 6. Further, the precharge voltage from the input terminal 67 is sent to the selected terminal b of the changeover switch 36 via the precharge buffer amplifier 68.

A / D, D / A having the above structure
The operation of the dual-purpose IC will be described with reference to FIGS.

First, during the A / D conversion operation, the A / D conversion mode switching control signal is supplied to the control circuit 53 via the input terminal 56, whereby the control circuit 5 is controlled.
Reference numeral 3 designates each of the changeover switches 34 and 35 for the selected terminal a.
Switch control to the side. At this time, the analog signal supplied to the analog input terminal 31 is controlled by the input volume amplifier 32 to have an appropriate amplitude, and then the emphasis amplifier 33 applies pre-emphasis having characteristics of time constants of 50 μs and 15 μs, for switching. It is sent to the LPF amplifier 35 via the selected terminal a of the switch 34. This L
In the PF amplifier 35, the band is limited to ½ or less of the sampling rate, and so-called anti-aliasing processing is performed. The output from the LPF amplifier 35 is sent to the integrator 40 via the selected terminal a of the changeover switch 36.

In the integrator 40, the times t _{1 to} t shown in FIG.
By turning on the switch 42 only during the time T ₁ of ₂ , the input voltage V _in is sampled and the capacitor 4 is turned on.
4, and the sampled voltage is held by turning off the switch 42 at time t ₂ . Next, by the control operation of the control circuit 53, the switch 46 is turned on from the time t ₃ to discharge the reference current source 47 with the constant current I ₁ , and the counting operation of the upper counter by the master clock is started.
This operation is continued for the time T ₂ until the time t ₄ when the integrated output reaches the first threshold value V _th1 . Then the lower-order counter for counting by the master clock with the switch 48 from time t ₄ is the discharge from the reference current source 49 is turned on with a constant current I ₂ is performed is started, the integration output is the second threshold value V _th2 Time to reach time t ₅
This operation is maintained for ₃ days. Here, the upper counter is weighted with respect to the lower counter according to the value of the current I ₁ / I ₂ , and I ₁ / I ₂ = 25.
In the case of 6 = 2 ^8, the upper counter performs the counting operation in the 8-bit upper digit with respect to the lower counter. As I ₁ / I ₂ 2 ⁸ -1 = 257, at the same time turns on the switch 46 and 48 and from time t _3, may be from the time t ₄ so as to turn on only the switch 48.

The master clock count value thus obtained during the time T ₂ is the upper bit, and the master clock count value during the time T ₃ is the lower bit. The digital value is the digital value output corresponding to the input analog voltage V _in .

In the A / D conversion operation as described above, the necessary parts (functional blocks) are the input volume amplifier 32, the emphasis amplifier 33, the LPF amplifier 35,
Inverter amplifier 43 serving as an integrating amplifier, and comparator 5
1 and 52, the precharge buffer amplifier 68, the deglitching inverter amplifier 63, and the de-emphasis amplifier 66 are unnecessary. Therefore, the control circuit 53 turns off the power supplies of the precharge buffer amplifier 68, the inverter amplifier 63, and the de-emphasis amplifier 66. The form of this power supply control is summarized in Table 1.

[0026]

[Table 1]

Next, the operation during D / A conversion will be described. In this case, first, the D / A conversion mode switching control signal is supplied to the control circuit 53 via the input terminal 56, so that the control circuit 53 shifts the changeover switches 34 and 35 to the selected terminal b side. Switch control. During this D / A conversion, a constant precharge voltage is sampled for each sample by an integrating amplifier, and the voltage of the reference current source is integrated to change the voltage at a constant rate. The operation is stopped when the signal is integrated for a time corresponding to the input signal, and the voltage is sampled and held by a deglitch amplifier to obtain a stepwise voltage.

That is, at the time t ₁₁ in FIG.
Is turned on, the precharge voltage from the precharge buffer amplifier 68 is supplied to the integrating capacitor 44 via the switch 42, and at a time t ₁₂ after the elapse of a predetermined time T ₁₁ , a constant precharge voltage higher than the signal maximum voltage value. It converges to the charge voltage. In FIG. 5, the integrated output is shown. Since the amplifier 43 is an inverting amplifier, the precharge voltage V _PR appears as a voltage lower than the signal minimum voltage. Next, at time t ₁₃ , the switches 46 and 48 are both turned on, and the switches 46 and 48 are continuously turned on for a time corresponding to the digital input signal input from the input terminal 55 to the control circuit 53. That is, the switch 46 is turned on only for the time T ₁₂ when the master clock is counted by the value of the upper bit of the digital signal, the current I ₁ of the reference current source 47 is integrated, and the switch is switched for the time T _{13 when} the value of the lower bit is counted. 48 is turned on to integrate each current I ₂ of the reference current source 49, and a final analog voltage output is obtained as an addition output of these.
In FIG. 5, the integrated output component due to the current I ₁ is shown in a broken line a, and the integrated output component due to the current I ₂ is shown in a broken line b, and the integrated output obtained by adding these is like a solid line bent at time t _14. Appears in. The integration operation is stopped at time t ₁₅ ,
By sampling the integrated output at this time at time t ₁₆ (turning on the switch 62 of the deglitching sample hold circuit 60), a stepped output voltage as shown by V _out in FIG. 5 is obtained. The time t ₁₆ is set after the time when the integration operation is finished even when the maximum digital value is input from the time t _13, and after the switch 62 is turned on for a predetermined time, the time t ₁₆ is set again. The cycle from the precharge operation similar to that from the time t ₁₁ is repeated.

The stepwise output voltage from the deglitch sample and hold circuit 60 is sent to the de-emphasis amplifier 66, and the emphasis amplifier 33.
De-emphasis is applied so that the pre-emphasis of the characteristic with the time constant of 50 μs and 15 μs returned to the original flat frequency characteristic. The output from the de-emphasis amplifier 66 is sent to the LPF amplifier 35 and band-limited to ½ or less of the sampling rate to form a smooth analog voltage waveform. LPF amplifier 3
The output from 5 is taken out as it is from the analog output terminal 37 as an analog line output, and the output level is controlled by the variable resistor 38 that serves as a headphone amplifier volume (attenuator), and taken out as a headphone amplifier output from the headphone output terminal 39. Be done.

Even during the D / A conversion operation as described above, the control circuit 53 controls the power of the unnecessary portions (functional blocks), that is, the input volume amplifier 32, the emphasis amplifier 33 and the comparators 51 and 52, to be turned off. ing. The form of this power supply control is as shown in Table 1 above.

Further, as shown in Table 1, in the so-called standby mode, the power supplies of all seven types of amplifiers are turned off to reduce power consumption.

The present invention is not limited to the above-mentioned embodiment, and, for example, using three reference current sources,
A / D conversion and D / A conversion operations may be performed in correspondence with the upper, middle, and lower digital values, or four or more reference current sources may be used. A / D conversion and D
The specific example of the IC (integrated circuit) that also serves as the A / A conversion is not limited to the cascade integration type configuration, and for example, a D / A converter using a ladder resistance network and a deglitch sample hold circuit, and a D / A converter Same IC as successive approximation type A / D converter using ladder resistance network of A converter
The present invention can also be applied to a D / A and A / D dual-purpose IC that is incorporated in a chip. In this case, D / A
In the conversion mode, the power of the comparator and successive approximation register dedicated to the A / D conversion unit is turned off, and in the A / D conversion mode, the power of the deglitch sample hold circuit dedicated to the D / A conversion unit is turned off. Furthermore, D / A and A / D combined I
In addition to C, the present invention can be applied to an integrated circuit device in which a plurality of signal processing circuit units such as an IC serving as an encoder and a decoder are incorporated in the same IC chip.

[0033]

As is apparent from the above description, according to the integrated circuit device of the present invention, there are two or more signal processing circuit sections each of which has a plurality of functional blocks capable of independently turning on / off the power supply. When the integrated circuit device is in a mode in which one signal processing circuit unit is not used, the power supply of the dedicated function block of the signal processing circuit unit is turned off, so that unnecessary power consumption of the integrated circuit is reduced. You can Therefore, the power supply circuit has a margin and a small battery or a small DC-DC converter can be used, which contributes to downsizing of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a main part of an embodiment of an integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing a specific example of a configuration for turning on / off a power source of an amplifier used in the embodiment.

FIG. 3 is a block circuit diagram showing a specific configuration of another embodiment of the integrated circuit device according to the present invention.

FIG. 4 is a time chart for explaining an A / D conversion operation in the embodiment.

FIG. 5 is a time chart for explaining a D / A conversion operation in the embodiment.

[Explanation of symbols]

 1, 2, 3 ... Functional block 4 ... First signal processing circuit section 5 ... Second signal processing circuit section 6 ... Power supply terminal 10 ... ..Control circuit 11, 12, 13 ... Switch 32 ... Input volume amplifier 33 ... Emphasis amplifier 34, 36 ... Changeover switch 35 ... LPF amplifier 40 ... Integrator 43, 63 ... Inverter amplifier 42, 46, 48, 62 ... Switch 47, 49 ... Reference current source 51, 52 ... Comparator 53 ... Control circuit 60 ... Deglitch sample hold circuit 66 ... De-emphasis amplifier

Claims (2)

[Claims] 1. A signal processing circuit section comprising a plurality of functional blocks is provided in two or more, and these functional blocks are shared by the two or more signal processing circuit sections, and each of the signal processing circuit sections is provided. In the integrated circuit device including a dedicated function block, each of the plurality of function blocks has a power ON / OFF means for each block, uses the first signal processing circuit section, and uses the second signal processing circuit section. An integrated circuit device characterized by turning off the power source of a dedicated functional block of the second signal processing circuit section in a mode not in use. 2. One of the plurality of signal processing circuit units is A /
2. The integrated circuit device according to claim 1, wherein the D conversion unit and the other one are D / A conversion units.