JPH08293791A - Analog/digital converter - Google Patents

Abstract

PURPOSE: To suppress power consumption through a simple configuration by subjecting the operation of an analog/digital converting means to stop control, making a conversion finish signal an input signal. CONSTITUTION: On the input of a conversion instruction signal, power is supplied from a control means 7 to the analog/digital converting means 12 and a conversion finish detecting means 11, and the digital signal converting operation of an input analog signal in the analog/digital converting means 12 is started. When it is detected by the conversion finish detecting means 11 that this digital signal converting operation is finished, the conversion finish signal is outputted from this conversion finish detecting means 11. Then, at the control means 7, power supply to the analog/digital converting means 12 and the conversion finish detecting means 11 is stopped by the conversion finish signal. Thus, only at the time of the digital signal converting operation, the power is supplied to the analog/digital converting means 12 and the conversion finish detecting means 11. Accordingly, the low power consumption of a circuit can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter which operates intermittently or at irregular intervals.

[0002]

2. Description of the Related Art Conventionally used analog / digital converters, so-called A / D converters, use circuit formats such as a flash method and a successive approximation method. In such an A / D conversion device, the circuit configuration is relatively large, and the power consumption is large because the current is constantly flowing, so that the battery-powered device has a large capacity. Are using.

Therefore, as disclosed in Japanese Patent Laid-Open No. 1-265722, there is disclosed a technique for reducing the current consumption of an A / D converter using the successive approximation method.

[0004]

By the way, the technique for reducing the current consumption described above is limited to the A / D converter of the successive approximation system, and the A / D conversion using a circuit format other than the successive approximation system is performed. In the device, the current consumption cannot be reduced.

Further, the control of power supply is limited to a part of the A / D conversion circuit.

In view of the above situation, the present invention has an analog / analog capable of suppressing power consumption with a simple circuit configuration.
A digital conversion device is provided.

[0007]

Analogs according to the present invention /
The digital conversion device includes an analog / digital conversion means for converting an input analog signal into a digital signal, and a conversion for detecting whether or not the conversion operation of the analog / digital conversion means is completed and outputting a conversion end signal. The above problem is solved by having the end detection means and the control means for stopping and controlling the operation of the analog / digital conversion means by inputting the conversion end signal from the conversion end detection means.

[0008]

According to the present invention, power is supplied from the control means to the analog / digital conversion means and the conversion end detection means by the input of the conversion instruction signal, and the digital signal conversion operation of the input analog signal in the analog / digital conversion means is performed. When the conversion end detecting means detects that the digital signal converting operation has ended, the conversion end detecting means outputs a conversion end signal, and the control means outputs the analog / digital signal by the conversion end signal. By stopping the power supply to the conversion means and the conversion end detection means, power is supplied to the analog / digital conversion means and the conversion end detection means only during the digital signal conversion operation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a first embodiment of an analog / digital converter according to the present invention.

The analog / digital converter (hereinafter referred to as A / D converter) of FIG. 1 is an analog / digital converter (hereinafter, referred to as an A / D converter) for converting an input analog signal into a digital signal. A
/ D conversion unit) 12 and the conversion end signal from the sequence control circuit 11 which is conversion end detection means and is built in the A / D conversion unit 12, and the operation of the A / D conversion unit 12 is performed. The power supply controller 7 is a control means for controlling stop. The power supply control unit 7 includes a pulse generator 4, an RS flip-flop 5, and a power supply circuit 6. The A / D converter 12 includes a sample hold circuit (hereinafter referred to as S / H circuit) 8, a digital / analog converter (hereinafter referred to as D / A converter) 9, a sequence control circuit 10, and a comparator 11. Composed.

The first embodiment is a successive approximation type A / D.
This is an example of a conversion device, and detects whether at least a part of the sequence control circuit 11 has completed the conversion operation of the A / D conversion unit 12 which is an analog / digital conversion means, and outputs a conversion end signal. It is used as a conversion end detecting means.

Next, the operation of the analog / digital converter will be described.

A conversion instruction signal from the outside is input to the signal input terminal 1. This conversion instruction signal is sent to the power supply controller 7 described above.
Of the pulse generator 4. The pulse generator 4 outputs a pulse for a certain period when the conversion instruction signal is input. This pulse is input to the input S of the RS flip-flop 5 and the reset RST of the sequence control circuit 11.

In the RS flip-flop 5, for example, when the value of the input S and the output Q is "0" and a pulse is input to the input S and the value of the input S becomes "1", A signal is output from the output Q until a pulse is next input to the input R. Then, when a pulse is input to the input R, a signal is output from the output Q until a pulse is input to the input S next. It is something that is not done. Therefore, as described above, when the value of the input S and the output Q of the RS flip-flop 5 is “0” and the pulse is input to the input S and the value of the input S becomes “1”, , A signal is output from the output Q, and this signal is input to the power supply circuit 6.

The power supply circuit 6 is provided with the A / D converter 1 while the output signal from the RS flip-flop 5 is being input.
Power is supplied to 2. The power supply circuit 6 does not supply power to the A / D converter 12 while the above signals are not input.

The power from the power supply circuit 6 is supplied to all the components of the A / D converter 12, that is, the S / H circuit 8, the D / A converter 9, the comparator 10 and the sequence control circuit 11, respectively. To be done.

The pulse output from the pulse generator 4 is also input to the reset RST of the sequence control circuit 11 as a reset signal of the sequence control circuit 11. In the sequence control circuit 11, the signal output from the signal input terminal 3 is the clock CL.
It is input to K, and this input signal is used as a clock signal in the sequence control circuit 11. Therefore, when the pulse output from the pulse generator 4 is input to the reset RST of the sequence control circuit 11, the sequence control circuit 11 is reset. After that, the reset is released in the sequence control circuit 11, a digital signal is output from the output O ₁ at the timing of the clock signal input to the clock CLK after the reset is released, and further, the output O ₂ to the output _ON. Digital signals are output sequentially from ₊₂ . The output signal from the output O ₁ is S /
The N-bit output signal from the output O ₂ to the output ON ₊₁ is input to the H circuit 8 and is input to the D / A converter 9 to output O _{N + 2.}
The output signal from is input to the input R of the RS flip-flop 5.

An analog signal from the signal input terminal 2 is input to the S / H circuit 8. In the S / H circuit 8, the output signal from the sequence control circuit 11 is used as a sample signal, and the analog signal from the signal input terminal 2 is sampled and held. The S / H circuit 8 outputs the same analog level as the analog signal from the signal input terminal 2 while the sample signal is being input. This analog level is stored, and while the sample signal is not input, the stored analog level immediately before the analog signal from the signal input terminal 2 is not input is continuously output. The analog level output from the S / H circuit 8 is sent to the comparator 10.

The D / A converter 9 outputs an analog level corresponding to the N-bit digital signal sequentially input from the sequence control circuit 11, and the analog level is input to the comparator 10.

In the comparator 10, the input S / H circuit 8
Is compared with the analog level from the D / A converter 9, and digital data corresponding to the magnitude relationship is output. This digital data is output to the outside of the analog / digital converter and also to the sequence control circuit 11.

Further, the output O of the sequence control circuit 11
_The digital signal output from _{N + 2} and input to the RS flip-flop 5 is used as a conversion end signal. When this conversion end signal is input to the RS flip-flop 5, no signal is output from the output Q of the RS flip-flop 5. As described above, when no signal is output from the output Q to the power supply circuit 6, power supply from the power supply circuit 6 to the A / D conversion unit 12 is stopped.

Next, the overall operation of the above A / D converter will be described with reference to the flowchart of FIG.

First, in the initial state, as shown in step S1, the values of the input S and the output Q of the RS flip-flop 5 are "0", and each component in the A / D converter 12 has Power is not supplied from the power supply circuit 6. That is, the power of the A / D converter 12 is off.

Next, when the pulse generator 4 receives the external conversion instruction signal from the signal input terminal 1 in step S2, a pulse is output from the pulse generator 4 for a certain period, and this pulse is input to the RS flip-flop 5. To be done. Therefore, in step S3, the value of the input S of the RS flip-flop 5 becomes'
The output Q of the RS flip-flop 5 becomes "1" in step S4, and a signal is output to the power supply circuit 6. As a result, power is supplied from the power supply circuit 6 to each component of the A / D conversion unit 12, and the power of the A / D conversion unit 12 is turned on as shown in step S5. .

Further, in step S6, the pulse output from the pulse generator 4 is input to the reset SRT of the sequence control circuit 11 as a reset signal and reset R
The value of ST changes from "0" to "1", and the sequence control circuit 11 is reset. After this, in step S7, the value of the reset RST of the sequence control circuit 11 changes from "1" to "0", and the reset of the sequence control circuit 11 is released.

As a result, in step S8, the operation of converting the analog signal into the digital signal in the A / D converter 12 is started. Specifically, the sequence control circuit 11
The digital signal from the output O ₁ of the sequence control circuit 11 to the S / H circuit 8 is output at the timing of the clock signal from the signal input terminal 3 which is input to the clock CLK of the sequence control circuit 11 after the reset of the Is output. The S / H circuit 8 samples and holds the analog signal from the signal input terminal 2 using the input signal.

Further, at the timing of the clock signal next inputted to the clock CLK of the sequence control circuit 11, the output from the output O ₁ of the sequence control circuit 11 becomes "0" and the S / H circuit 8 outputs. Output is retained,
At the same time, a digital signal is output from the output O ₂ of the sequence control circuit 11 to the D / A converter 9.
The digital signal from the output O ₂ is the most significant bit of the D / A converter 9, that is, MS, as shown in step S9.
It is input as B, and the MSB input of this D / A converter 9 changes from "0" to "1".

The output from the S / H circuit 8 and the output from the MSB of the D / A converter 9 are compared by a comparator 10, and S
If the output from the / H circuit 8 is larger, the comparator 10
Outputs "1", and if the output from the S / H circuit 8 is smaller, outputs "0". The output digital data is output to the outside as the most significant bit of the analog / digital converter, that is, the MSB data, and is also input to and stored in the sequence control circuit 11.

The output O ₃ of the sequence control circuit 11 is transferred to the D / A converter 9 at the timing of the clock signal input to the clock CLK next to the clock signal at the signal output timing from the output O _2. In response, a digital signal is output. The digital signal from the output O ₃ is input to the D / A converter 9 as the bit next to the MSB, is compared with the output from the S / H circuit 8 in the comparator 10, and then digital data is output. . This digital data is output to the outside as the next data of the MSB of this A / D converter, and is also input to and stored in the sequence control circuit 11.

In this way, the sequence control circuit 11
The digital signals are sequentially output from the outputs O _{2 to} ON _{+1 of} the above, and A / D conversion processing is performed.

In step S10, the digital signal output from the output O _{N + 1} is input to the least significant bit of the D / A converter 9, that is, the LSB, and the A / D conversion process is performed. In step S11, the output O of the sequence control circuit 11 is output at the timing of the clock signal next to the timing at which the digital signal is output from the output ON _{+ 1.
A} conversion end signal is output from _{N + 2} to the input R of the RS flip-flop 5, and A / D in the A / D conversion unit 12
The D conversion operation ends.

Specifically, in step S12, the conversion end signal is input to the input R of the RS flip-flop 5 to change the value of the input R from "0" to "1", and in step S13.
Then, the value of the output Q of the RS flip-flop 5 becomes "0". As a result, no signal is output from the output Q to the power supply circuit 6, and the power supply from the power supply circuit 6 to each component of the A / D conversion unit 12 is stopped in step S14. After that, the process returns to step S1 and the values of the input S and the output Q of the RS flip-flop 5 become "0", and the power of the A / D conversion unit 12 is turned off. This power-off state continues until the conversion instruction signal from the signal input terminal 1 is input to the pulse generator 4.

The second aspect of the A / D conversion device according to the present invention
FIG. 3 shows a schematic configuration of the embodiment of FIG.

This A / D converter is provided with a power supply control unit 7, A
The D / D conversion unit 20 and the conversion end detection unit 18 are included. The power supply control unit 7 has the same configuration as the power supply control unit 7 in the first embodiment described above, and the operation of the power supply control unit 7 is also the operation of the power supply control unit 7 in the first embodiment. The description of the operation of the power supply control unit 7 is omitted. The A / D converter 20 includes the reference voltage generator 1
3, an analog comparator 14, and a logic circuit 15. The conversion end detection unit 18 is composed of a digital comparator 16 and a delay unit 17.

Although the conversion end detection unit 18 has a circuit configuration of hardware, the operation of the conversion end detection unit 18 may be performed by software.

When the conversion instruction signal from the signal input terminal 1 is input to the pulse generator 4 in the power supply control unit 7, the power supply from the power supply circuit 6 causes the A / D converter 20 and the conversion end detection unit 18 to operate. Is supplied to each component of. A
When power is supplied to each component of the / D conversion unit 20, A
The A / D conversion operation is immediately performed in the / D conversion unit 20.

However, since an unstable portion exists in a specific component immediately after the power supply is started, an accurate output cannot be obtained from the A / D conversion section 20. Therefore, in the conversion end detector 18, the output from the A / D converter 20 is sampled at a predetermined time interval, and when the equal outputs continue, all the constituent elements of the A / D converter 20 are stable and correct. It is determined that the output is obtained, the output valid signal is output to the outside, and the conversion end signal is output to the RS flip-flop 5.
It outputs to the input R of. The output valid signal is
It is used when detecting digital data output from this A / D converter.

A / D converter 20 and conversion end detector 18
When power is supplied to the reference voltage generator 13 in the A / D converter 20, an analog level at which the LSB of the digital signal output changes is generated. This analog level is input to a plurality of comparators forming the analog comparator 14. The analog signals input from the signal input terminal 2 are sequentially input to the plurality of comparators in the analog comparator 14. Then, in each comparator, the analog level from the reference voltage generator 13 is compared with the level of the input analog signal, and 1-bit digital data based on the magnitude relation is output. These digital data are input to the logic circuit 15. The input digital data is encoded in the logic circuit 15, and the encoded digital data is output to the digital comparator 16 and the delay unit 17 in the conversion end detecting unit 18.

The delay unit 17 outputs the digital signal input at the timing before the input of the clock signal. This digital signal is output to the outside and
It is also sent to the digital comparator 16. In this digital comparator 16, the digital signal from the logic circuit 15 and the digital signal from the delay device 17 are compared, and if these digital signals are equal, the digital comparator 16 converts the digital signal into the input R of the RS flip-flop 5. An end signal is output.

The RS flip-flop 5 performs the same operation as the operation of the RS flip-flop 5 of the first embodiment, and the power supply circuit 6 supplies power to the A / D converter 20 and the conversion end detector 18. Stops.

In the above-described embodiment, the operation of the A / D converter may be stopped, which can reduce the power consumption of the A / D converter.

If an output control circuit or the like is provided at the subsequent stage of the A / D converter, for example, the power of the A / D converter is reduced so as not to affect the output control circuit. You may make it control the power supply of a conversion part.

The A / D conversion section is not limited to the configurations of the first and second embodiments described above, and the A / D conversion section may detect the end by an external control device such as a CPU, for example. The power supply control of the D conversion unit may be performed.

[0044]

As is apparent from the above description, the analog / digital conversion device according to the present invention is an analog / digital converter that converts an input analog signal into a digital signal.
A digital conversion means, a conversion end detection means for detecting whether or not the conversion operation of the analog / digital conversion means is completed and outputting a conversion end signal, and a conversion end signal from the conversion end detection means as inputs, By providing the control means for controlling the operation of the analog / digital conversion means, the power supply of the circuit which is not operating is kept off until the necessity of the operation arises. It is possible to reduce the power consumption of the circuit of the analog / digital conversion device at low cost.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a first embodiment of an analog / digital conversion device according to the present invention.

FIG. 2 is a flow chart of the operation of the analog / digital conversion device of FIG.

FIG. 3 is a schematic configuration diagram of a second embodiment of an analog / digital conversion device according to the present invention.

[Explanation of symbols]

 4 pulse generator 5 RS flip-flop 6 power supply circuit 7 power supply control unit 8 sample hold circuit 9 digital / analog converter 10 comparator 11 sequence control circuit 12 analog / digital conversion unit 14 analog comparator 15 logic circuit 16 digital comparator 17 Delay device 18 Conversion end detection unit 20 Analog / digital conversion unit

Claims (3)

[Claims] 1. An analog / digital conversion means for converting an input analog signal into a digital signal, and a conversion for detecting whether or not the conversion operation of the analog / digital conversion means is completed and outputting a conversion end signal. Analog / characterized in that it has end detection means and control means for stopping the operation of the analog / digital conversion means by inputting the conversion end signal from the conversion end detection means.
Digital converter. 2. The control means supplies power from a power supply circuit to the analog / digital conversion means and the conversion end detection means by inputting a conversion instruction signal from the outside, and inputs the conversion end signal to the analog. 2. The analog / digital conversion device according to claim 1, wherein the power supply from the power supply circuit to the digital / digital conversion means and the conversion end detection means is stopped. 3. The analog / digital conversion means comprises:
2. The analog / digital converter according to claim 1, wherein the analog / digital converter has a structure of a successive approximation system, and at least a part of a sequence control circuit in the structure of the successive comparison system is used as the conversion end detecting means.