JPH10190464A - Successive comparison type a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform conversion to the digital signals of a resolution set beforehand without increasing a circuit scale by constituting a successive comparison register provided with a temporary register for holding temporary digital signals in the middle of conversion and a shift register for successively setting the digital signals to the temporary register. SOLUTION: After selection signals supplied to a multiplexer 20 are decided and the resolution of the digital signals obtained by converting analog signals is set, the temporary register 22 and the shift register 24 are initialized by control signals or the like. When initialization is ended, in the successive comparison register 12, '1' is successively shifted from the side of a most significant bit 3 to the shift register 24 synchronized with clock signals. '1' is set to the most significant bit 3 of the temporary register 22, and when '1000' is outputted as the output signal of the respective bits 3-0, in a reference voltage generator 14, the reference voltage which is 1/2 of a maximum reference voltage is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation A / D converter for converting an analog signal into a digital signal having a predetermined resolution (a predetermined number of bits).

[0002]

2. Description of the Related Art A successive approximation type A / D converter converts an analog signal into a digital signal of a predetermined resolution corresponding to the analog signal one bit at a time from the most significant bit side. , A reference voltage generator for generating a reference voltage corresponding to the provisional digital signal set in the successive approximation register, a reference voltage generated by the reference voltage generator And a comparator that compares the input voltage of the analog signal with the analog signal.

In the successive approximation type A / D converter, first, "1" is set to the most significant bit of the successive approximation register. Thus, the reference voltage generator generates a reference voltage that is １ ／ of the maximum reference voltage, and the comparator compares the generated reference voltage with the input voltage of the analog signal. At this time, the most significant bit of the successive approximation register is determined to be “1” if the input voltage of the analog signal is higher than the reference voltage, and to “0” if the input voltage of the analog signal is lower than the reference voltage. It is determined.

Subsequently, "1" is set to the bit next to the most significant bit of the successive approximation register. Accordingly, when the most significant bit is determined to be “1” from the reference voltage generator, a reference voltage of ／ of the maximum reference voltage is generated, and conversely, the most significant bit is determined to be “0”. In this case, a reference voltage of 1/4 of the maximum reference voltage is generated. Then, the comparator compares the reference voltage with the input voltage of the analog signal, and determines the value of the bit next to the most significant bit of the successive approximation register.

Similarly, after the value of each bit of the successive approximation register is determined and the value of the least significant bit is determined, the value of each bit of the successive approximation register corresponds to an analog signal by a CPU or the like. Read as a digital signal. In this successive approximation type A / D converter, usually, it is not possible to read a digital signal or to perform a next conversion until conversion of all bits of a digital signal corresponding to an analog signal is completed. There was a point.

Therefore, when only a predetermined number of higher-order bits of the digital signal to be converted are required, there is a problem that conversion is wasteful and conversion efficiency is low. For example, in a successive approximation type A / D converter for converting an analog signal into a 10-bit digital signal, when only the data up to the upper 6 bits of the digital signal is required, all 6 bits may be converted from the 6 bits. If conversion is performed until conversion is completed, conversion time for 4 bits is wasted.

On the other hand, for example, Japanese Patent Application Laid-Open No.
No. 7 and Japanese Patent Application Laid-Open No. 4-337925 disclose that the conversion operation is stopped when an analog signal is converted into a digital signal having a predetermined desired resolution, and the next conversion operation can be performed. A / D converter has been proposed.
Here, FIG. 3 and FIG.
FIG. 1 is a conceptual diagram of an A / D converter disclosed in Japanese Patent Application Laid-Open No. 427 and Japanese Patent Application Laid-Open No. 4-337925.

First, as shown in FIG. 3, an A / D converter 30 disclosed in Japanese Unexamined Patent Publication No. Hei 4-249427 has, in addition to a successive approximation register 32, a reference voltage generator 34 and a comparator 36, Every time the digital signal is determined in order from the upper bit in the successive approximation register 32, the shift register 38 sequentially shifts and stores the digital signal, and the number of bits of the digital signal determined in the successive approximation register 32 becomes a predetermined value. And stopping means 40 for stopping the conversion operation when the conversion operation is performed.

According to the A / D converter 30, each time the A / D conversion is performed in the successive approximation register 32 in order from the most significant bit, the bit as the conversion result is sequentially shifted to the shift register 38. A / D to be stored
When the number of converted bits reaches a predetermined value, the A / D conversion operation can be terminated, and a digital signal corresponding to the completion of the A / D conversion can be taken out as an A / D conversion result. I can do it.

An A / D converter 42 disclosed in Japanese Patent Application Laid-Open No. Hei 4-337925 has a plurality of analog input terminals 44 in the A / D converter 30. Is provided for each analog terminal 44, and under the control of the controller 48, the analog signal input from each analog input terminal 44 is digitalized by the number of bits set in the corresponding register 46. The signals are sequentially converted into signals.

According to the A / D converter 42, since the register 46 for setting the resolution of the A / D conversion is provided for each analog input terminal 44, a plurality of analog input terminals 44 are switched by the switch 50. A / D conversion is performed on each analog signal input from the A / D converter at a predetermined resolution, so that A / D conversion can be performed without wasting time. He says that he can get minute data.

However, these A / D converters 3
At 0 and 42, the bits for which the A / D conversion has been completed are stored in the shift register 38 while being sequentially shifted.
Every time the resolution of the / D conversion changes, the position of the most significant bit of the digital signal stored in the shift register 38 changes. For example, the most significant bit in the case of 8 bits and the most significant bit in the case of 10 bits Since the positions in the shift register 38 are different, there is a problem that data processing of digital signals is difficult.

The A / D converters 30 and 42 include a register for setting the resolution at which the conversion operation is stopped, a stop means 40 or a controller 48 for stopping the A / D conversion, Many circuits that have nothing to do with the original operation of the A / D converter, such as a counter that counts the number of bits of the converted digital signal and a comparator that compares the value of this counter with the number of bits set in the register, are required. Therefore, there is a problem that a circuit scale and power consumption increase.

Further, these A / D converters 30 and 42
In, for example, counting the number of bits of the digital signal after the conversion is completed, comparing this count value with the resolution of the preset digital signal, when the count value reaches the resolution of the preset digital signal Since the conversion stop signal is output, an extra time of, for example, about one clock time is required from the end of the conversion of the digital signal having the preset resolution to the end of the actual conversion operation. There is also a problem.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to convert an analog signal into a digital signal having a predetermined resolution without increasing the circuit scale, in view of the problems based on the prior art. Possible successive approximation type A /
It is to provide a D converter.

[0016]

According to the present invention, there is provided a successive approximation type A / D converter for converting an analog signal into a digital signal having a predetermined resolution. A temporary register for holding a temporary digital signal on the way, a successive approximation register having a shift register for sequentially setting the temporary digital signal in the temporary register, and a temporary digital register set in the successive approximation register. A reference voltage generator for generating a reference voltage corresponding to the signal, a comparator for comparing the reference voltage generated by the reference voltage generator with the input voltage of the analog signal, and a final digital signal after the conversion is completed. A data storage register to be held, and a shift register constituting the successive approximation register in accordance with the resolution of the preset digital signal. And it provides a successive approximation type A / D converter and having a multiplexer for selecting and outputting one of the output signals of each bit of data as an end of conversion signal.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a successive approximation type A / D converter according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a conceptual diagram of an embodiment of a successive approximation type A / D converter according to the present invention. A successive approximation type A / D in the illustrated example
The converter 10 converts, as a digital signal (digital data) obtained by converting an analog signal (analog input voltage), the successive approximation type A /
An example of a D converter is shown in FIG.
2, a reference voltage generator 14, a comparator 16, a data storage register 18, and a multiplexer 20.

In the successive approximation type A / D converter 10, first, a successive approximation register 12 is used to sequentially set a tentative digital signal being converted and supplied to a reference voltage generator 14. A provisional register 22 for holding a 4-bit provisional digital signal, and 5 bits for sequentially setting “1 (high level)” as a provisional digital signal in order from the most significant bit side of the provisional register 22 Shift register 24.

The reference voltage generator 14 generates a reference voltage (analog comparison voltage) corresponding to a digital signal provisionally set in the successive approximation register 12, and in the illustrated example, a decoder 26 and a resistance ladder 28. Having. The decoder 26 decodes the provisional digital signal provided from the successive approximation register 12 and outputs a decoded signal. The resistor ladder 28 generates a predetermined reference voltage according to the decoded signal output from the decoder 26. .

The comparator 16 includes a reference voltage generator 14
Is compared with the input voltage of the analog signal, and the result of the comparison is fed back to the successive approximation register 12. Each bit of the provisional register 22 of the successive approximation register 12 is determined according to the comparison result of the comparator 16, and the value of the determined digital signal is set instead of the value of the provisional digital signal.

When the analog signal is converted into a digital signal having a predetermined resolution, as will be described later, of the analog signal, the data storage register 18 temporarily stores the temporary signal in the successive approximation register 12. Register 2
The digital signal set to 2 is held as a final digital signal. In the illustrated example, a 4-bit data storage register is provided corresponding to the provisional register 22 of the successive approximation register 12.

The multiplexer 20 outputs one of the output signals of each bit of the shift register 24 constituting the successive approximation register 12 in accordance with the resolution of the digital signal set in advance.
One of them is selectively output as a conversion stop signal. As a selection signal for the multiplexer 20, for example, a register or the like for setting the resolution of a digital signal may be provided to control the multiplexer 20, or the selection terminal of the multiplexer 20 may be directly controlled by an external circuit. You may.

Note that the above-mentioned conversion stop signal notifies the outside of the stop of the conversion operation in the successive approximation type A / D converter 10 of the present invention to the outside.
8 is read and used as a signal for latching the digital signal in an external register, or as a signal for reducing power consumption, or a provisional comparison register 12 is constituted. Register 2
2 and a signal for initializing the shift register 24.

In the successive approximation type A / D converter 10 of the present invention having the above configuration, first, the selection signal given to the multiplexer 20 is determined, and the resolution of the digital signal obtained by converting the analog signal is determined. Is set, the temporary register 22 and the shift register 24 constituting the successive approximation register 12 are initialized by, for example, a control signal supplied from the outside, a conversion stop signal output from the multiplexer 20, and the like.

For example, when the resolution of the digital signal is 1 bit and the conversion operation is to be stopped after the most significant bit of the digital signal is converted, the multiplexer 20 is selected so that bit 2 of the shift register 24 is selectively output. Set the selection signal. Also, due to the initialization, the output signal of each bit 3 to 0 of the temporary register 22 becomes “0000 (2
Base number)], and each bit 3-0 of the shift register 24
The output signal of the last bit S is “00000 (binary number)”.

When the setting of the selection signal of the multiplexer 20 is completed and the initialization of the successive approximation register 12 is completed, the successive approximation register 12 is synchronized with a clock signal (not shown) as shown in the timing chart of FIG. Then, “1” is sequentially shifted to the shift register 24 from the bit 3 which is the most significant bit. First, when "1" is shifted to bit 3 of shift register 24, bit 3 which is the most significant bit of provisional register 22 corresponding thereto is set to "1".

When bit 3 of provisional register 22 is set to “1”, that is, each bit 3 of provisional register 22
When "1000 (binary number)" is output as an output signal of "0" to "0", the provisional digital signal set in the provisional register 22 of the successive approximation register 12 is decoded by the decoder 26 in the reference voltage generator 14. , The resistor ladder 28 generates a reference voltage that is の of the maximum reference voltage in accordance with the decode signal output from the decoder 26.

The reference voltage of １ ／ of the maximum reference voltage generated by the reference voltage generator 14 is input to the comparator 16, where the comparator 16 outputs 1 / の of the maximum reference voltage.
2 is compared with the input voltage of the analog signal. At this time, bit 3 of the provisional register 22 is determined to be “1” if the input voltage of the analog signal is larger than half the reference voltage of the maximum reference voltage. Is determined to be "0" if it is smaller than 1/2 of the reference voltage.

Subsequently, in the successive approximation register 12,
As shown in the timing chart of FIG. 2, "1" is shifted to the shift register 24 in synchronization with a clock signal (not shown), and bit 3 is set to "0" and bit 2 is set to "1". When “1” is shifted to bit 2 of shift register 24, bit 3 of provisional register 22 is shifted.
, The bit 2 of the temporary register 22 corresponding to the bit 2 of the shift register 24 is set to “1”.

When bit 2 of provisional register 22 is set to “1”, that is, each bit 3 of provisional register 22
When "1100 (binary number)" or "0100 (binary number)" is output as an output signal of ".about.0", each bit 3-0 of the provisional register 22 is output from the reference voltage generator 14 as "1100 (binary number)". )), 3/4 of the maximum reference voltage
When the bits 3 to 0 of the temporary register 22 are “0100 (binary number)”, a reference voltage that is の of the maximum reference voltage is generated.

Then, the comparator 16 compares the reference voltage with the input voltage of the analog signal, and determines the value of bit 2 of the successive approximation register 12. Similarly, after the values of bits 3 to 0 of provisional register 22 of successive approximation register 12 are determined, and the value of bit 0 is determined, the values of bits 3 to 0 of provisional register 22 are stored in data. The data is held in the register 18 and read as a digital signal corresponding to an analog signal by a CPU (not shown) or the like.

Although the successive approximation type A / D converter of the present invention has been described in detail, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention. Of course, you can. For example,
In the above embodiment, one analog signal is input. However, the successive approximation type A / D converter of the present invention is provided with a plurality of analog input terminals, and is provided with a plurality of analog input terminals. The present invention is also applicable to an A / D converter in which an analog signal is switched and used by a switch.

[0034]

As described above in detail, the successive approximation type A / D converter according to the present invention includes a successive approximation register, which is an essential component of the successive approximation type A / D converter, as a temporary register and a temporary register. A shift register is used, and one of the output signals of each bit of the shift register is selectively output as a conversion end signal by a multiplexer in accordance with a preset resolution of a digital signal. is there. Therefore, according to the successive approximation A / D converter of the present invention, an analog signal can be converted into a digital signal having a predetermined resolution without increasing the circuit scale. Further, the successive approximation type A / D converter of the present invention can be easily applied to an A / D converter that uses a plurality of analog signals by switching with a switch.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of one embodiment of a successive approximation A / D converter of the present invention.

FIG. 2 is a timing chart of one embodiment showing the operation of the successive approximation type A / D converter of the present invention.

FIG. 3 is a conceptual diagram of an example of a conventional successive approximation A / D converter.

FIG. 4 is a conceptual diagram of another example of a conventional successive approximation type A / D converter.

[Explanation of symbols]

 10, 30, 42 A / D converter 12, 32 Successive comparison register 14, 34 Reference voltage generator 16, 36 Comparator 18 Data storage register 20 Multiplexer 22 Temporary register 24, 38 Shift register 26 Decoder 28 Resistance ladder 40 Stopping means 44 Analog input terminal 46 Register 48 Controller 50 Switch

Claims (1)

[Claims] 1. A successive approximation A / D converter for converting an analog signal into a digital signal having a predetermined resolution, comprising: a temporary register for holding a temporary digital signal being converted; A successive approximation register having a shift register for sequentially setting the temporary digital signal in the temporary register; a reference voltage generator for generating a reference voltage corresponding to the temporary digital signal set in the successive approximation register; A comparator for comparing a reference voltage generated by a reference voltage generator with an input voltage of the analog signal, a data storage register for holding a final digital signal after conversion, and a resolution of the preset digital signal , One of the output signals of each bit of the shift register constituting the successive approximation register is selected as the conversion end signal. A successive approximation type A / D converter, comprising: a multiplexer for selectively outputting.