JPH07131353A - Successive approximation a/d converter - Google Patents

Abstract

PURPOSE:To perform digitizing with high accuracy rather than a conventional circuit. CONSTITUTION:The successive approximation A/D converting circuit digitizes an input voltage I to arrive at an analog comparator 1 based on an output provided from this analog comparator 1 when different reference voltages are successively applied to the reference voltage input side terminal of this analog comparator 1. The successively comparative A/D converter is provided with a control means 22 for successively setting correspondent data as outputs based on the output provided from this analog comparator 1 and a pulse modulation circuit 23 for outputting a pulse corresponding to the data set by this control means 22 to the reference voltage input side terminal of this analog comparator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a successive approximation type AD converter.

[0002]

2. Description of the Related Art FIG. 8 shows a successive approximation type AD according to a conventional example.
A converter is shown. This AD converter inputs an analog input voltage VI to be digitized to one input terminal of an analog comparator 1 and supplies a reference voltage VO to the other input terminal to compare them, and the analog input voltage VI is H level (1) when the voltage is higher than the reference voltage VO
Is output, and in the opposite case, L level (0) is output. The output of the analog comparator 1 is sent to the successive approximation register 2 of the digital control ASIC (application specific IC) 20A. The successive approximation register 2 is provided with register control data of a predetermined bit transmitted from a control circuit 4 configured by a microprocessor or the like, and the successive approximation register 2 converts the digital data corresponding to the control data into the DA converter 3. Output to. D
The A converter 3 converts the given digital data into a reference voltage VO having a corresponding analog voltage level and outputs it. As a result, the output of the analog comparator 1 becomes H
Level or L level, so successive approximation register 2
Outputs 1 bit of the digital data relating to the output according to the H level or L level of the output of the analog comparator 1. As a result, the DA converter 3 converts the supplied digital data into a reference voltage VO having a corresponding analog voltage level and outputs it. As a result,
The output of the analog comparator 1 becomes H level or L level. The successive approximation register 2 further changes the output digital data by 1 bit and outputs the digital data according to the H level or L level of the output of the analog comparator 1.

Similarly, the digital data of a predetermined bit is determined bit by bit from the MSB side, and the LSB is determined according to the result of the last change of 1 bit. The digital data determined in this way is given to another digital logic circuit 30 in the digital control ASIC 20A and processed.

[0004]

However, in the above configuration, the DA converter 3 has various types such as a capacitance series type, a resistance string type, a resistance series type, and a ladder resistance type, and all of them are analog circuits. Therefore, there has been a problem that the reference voltage cannot be changed with high accuracy corresponding to the digital data output from the successive approximation register 2. Further, since the DA converter 3 is an analog circuit, it cannot be incorporated in the digital control ASIC, and the miniaturization,
There is also a problem that it is difficult to reduce the weight and further reduce the power consumption.

The present invention has been made in order to solve the above problems, and an object thereof is a successive approximation type AD capable of highly accurately digitizing a reference voltage by changing the reference voltage with high accuracy. It is to provide a converter. Furthermore,
Another object of the present invention is to provide a successive approximation A / D converter which can be incorporated in a digital control ASIC, which can be reduced in size and weight, and which can further reduce power consumption.

[0006]

Therefore, in the present invention, when different reference voltages are sequentially applied to the reference voltage input side terminals of the analog comparator, the analog comparator arrives at the analog comparator based on the output obtained from the analog comparator. Successive approximation type AD that digitizes the input voltage
In the converter, based on the output obtained from the analog comparator, control means for sequentially setting the corresponding data, and a pulse corresponding to the data set by the control means to the reference voltage input side terminal of the analog comparator. Successive-comparison type AD equipped with an output pulse modulation circuit
Configured the converter.

Further, in the second invention of the present application, when different reference voltages are sequentially applied to the reference voltage input side terminals of the analog comparator, the input arriving at the analog comparator is based on the output obtained from the analog comparator. Control means for sequentially setting output of corresponding data based on the output obtained from the analog comparator and a pulse corresponding to the data set by the control means are output to the successive approximation type AD converter for digitizing the voltage. And a smoothing circuit for smoothing the output of the pulse modulating circuit and sending it to the reference voltage input side terminal of the analog comparator.
Configured the converter.

Further, according to the third invention of the present application, when different reference voltages are sequentially applied to the reference voltage input side terminals of the analog comparator, the input arriving at the analog comparator is based on the output obtained from the analog comparator. In the successive approximation type AD converter for digitizing the voltage, based on the output obtained from the analog comparator, control means for sequentially outputting and setting corresponding data, and a pulse corresponding to the data set by the control means are provided. The analog comparator is provided with a pulse modulation circuit for outputting to a reference voltage input side terminal, and the analog comparator is constituted by an integrating circuit.
It was a D converter.

In the present invention, the pulse modulation circuit is a pulse width modulation circuit, the register in which the data from the control means is set, the ring counter for sending the count output at a predetermined cycle, and the register are set in the register. The data is compared with the output of the ring counter, and the output level is changed according to the comparison result.

[0010]

According to the present invention having the above-mentioned structure, the fact that the pulse modulation circuit outputs a pulse according to the data set by the control means is used, and the voltage effectively realized by the set of this pulse is used as the reference voltage. Since it is configured to be supplied to the analog comparator as, the high precision digitization becomes possible as the pulse is digitally changed. Also, the pulse modulation circuit is a digital A
It is possible to provide a successive approximation type AD converter which is incorporated in an SIC and has a small size, a light weight, and low power consumption.

According to the second invention of the present application, since the output of the pulse modulation circuit is smoothed and sent to the reference voltage input side terminal of the analog comparator, the above pulse can be changed digitally. Accordingly, in addition to the point that highly accurate digitization is possible, the smoothed reference voltage ensures a more accurate comparison operation, and further higher accuracy can be achieved.

Further, according to the third invention of the present application, since the analog comparator is composed of an integrating circuit, high-precision digitization is possible as the pulse is digitally changed in the same manner as above. In addition to the above point, the output of the integration circuit is smoothed regardless of the fluctuation of the reference voltage, so that a more accurate comparison result can be obtained and higher accuracy can be achieved.

Further, in the present invention, the pulse modulation circuit is a pulse width modulation circuit, a register in which the data from the control means is set, a ring counter for sending a count output at a predetermined cycle, and the data set in the register. And the output of the ring counter are compared, and a digital comparator for displacing the output level according to the comparison result is incorporated into a digital ASIC to reduce the size, weight, and power consumption. Realize a vessel.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A successive approximation type AD converter according to an embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a block diagram of a successive approximation type AD converter according to the present embodiment. In the AD converter of this embodiment, the analog input voltage VI to be digitized is input to one input terminal of the analog comparator 1, and the reference voltage VO is input to the other input terminal.
To make these comparisons take place, and the analog input voltage V
When I is equal to or higher than the reference voltage Vo, the H level (1) is output, and when the I is higher than the reference voltage Vo, the L level (0) is output. The output of the analog comparator 1 is sent to a digital input port 21 of a digital control ASIC (application specific IC) 20. The digital input port 21 digitizes the H-level or L-level signal output from the analog comparator 1 and supplies it to the CPU 22 as "1" or "0".

The CPU 22 uses the digital control ASI.
It is a processor that controls the C20 as a whole, and as far as the control of the successive approximation type AD converter here is concerned,
Control based on the program of the flowchart shown in FIG. 7 is performed. That is, here, the pulse width modulation circuit (PW
M) 23 has an 8-bit range, so initially load 8-bit data with the MSB set to 1 and the other bits set to 0, and based on this result, the LS is set bit by bit thereafter.
Each bit is decided toward B.

The pulse width modulation circuit 23 includes the CPU 22.
8 bit register 23a in which data is loaded and data is set, and an 8 bit ring counter 23 which is stepped at a predetermined cycle (by a clock of a predetermined cycle)
c, the data of the register 23a and the ring counter 2
A digital comparator which compares the output of 3c and outputs H level when the data of the register 23a is larger than the output of the ring counter 23c, and conversely outputs L level when the data of the register 23a becomes less than the output of the ring counter 23c. 23b and.

Therefore, the output (H / L) of the digital comparator 23b changes depending on the relationship between the set value of the register 23a and the counter value of the counter 23c, as shown in FIG. That is, for one cycle T of the ring counter 23c, the set value in the register 23a is (0100000).
0), (10000000), (11000000), the pulse width changes as shown in FIG. 3 and several cycles are given to the analog comparator 1,
When the output of the digital comparator 23b at (11111111) is VO MAX, (VO MAX) / 4 and (VO MAX) / are effectively (average) respectively.
It works as if a reference voltage of 2, 3 (VO MAX) / 4 is given. Note that (VO MAX) is a voltage equal to or lower than the rating of the analog comparator 1.

Next, the operation of the successive approximation type AD converter configured as described above will be described with reference to the flowchart of FIG. When the operation starts, the CPU 22 sets the register i (not shown) to the number of bits corresponding to the MSB (here, 8).
(71), the data corresponding to the MSB is set to 1 and the other bits are set to 0 (10000000) is loaded into the register 23a (72). As a result, as described above, the pulse width of T / 2 corresponding to (VO MAX) / 2 is H from the digital comparator 23b as shown in FIG.
A level pulse is output, the analog comparator 1 compares it with the analog input voltage VI to be digitized, and outputs an H level or L level signal in accordance with the result. In response to this, digital data of 1 or 0 is supplied from the digital input port 21 to the CPU 22. Therefore, the CPU 22 detects whether the incoming data is "1" (73). If it is "1", the i-th bit (here, the MSB) is set to 1.
(74), and conversely, if it is "0", the i-th bit (here, MSB) is fixed to 0 (75). Furthermore,
The CPU 22 decrements the value of the register i by 1 (76) and detects whether the value of the register i becomes 0 (77). If not 0, steps 74 and 75
The data having the i-th bit as 1 is created for the data of (1) and loaded into the register 23A (78). That is,
When the i-th bit (here, MSB) is fixed to 1, (11000000) is loaded, and conversely, when the i-th bit (here, MSB) is fixed to 0,
(01000000) is loaded. As a result, a pulse having a pulse width as shown in FIG. 3 is output, and again,
In step 73, since digital data of 1 or 0 is supplied from the digital input port 21 to the CPU 22, the CPU 22 detects whether the incoming data is "1" (73). If it is “1”, the i-th bit (here, the bit next to the MSB) is set to 1
(74), and conversely, if it is "0", the i-th bit (here, the bit next to the MSB) is fixed to 0 (7).
5). Further, the CPU 22 decrements the value of the register i by 1 (76) and detects whether the value of the register i becomes 0 (77). If not 0, step 7
For the data of 4 and 75, data in which the i-th bit is 1 is created and loaded into the register 23A (78). In the same manner, each time the operation is repeated, one bit is determined from the MSB bit side to the LSB bit side, and when the value of the register i becomes 0, the operation ends, and the AD conversion operation ends.

In the above embodiment, the reference period of the pulse is set appropriately so that the analog comparator 1 is effectively supplied with the reference voltage of the predetermined level. However, even when the pulse cycle T is not set appropriately, it is possible to apply a reference voltage of a predetermined level to the analog comparator 1. FIG. 4 shows a configuration diagram of a main part of the embodiment thus configured. In this embodiment, the output of the pulse width modulation circuit 23 is smoothed via the smoothing circuit 3a and given to the analog comparator 1. By doing so, even if the voltage waveform has unevenness due to each pulse, as a result of smoothing, the analog comparator 1
It is possible to apply a reference voltage of a predetermined level to the.

FIG. 5 shows a main part of still another embodiment. In this embodiment, similarly to the embodiment of FIG. 4, the output of the pulse width modulation circuit 23 is smoothed via the smoothing circuit 3b and given to the analog comparator 1. This smoothing circuit 3b is
This is an integrating circuit using an operational amplifier, and smoothes by integrating each pulse, and even if the voltage waveform has unevenness by each pulse, the analog comparator 1
It is possible to apply a reference voltage of a predetermined level to the.

In the embodiment shown in FIGS. 4 and 5, the output of the pulse width modulation circuit 23 is smoothed through the smoothing circuit and applied to the analog comparator 1, and the pulse period T is not set appropriately. Even in this case, it is possible to apply a reference voltage of a predetermined level to the analog comparator 1. However, in another embodiment, the analog comparator 1 itself is configured by the integrating circuit 4 as shown in FIG. 6 without passing the output of the pulse width modulation circuit 23 through the smoothing circuit. With this configuration, even if the output of the analog comparator 1 originally has unevenness because the voltage waveform has unevenness due to each pulse of the reference voltage VO, the integrating circuit 4 causes the output side to have unevenness. The output will be sent out after being stabilized.

Further, in this embodiment, the reference voltage is obtained by using the pulse width modulation circuit, but in other embodiments,
A pulse frequency modulation circuit is used. Also in this embodiment, the reference voltage is obtained corresponding to the density of the pulses, and the same effect as that of the above embodiment can be expected. In addition, the same effect can be obtained by using a pulse modulation circuit using a digital circuit. In addition, the number of bits and the CPU 22 as a control unit in this embodiment are merely examples, and it is needless to say that the control unit can be applied to various numbers of bits and the control unit can be configured by a microprocessor or a dedicated control circuit.

[0023]

As described above, according to the present invention, the voltage effectively realized by the pulse modulation circuit outputting the pulse according to the data set by the control means is given to the analog comparator as the reference voltage. With this configuration, highly accurate digitization is possible as the pulse is digitally changed.
In addition, the pulse modulation circuit is incorporated in a digital ASIC to reduce the size, weight, and power consumption of the successive approximation type AD.
A converter can be provided.

According to the second invention of the present application, since the output of the pulse modulation circuit is smoothed and sent to the reference voltage input side terminal of the analog comparator, in addition to the above, the smoothed reference voltage is used. As a result, a more accurate comparison operation can be ensured and higher accuracy can be achieved.

Further, according to the third invention of the present application, since the analog comparator is constituted by the integrating circuit, in addition to the above, the output of the integrating circuit is smoothed regardless of the fluctuation of the reference voltage. A more accurate comparison result can be obtained, and higher precision can be achieved.

Further, in the present invention, the pulse modulation circuit is a pulse width modulation circuit, the register in which the data from the control means is set, the ring counter for sending the count output at a predetermined cycle, and the data set in the register. And the output of the ring counter are compared, and a digital comparator for displacing the output level according to the comparison result is incorporated into a digital ASIC to reduce the size, weight, and power consumption. Realize a vessel.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a successive approximation type AD converter according to an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the reference voltage output data of the successive approximation type AD converter according to the embodiment of the present invention and the output of the comparator.

FIG. 3 is a diagram showing the relationship between the pulse width of the reference voltage output and the data for the reference voltage output of the successive approximation type AD converter according to the embodiment of the present invention.

FIG. 4 is a main part configuration diagram of a successive approximation type AD converter according to another embodiment of the present invention.

FIG. 5 is a configuration diagram of a main part of a successive approximation type AD converter according to another embodiment of the present invention.

FIG. 6 is a configuration diagram of a main part of a successive approximation type AD converter according to another embodiment of the present invention.

FIG. 7 is a flowchart for explaining the operation of the successive approximation type AD converter according to the embodiment of the present invention.

FIG. 8 is a configuration diagram of a conventional successive approximation type AD converter.

[Explanation of symbols]

1 Analog Comparator 20 Digital Control ASIC 21 Digital Input Port 22 CP
U 23 pulse width modulation circuit 23a register 23b digital comparator 23c ring counter

Claims (4)

[Claims] 1. A successive comparison for digitizing an input voltage arriving at the analog comparator based on an output obtained from the analog comparator when different reference voltages are sequentially applied to a reference voltage input side terminal of the analog comparator. In the AD converter, based on the output obtained from the analog comparator,
And a pulse modulation circuit for outputting a pulse corresponding to the data set by the control means to the reference voltage input side terminal of the analog comparator. Comparative AD converter. 2. A successive comparison that digitizes the input voltage arriving at the analog comparator based on the output obtained from the analog comparator when different reference voltages are sequentially applied to the reference voltage input side terminals of the analog comparator. In the AD converter, based on the output obtained from the analog comparator,
Control means for sequentially setting the output of corresponding data, a pulse modulation circuit for outputting a pulse according to the data set by this control means, an output of this pulse modulation circuit is smoothed, and the reference voltage input of the analog comparator is input. A successive approximation type AD converter, comprising: a smoothing circuit for sending to a side terminal. 3. A successive approximation that digitizes the input voltage arriving at the analog comparator based on the output obtained from the analog comparator when different reference voltages are sequentially applied to the reference voltage input side terminals of the analog comparator. In the AD converter, based on the output obtained from the analog comparator,
Control means for sequentially setting the output of corresponding data, and a pulse modulation circuit for outputting a pulse according to the data set by this control means to the reference voltage input side terminal of the analog comparator, the analog comparator, A successive approximation type AD converter characterized by being constituted by an integrating circuit. 4. The pulse modulation circuit is a pulse width modulation circuit, a register in which data from the control means is set, a ring counter for sending a count output at a predetermined cycle, the data set in the register and the ring. 4. A successive approximation type AD converter according to claim 1, further comprising a digital comparator that compares the output of the counter and shifts the output level according to the comparison result. vessel.