JPH0629856A - Oversampling mode ad converter - Google Patents

Abstract

PURPOSE:To obtain the highest conversion accuracy only when it is necessary and to save extra electric power on the other occasions by constituting a clock frequency to be supplied to be changed according to required minimum A/D conversion accuracy. CONSTITUTION:A processor for control 106 performs a judgment based on control information 107 and it lowers a sampling frequency clock 110 when it judges that the reduction of conversion accuracy is possible. The processor controlls each block of a subtracter 101, an analog integrator 102, a comparator 103, a digital integrator 105 and an internal DA converter 104, using a control signal 109 and lowers conversion accuracy. Therefore, the highest conversion accuracy can be obtained only when it is necessary and extra electric power can be saved on the other occasions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling AD converter, and more particularly to an oversampling AD converter which is required to have a conversion accuracy that is not a single value and low power consumption.

[0002]

2. Description of the Related Art Oversampling AD converters are
The feature is that high conversion accuracy can be obtained even when a low-scale, low-precision analog circuit is used due to the dispersion of quantization noise in a high frequency range due to a high sampling frequency and the noise shaping effect due to ΔΣ modulation or the like. . However, power consumption is large because a large-scale digital circuit is driven by a high-speed sampling clock. Regarding this, for example, the description in “Design of AD / DA conversion circuit” by Yoshiyuki Nagahashi (published in 1982 by CQ publisher) can be referred to.

[0003]

By the way, depending on the application, the AD converter is not always required to have high conversion accuracy. Therefore, in such cases,
Extra power is consumed in order to obtain more precision than necessary. This is a serious problem, especially in battery-powered electronic devices. The present invention has been made in view of the above circumstances, and an object thereof is to solve the problems as described above in the related art and to obtain the highest conversion accuracy only when necessary.
Another object of the present invention is to provide an oversampling AD converter capable of saving the above-mentioned extra power in other cases.

[0004]

The above object of the present invention is to provide an analog integrator, a comparator for quantizing the output of the analog integrator, a digital integrator for cumulatively adding the outputs of the comparator, and the digital integration. DA output
And an internal DA converter for converting the analog output of the internal DA converter and an analog input to be detected as a difference between the analog integrator and the analog sampling. , A comparator, a digital integrator, and an internal DA converter are configured to change the clock frequency according to the minimum required AD conversion accuracy. It

[0005]

In the oversampling AD converter according to the present invention, the CMOS logic circuit has a characteristic that the power consumption thereof is proportional to the frequency, so that the sampling frequency can be reduced corresponding to the required conversion accuracy. In addition, the power consumption is reduced by optimizing the analog and digital signal processing units such as the speed reduction of the analog unit and the bypassing / disconnection of the unnecessary portion of the digital unit in accordance with this. Further, in this case, since the analog circuit is not required to have high speed, it is possible to operate at a low speed with a small bias current, and thereby it is possible to save power.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an oversampling AD converter according to an embodiment of the present invention. Here, 101 is a subtractor, 102 is an analog integrator, 10
3 is a comparator, 104 is an internal DA converter, 105 is a digital integrator, 106 is a control processor, 107
Is information for controlling, 108 is a decimator, 109
Indicates each block control signal, and 110 indicates a sampling frequency clock. In the AD converter shown in the present embodiment, the control processor 106 makes a judgment based on the control information 107, and if it is judged that the conversion accuracy can be reduced, the sampling frequency clock 110 is lowered and the control signal 109 is made.
Is used to control the blocks 101 to 104 to reduce the conversion accuracy and power consumption. The power reduction in this case is realized by the following four methods. Reduce the sampling frequency. High speed to support high sampling frequencies,
Reduce the speed of the integrator, comparator, and internal DA converter. The operation of the digital integrator in the interpolation type AD converter is stopped. The unnecessary part of the decimator is cut off as the sampling frequency is reduced. Hereinafter, details of the above-described power reduction method will be described.

Sampling frequency reduction: This is CM
The fact that the power consumption in the OS digital circuit is proportional to the frequency is utilized. Reduction of speed of high-speed integrator, comparator, etc .: This is based on the two methods shown in FIGS. In Fig. 2, the bias current of the OP amplifier, comparator, etc. is reduced to reduce the speed.
It is intended to reduce power consumption. Here, 201 is an analog integrator bias constant current circuit, 202 is a comparator bias constant current circuit, 203 is a DA converter bias constant current circuit, 204 is a DA converter that generates a reference voltage of the bias constant current circuit, and 205 is Reference voltage signal, 206 digital bypass circuit bypass path, 207 bypass switch, 208 bypass control signal, 209 digital integration circuit, 210 control processor, 211 analog integrator, 212 comparator, 213 internal DA conversion Showing the vessel.

If the control processor 210 determines that the conversion accuracy can be reduced based on the control information, the control processor 210 lowers the sampling frequency and, with respect to each of the blocks 211 to 213, which has an unnecessarily high speed, Via the DA converter 204, the bias current sources 201 to 203
In order to reduce power consumption, reduce the current value in. Further, in FIG. 3, two sets of integrator and comparator are provided for the high sampling frequency and the low sampling frequency, and they are switched by the control processor. In FIG. 3, 301 to 304 are high sampling frequency circuit / low sampling frequency circuit selection switches, 305 is a high sampling frequency analog integrator, 306 is a low sampling analog integrator, 307 is a high sampling frequency comparator, and 308. Is a low sampling frequency comparator, 309 is a high sampling frequency DA converter, 310 is a low sampling frequency DA converter, 31
Reference numeral 1 is a digital integrator, and 312 is a control processor.

The control method differs from the example shown in FIG. 2 in that
The low-speed analog integrator 306, the low-speed comparator 308, and the low-speed internal D are low in power consumption because the analog integrator, the comparator, and the internal DA converter are designed for low speed, instead of lowering the bias current when the conversion accuracy is reduced.
The point is that the A converter 310 is switched to. At this time, the power supply is cut off in each unused high-speed circuit. Stopping the operation of the digital integrator: In the interpolation type AD converter, when the conversion accuracy is reduced, the digital integrating circuit is stopped to bypass the signal and operate as a ΔΣ type, and the power is reduced by stopping the operation of the integrator. . This is a part of 206 to 209 shown in FIG. 2, 206 is a bypass path, 207 is a bypass switch,
Reference numeral 208 is a bypass switch control signal, and 209 is a digital integrator.

Further, along with this, a comparator and an internal DA
Although it is necessary to change the bit number of the converter, FIGS. 4 and 5 show configuration examples of the quantizer and the DA converter whose bit number is variable. FIG. 4A is a diagram showing a configuration example of a quantizer having a variable number of bits, where 401 is an analog input and 4
Reference numeral 02 is a comparator, 403 is a successive approximation register, 404 is a digital output, 405 is an internal DA converter, 406 is an internal DA converter output voltage, and 407 is a control signal from the control processor. Further, FIG. 4B is an output voltage-time characteristic diagram of the internal DA converter, and 410 is the output voltage,
411 is an output fixed time as a 1-bit quantizer, 41
Reference numeral 2 indicates a 2-bit quantizer output finalization time, 413 indicates a 3-bit quantizer output finalization time, and hereinafter, 414 to 416 indicate 4 to 6-bit quantizer output finalization times. The control processor controls at which point in time data is output based on the required number of quantization bits.

FIG. 5 shows an example of the configuration of the DA converter in which the bit number of the input data is variable. here,
An example of maximum 6 bits is shown. In the figure, 501 is a reference voltage source, 502 is an R-2R ladder resistor, 503 to 508 are groups of switches for setting an arbitrary number of bits, 509 is input digital data, and 510 to 515 are on / off corresponding to input data. Switch group 516, a current-voltage converter 517, and an analog output 517. In this DA converter, for example, in the case of 3-bit input, the switches 503 to 505 are opened and the switches 506 to 508 are closed,
Tilt the switches 513 to 515 to the ground side. Further, the switches 510 to 512 correspond to 3 bits of input data. Separation of unnecessary part of decimator due to reduction of sampling frequency: This is because unnecessary part of decimator is generated due to decrease of decimation ratio in decimator along with reduction of sampling frequency, so that unnecessary power is not consumed. To do so.

Here, when the decimation ratio is changed from 1/4 to 1/2, that is, when the oversunring ratio is 4
It shows the case where the doubling is changed to the doubling. This is shown in FIG. In the figure, 601 is input data of the decimator, 6
02 is output data, 603 and 604 are unnecessary portion separating switches, and 605 is a register group (4 of registers 1 to 4).
, 606 is a disconnection switch control signal, 607 is a register clock, 608 is a control processor, 609
Is a ROM for storing the coefficient of decimation. When the conversion accuracy is reduced, the control processor 608 lowers the sampling frequency and outputs the disconnection signal 606,
The unnecessary registers (here, registers 3 and 4) are separated, the register clock 603 is set to 1/2 cycle, and new coefficients are called from the ROM 609 to be changed. As a result, in addition to the decrease in the overall operating frequency, the power consumption is reduced by the amount of the separated circuit.

According to each of the above-described embodiments, the oversampling AD converter capable of saving the extra power in other cases is provided as a structure that can obtain the highest conversion accuracy only when necessary. Can be realized. The techniques described in each of the above embodiments can be appropriately combined and used. Next, as an application example of the present invention, FIG. 7 shows a configuration in which the above-described oversampling AD converter is applied to a mobile radio terminal. In the figure, a demodulation AD converter 701 is an over-sampling AD converter that changes the accuracy and reduces power consumption, and has a function of digitizing a received signal and passing it to the demodulator. Further, 702 is an antenna, 703 is a radio frequency receiving unit, 704 is a radio frequency transmitting unit, 705 is a modulator, and 706.
Is a demodulator, 707 is an encoded voice signal, 708 is a received electric field strength signal, 709 is for electric field strength signal, 710 is an input keypad, and 711 is a terminal user. In the mobile radio terminal, the demodulation AD converter 7 is operated in the following states.
Since the accuracy of 01 can be reduced, in this case, it is possible to reduce the conversion accuracy and reduce the power consumption.

(1) The received electric field strength is sufficiently high. (2) Fading is not a problem because it is stationary. (3) Signal with a large BER (Bit Error Rate) margin
A control channel signal for which error correction has been applied is being received. (4) Standby. (5) When the terminal user deems it necessary and reduces accuracy.
(When the remaining talk time becomes short and the battery life is desired to be extended) The control processor determines the state of the terminal placed based on the information from the user 711, the electric field strength signal 708, etc., and this is the above (1). When any of the conditions (5) to (5) is satisfied, the conversion accuracy is reduced and the power consumption is reduced by the procedure described above. According to the present embodiment, when the above-mentioned AD converter of the oversampling method is applied to a mobile radio terminal, it is possible to obtain the effect of suppressing the power consumption and extending the usable time of the terminal.

[0015]

As described above in detail, according to the present invention, it is possible to save the extra power in the other cases, as the structure that can obtain the highest conversion accuracy only when necessary. The remarkable effect that the oversampling AD converter can be realized is achieved. It is needless to say that the above-mentioned embodiments show examples of the present invention, and the present invention should not be limited to these. Further, it goes without saying that the techniques shown in the above-mentioned embodiments can be appropriately combined and used. The application range is not limited to mobile radio terminals.

[0016]

[Brief description of drawings]

FIG. 1 is a block configuration diagram (1) of an oversampling AD converter according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram (2) of an oversampling AD converter according to an embodiment of the present invention.

FIG. 3 is a block configuration diagram (No. 3) of an oversampling AD converter according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating the configuration and operation of a quantizer that can obtain arbitrary output bits.

FIG. 5 is a configuration diagram of a DA converter in which the number of input bits can be arbitrarily set.

FIG. 6 is a configuration diagram of a decimator with a variable decimation ratio.

FIG. 7 is a block diagram of a mobile radio terminal using an AD converter with variable accuracy.

[Explanation of symbols]

101: subtractor, 102: analog integrator, 103: comparator, 104: internal DA converter, 105: digital integrator, 106: control processor, 107: information for performing control, 108: decimator, 109: each Block control signal, 110: sampling frequency clock, 201: analog integrator bias constant current circuit, 20
2: Comparator bias constant current circuit, 203: DA converter bias constant current circuit, 204: Bias constant current circuit DA converter that generates a reference voltage, 205: Reference voltage signal, 206: Digital integration circuit bypass path, 207:
Bypass switch, 208: Bypass control signal, 20
9: Digital integrator, 211: Analog integrator, 21
2: Comparator, 213: Internal DA converter, 301-
304: High speed circuit / low speed circuit selection switch, 305: High sampling frequency analog integrator, 306: Low sampling frequency analog integrator, 307: High sampling frequency comparator, 308: Low sampling frequency comparator, 309: High Sampling frequency DA converter, 310: Low sampling frequency DA converter, 311: Digital integrating circuit, 312: Control processor, 401: Analog input, 402: Comparator, 4
03: successive approximation register, 404: digital output, 4
05: internal DA converter, 406: internal DA converter output voltage, 407: control signal from control processor, 410:
Output voltage, 411: 1-bit quantized output fixed time, 41
2: 2 bit quantized output fixed time, 413: 3 bit quantized output fixed time, 414: 4 bit quantized output fixed time, 415: 5 bit quantized output fixed time, 416: 6
Bit quantized output fixed time, 501: reference voltage source, 50
2: R-2R ladder resistance, 503 to 508: Switch group for setting arbitrary number of input bits, 509: Input digital data, 510 to 515: Switch group to be turned on / off corresponding to input data, 516: Current voltage Converter, 51
7: analog output, 601: decimator input data,
602: output data, 603, 604: unnecessary part disconnecting switch, 605: register group, 606: disconnecting switch control signal, 607: register clock, 60
8: control processor, 609: decimation coefficient storage ROM, 701: oversampling AD converter (AD converter for coded audio signal) with variable precision, 702:
Antenna, 703: Radio frequency receiver, 704: Radio frequency transmitter, 705: Modulator, 706: Demodulator, 707: Encoded audio signal, 708: Electric field strength signal, 709:
For electric field strength signal, 710: input keypad, 711: terminal user.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Hatano 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. An analog integrator, a comparator for quantizing the output of the analog integrator, a digital integrator for cumulatively adding the output of the comparator, and an internal DA converter for DA converting the output of the digital integrator. In the oversampling AD converter in which the difference between the analog output of the internal DA converter and the analog input to be detected is used as the input of the analog integrator, the analog integrator, the comparator, and the digital integrator are included. , Internal DA
An oversampling AD converter characterized in that the clock frequency supplied to the converter is configured to be changed according to the required minimum AD conversion accuracy. 2. An analog integrator, a comparator for quantizing the output of the analog integrator, a digital integrator for cumulatively adding the output of the comparator, and an internal DA converter for DA converting the output of the digital integrator. In the oversampling AD converter in which the difference between the analog output of the internal DA converter and the analog input to be detected is used as the input of the analog integrator, when the AD conversion accuracy is reduced, the analog integrator is included. An oversampling AD converter characterized by reducing a bias current in a comparator and an internal DA converter. 3. An analog integrator, a comparator for quantizing the output of the analog integrator, a digital integrator for cumulatively adding the output of the comparator, and an internal DA converter for DA converting the output of the digital integrator. In the oversampling AD converter, which includes the difference between the analog output of the internal DA converter and the analog input to be detected as an input of the analog integrator, the analog integrator, the comparator, and the internal DA conversion. An oversampling AD converter characterized in that two systems, a high bias current circuit / a low bias current circuit, are provided, and these are switched according to the AD conversion accuracy. 4. An analog integrator, a comparator for quantizing the output of the analog integrator, a digital integrator for cumulatively adding the output of the comparator, and an internal DA converter for DA converting the output of the digital integrator. In the oversampling AD converter in which the difference between the analog output of the internal DA converter and the analog input to be detected is used as the input of the analog integrator, the conversion accuracy of the digital integrator is reduced when the conversion accuracy is reduced. An oversampling AD converter characterized by stopping the operation. 5. The digital integrator has a decimator for noise removal and data frequency reduction by averaging the outputs, and the decimator, when the sampling frequency is lowered,
The oversampling AD converter according to claim 1, characterized in that the unnecessary portion is separated.