JPH03101047U - - Google Patents
Info
- Publication number
- JPH03101047U JPH03101047U JP896090U JP896090U JPH03101047U JP H03101047 U JPH03101047 U JP H03101047U JP 896090 U JP896090 U JP 896090U JP 896090 U JP896090 U JP 896090U JP H03101047 U JPH03101047 U JP H03101047U
- Authority
- JP
- Japan
- Prior art keywords
- conversion
- during
- time constant
- switching means
- resolution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 28
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図a,bはこの考案のAD変換処理装置の
クレーム対応図、第1図cはこの考案のAD変換
処理装置の一実施例を示す構成図、第2図は従来
のAD変換処理装置を示す構成図、第3図はAD
変換値のフオーマツト、第4図は従来のAD変換
処理装置にマルチプレクサを接続した場合の構成
図である。
1……コンパレータ、2……DA変換器、3…
…CPU、4……可変ゲインアンプ、5a……ロ
ーパスフイルタ、6……ゲイン決定手段、7……
時定数切換手段、8……AD変換分解能切換手段
、10……逐次比較型AD変換回路、D1,D2
……デジタルコード、SW……スイツチ、R1,
R2……抵抗、C……コンデンサ、V1……入力
電圧、VGI……出力電圧、VDA……DA変換
器の出力電圧。
Figures 1a and b are complaint correspondence diagrams of the AD conversion processing device of this invention, Figure 1c is a block diagram showing an embodiment of the AD conversion processing device of this invention, and Figure 2 is a conventional AD conversion processing device. A configuration diagram showing the configuration, Figure 3 is AD
FIG. 4 is a block diagram of a conventional AD conversion processing device in which a multiplexer is connected. 1... Comparator, 2... DA converter, 3...
...CPU, 4...Variable gain amplifier, 5a...Low pass filter, 6...Gain determining means, 7...
Time constant switching means, 8... AD conversion resolution switching means, 10... Successive approximation type AD conversion circuit, D1, D2
...Digital code, SW...Switch, R1,
R2...Resistor, C...Capacitor, V1 ...Input voltage, VGI...Output voltage, VDA...Output voltage of the DA converter.
Claims (1)
インを任意に制御し得る可変ゲインアンプと、該
可変ゲインアンプの次段に配置された逐次比較型
AD変換回路とを具備したAD変換処理装置にお
いて、 1回目のAD変換動作により得られたAD変換
値に基づいて2回目のAD変換動作時の可変ゲイ
ンアンプのゲインを決定するゲイン決定手段と、 前記ローパスフイルタの時定数を大小2段階に
切り換える時定数切換手段とを有し、 前記1回目のAD変換動作時には前記時定数切
換手段により前記ローパスフイルタの時定数を小
に切り換え、前記2回目のAD変換動作時には前
記時定数切換手段により前記ローパスフイルタの
時定数を大に切り換えるようにしたことを特徴す
るAD変換処理装置。 (2) ゲインを任意に制御し得る可変ゲインアン
プと、該可変ゲインアンプの次段に配置された逐
次比較型AD変換回路とを具備したAD変換処理
装置において、 1回目のAD変換動作により得られたAD変換
値に基づいて2回目のAD変換動作時の可変ゲイ
ンアンプのゲインを決定するゲイン決定手段と、 AD変換動作時の分解能を大小2段階に切り換
えるAD変換分解能切換手段と有し、 前記1回目のAD変換動作時には前記AD変換
分解能切換手段により前記AD変換分解能を小に
切り換え、前記2回目のAD変換動作時には前記
AD変換分解能切換手段により前記AD変換分解
能を大に切り換えるようにしたことを特徴とする
AD変換処理装置。[Claims for Utility Model Registration] (1) A variable gain amplifier that is equipped with a low-pass filter in its output stage and whose gain can be arbitrarily controlled, and a successive approximation type AD conversion circuit that is disposed at the next stage of the variable gain amplifier. An AD conversion processing device comprising: gain determining means for determining the gain of the variable gain amplifier during the second AD conversion operation based on the AD conversion value obtained from the first AD conversion operation; and a time constant switching means for switching a time constant into two stages, large and small, the time constant switching means switching the time constant of the low-pass filter to a small value during the first AD conversion operation, and during the second AD conversion operation. An AD conversion processing device, characterized in that the time constant switching means switches the time constant of the low-pass filter to a large value. (2) In an AD conversion processing device equipped with a variable gain amplifier whose gain can be arbitrarily controlled and a successive approximation type AD conversion circuit placed at the next stage of the variable gain amplifier, the gain obtained by the first AD conversion operation is gain determining means for determining the gain of the variable gain amplifier during the second AD conversion operation based on the AD conversion value obtained; and AD conversion resolution switching means for switching the resolution during the AD conversion operation into two levels, large and small; During the first AD conversion operation, the AD conversion resolution switching means switches the AD conversion resolution to a small value, and during the second AD conversion operation, the AD conversion resolution switching means switches the AD conversion resolution to a large value. An AD conversion processing device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP896090U JPH03101047U (en) | 1990-02-02 | 1990-02-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP896090U JPH03101047U (en) | 1990-02-02 | 1990-02-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03101047U true JPH03101047U (en) | 1991-10-22 |
Family
ID=31512570
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP896090U Pending JPH03101047U (en) | 1990-02-02 | 1990-02-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03101047U (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006344697A (en) * | 2005-06-07 | 2006-12-21 | Sharp Corp | Multilayer wiring board and its manufacturing method |
JP2018078568A (en) * | 2016-11-13 | 2018-05-17 | アナログ ディヴァイスィズ インク | Dynamic anti-alias filter for analog-to-digital converter front end |
CN108712157A (en) * | 2016-11-13 | 2018-10-26 | 美国亚德诺半导体公司 | Quantizing noise in feedback loop is eliminated |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS538045A (en) * | 1976-06-30 | 1978-01-25 | Fujitsu Ltd | Automatic range selecting type a-d converter |
JPS59132230A (en) * | 1983-01-19 | 1984-07-30 | Hitachi Ltd | Analog-digital converting circuit |
JPH01309418A (en) * | 1988-02-19 | 1989-12-13 | Silicon Syst Inc | Automatic gain controller |
-
1990
- 1990-02-02 JP JP896090U patent/JPH03101047U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS538045A (en) * | 1976-06-30 | 1978-01-25 | Fujitsu Ltd | Automatic range selecting type a-d converter |
JPS59132230A (en) * | 1983-01-19 | 1984-07-30 | Hitachi Ltd | Analog-digital converting circuit |
JPH01309418A (en) * | 1988-02-19 | 1989-12-13 | Silicon Syst Inc | Automatic gain controller |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006344697A (en) * | 2005-06-07 | 2006-12-21 | Sharp Corp | Multilayer wiring board and its manufacturing method |
JP2018078568A (en) * | 2016-11-13 | 2018-05-17 | アナログ ディヴァイスィズ インク | Dynamic anti-alias filter for analog-to-digital converter front end |
CN108075777A (en) * | 2016-11-13 | 2018-05-25 | 美国亚德诺半导体公司 | For the dynamic frequency overlapped-resistable filter of analog-digital converter front end |
CN108712157A (en) * | 2016-11-13 | 2018-10-26 | 美国亚德诺半导体公司 | Quantizing noise in feedback loop is eliminated |
CN108075777B (en) * | 2016-11-13 | 2021-09-14 | 美国亚德诺半导体公司 | Dynamic anti-aliasing filter for analog-to-digital converter front-end |
CN108712157B (en) * | 2016-11-13 | 2022-04-29 | 美国亚德诺半导体公司 | Quantization noise cancellation in a feedback loop |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0901232A3 (en) | Voltage comparator, operational amplifier and analog-to-digital conversion circuit employing the same | |
JPH03101047U (en) | ||
KR920020859A (en) | Dual Slope Integrating A / D Converter | |
JP3483565B2 (en) | Method and apparatus for integrating multiple input signals | |
JPH07221642A (en) | Semiconductor integrated circuit | |
SU938392A1 (en) | Analog-digital converter | |
JPS6457813A (en) | Amplifier | |
JPH0316740U (en) | ||
JPS56168427A (en) | Analog-to-digital converter | |
JPH0186328U (en) | ||
JPH03109435U (en) | ||
JPS61114375U (en) | ||
JPS6316727U (en) | ||
JPH0475435U (en) | ||
JPS5888447U (en) | Analog to digital converter | |
JPS63196171U (en) | ||
JPH021932U (en) | ||
JPS58170219A (en) | Integration type variable gain analog-digital converter | |
JPS5951780B2 (en) | Logarithmic AD converter | |
JPH0224619U (en) | ||
JPH01177618U (en) | ||
JPH0480135U (en) | ||
JPH0165529U (en) | ||
JPH03101033U (en) | ||
JPS637823U (en) |