JPH07221642A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the conversion accuracy of a D/A converter by lowering the gate voltage of the p-type MOS of a CMOS analog switch in a voltage lowering circuit and raising the gate potential of an n-type MOS in a boosting circuit. CONSTITUTION:A CMOS transmission gate 4a is composed of the CMOS analog switch 9 for which the p-type and n-type MOSes 9a and 9b are parallelly connected, an inverter 10 for which resistor decoder 7 are inputted and the output is connected to the gate inverter 12 and output is connected to the gate electrode of the p-type MOS 9a and the inverter 11 for which signals from the decoder 7 are inputted and the output is connected to the gate electrode of the n-type MOS 9b. Then, the voltage lowering circuit 13 is connected to the grounded electrode side of the p-type MOS 9a and the gate potential of the p-type MOS 9a is lowered at the time of the operation of the CMOS analog switch 9. Also, the boosting circuit 14 is connected to the power supply electrode side of the n-type MOS 9b and the gate potential of the n-type MOS 9b is raised at the time of the operation of the CMOS analog switch 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and is particularly effective when applied to a semiconductor integrated circuit equipped with a D / A converter for converting a digital signal into an analog signal.

[0002]

2. Description of the Related Art A semiconductor integrated circuit such as a microcomputer or DSP (digital signal processor) has an internal CP.
A D / A converter that converts a signal digitally processed by U or the like into an analog signal and outputs the analog signal is used. The semiconductor integrated circuit as described above uses a D / A converter of a resistance voltage dividing type, which has relatively high accuracy and is essentially monotonic. FIG. 6 shows a resistance voltage dividing type D / A converter 23.
The circuit configuration of is shown. The resistor group 24, one end of which is connected to the power electrode AVcc and the other end thereof to the ground electrode AVss, has resistors R of the same value, all connected in series to the n-th power of 2, and varies depending on the number of resistors connected. It is possible to output the voltage (analog signal) of the value. At the connection point between these resistors R and R, the resistance selection switch group 26 (2 to the n-th power-1) are all connected in parallel, and by turning one of them into the ON state, An analog signal of the voltage at the connection point can be output to the outside. This D
The / A converter 23 inputs the digital signal to the decoder 27, and the resistance selection signal 31 for outputting an analog signal corresponding to the digital signal is input to the decoder 2
By turning on the selected resistance selection switch output from 7, the input digital signal is converted into an analog signal.

Regarding the resistance voltage dividing type D / A converter (converter), for example, "Introduction to A / D converter"
(Published by Ohmsha), pages 152 to 153.

[0004]

A CMOS transmission gate whose ON resistance does not change much depending on an input analog voltage is used as the resistance selection switch used in the above-mentioned resistance division type D / A converter. As shown in FIG. 7, the CMOS transmission gate 26a is driven by applying voltages of opposite polarities to the respective gates of the CMOS analog switch 29 including the p-type MOS 29a and the n-type MOS 29b connected in parallel.

However, since the number of semiconductor integrated circuits operated by a low voltage is increasing recently, CMOS
The transmission gate is also forced to operate at a low voltage. When the CMOS transmission gate 26a is operated at a low voltage, the AVcc voltage is lowered. Therefore, the n-type MOS of the CMOS analog switch 29 is
The gate potential of 29b drops. Therefore, VGS (gate-source voltage) of the CMOS analog switch 29
Decreases and the ON resistance increases. When the ON resistance of the CMOS transmission gate 26 increases, a difference occurs between the input voltage and the output voltage of the CMOS transmission gate 26a due to the influence of the external load resistance 28 (FIG. 6). If this voltage difference widens, the D / A conversion accuracy will deteriorate.

Therefore, an object of the present invention is to improve the conversion accuracy of a D / A converter incorporated in a semiconductor integrated circuit operating at a low voltage.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the step-down circuit lowers the gate potential of the p-type MOS of the CMOS analog switch that constitutes the CMOS transmission gate that serves as the resistance selection switch of the D / A converter, and the gate potential of the n-type MOS is raised by the booster circuit. is there.

[0009]

According to the above means, the decrease in VGS of the CMOS analog switch due to the low voltage operation of the semiconductor integrated circuit can be suppressed and the ON resistance can be prevented from increasing, so that the deterioration of the D / A conversion accuracy due to the influence of the external additional resistance can be prevented. be able to.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a circuit configuration when a CMOS transmission gate is used for the resistance selection switch of the D / A converter 1. In the D / A converter 1, resistors R having the same value are connected in series to the n-th power of 2 and one end thereof is connected to the power supply electrode AVcc and the other end thereof is connected to the ground electrode AVss, and the resistor R. From the connection point of
A CMOS transmission gate group 4 which is a resistance selection switch that outputs an analog signal having a voltage corresponding to the number of resistors R, and a CMOS transmission gate selection signal that outputs an analog signal corresponding to the digital signal by inputting a digital signal It is composed of a decoder 7 for outputting. The p-type MOSs 5a and 5b are resistance selection switches that output the analog signal of the highest voltage, and the n-type MOSs 6a and 6b are resistance selection switches that output the analog signal of the lowest voltage. These CMOS transmission gate groups 4,
A resistance selection switch group including p-type MOSs 5a and 5b and n-type MOSs 6a and 6b is connected in parallel for each resistance R.

FIG. 2 is a diagram showing a circuit configuration of the CMOS transmission gate 4a of the present invention. In the CMOS transmission gate 4a, a CMOS analog switch 9 in which a p-type MOS 9a and an n-type MOS 9b are connected in parallel, a resistance selection signal 15 from a decoder 7 is input via an inverter 12, and an output is output to the gate electrode of the p-type MOS 9a. The connected first inverter 10 and the signal from the decoder 7 are input, and the output is composed of the second inverter 11 connected to the gate electrode of the n-type MOS 9b. p-type M
The step-down circuit 13 is connected to the ground electrode side of the OS 9a, and when the CMOS analog switch 9 operates, the p-type MOS
The gate potential of 9a is lowered. In addition, the n-type MOS 9b
The booster circuit 14 is connected to the power supply electrode side of
During the operation of the MOS analog switch 9, the gate potential of the n-type MOS 9b is raised. FIG. 3 is a circuit diagram of the step-down circuit 13. The step-down circuit 13 includes the first switch 1 provided in series between the power supply electrode AVcc and the ground electrode AVss.
3a and the second switch 13b, and the first switch 13
The capacitor 13d has one electrode connected between a and the second switch 13b, and the other electrode of the capacitor 13d and a changeover switch 13c for switching connection to either the ground electrode AVss or the output. ing. The operation of the step-down circuit 13 is as follows.
Connect 3c to AVss, turn off second switch 13b
Then, by turning on the first switch 13a, the capacitor 13d is charged with the AVcc voltage.
Then, the first switch 13a is turned off, the second switch 13b is turned on, and the changeover switch 13c is set to the output side, whereby the -AVcc voltage is output. This voltage is output from the first inverter 10 and lowers the gate potential of the p-type MOS 9a. FIG. 4 is a circuit diagram of the booster circuit 14. The booster circuit 14 includes a first switch 14 provided in series between the power supply electrode AVcc and the ground electrode AVss.
a and the second switch 14b, and the first switch 14a
And a second switch 14b, one electrode of which is connected to the capacitor 14d, and the other electrode of the capacitor 14d and a changeover switch 14c for switching connection to either the power supply electrode AVcc or the output. There is.
The operation of the booster circuit 14 is as follows.
Connected to AVcc, second switch 14b turned on, first
By turning off the switch 14a, the capacitor 14d is charged with the AVcc voltage. Next, the first switch 14a is turned on, the second switch 14b is turned off,
By setting the changeover switch 14c to the output side, AVc
A voltage of c × 2 is output. This voltage is output from the second inverter 11 and raises the gate potential of the n-type MOS 9b. The switches of the step-down circuit 13 and the step-up circuit 14 are controlled by clock pulses or the like. By providing the step-down circuit 13 and the step-up circuit 14,
Even if the semiconductor integrated circuit is operated at a low voltage, the VGS of the CMOS analog switch 9 is suppressed from decreasing, so that the ON resistance can be decreased.

Next, the operation of the D / A converter 1 will be described. First, the digital signal corresponding to the analog signal of the voltage to be output is input to the decoder 7. Decoder 7
Outputs a resistance selection signal 15 to the CMOS transmission gate 4a that outputs a voltage corresponding to the input digital signal. The resistance selection signal 15 output from the decoder 7 is input in parallel to the first inverter 10 and the second inverter 11, respectively. At that time, a signal having a polarity opposite to that of the second inverter 11 is input to the first inverter 10 via the inverter 12. Since the "High" voltage is input from the inverter 12 to the first inverter 10, the -AVcc voltage is output from the step-down circuit 13 and applied to the gate electrode of the p-type MOS 9a.
As a result, the gate potential of the p-type MOS 9a drops and V
Suppress the decrease in GS. On the other hand, since the "Low" voltage is input to the second inverter 11, the voltage of AVcc × 2 is output from the booster circuit 14 and applied to the gate electrode of the n-type MOS 9b. This raises the gate potential of the n-type MOS 9b and suppresses the decrease of VGS. As described above, even when the semiconductor integrated circuit operates at a low voltage, the step-down circuit 13 and the step-up circuit 14 suppress the decrease in VGS of the CMOS analog switch 9, so that the ON resistance of the CMOS analog switch 9 decreases. Therefore, the external load resistance 8
It is possible to suppress the decrease of the output voltage due to the influence of, and to suppress the spread of the voltage difference between the input voltage and the output voltage. As a result, the conversion accuracy of the D / A converter 1 can be improved.

The operation and effect of the present invention will be described below.

(1) Since the CMOS transmission gate is provided with the step-down circuit for lowering the gate potential of the p-type MOS of the CMOS analog switch and the step-up circuit for raising the gate potential of the n-type MOS, the semiconductor integrated circuit can be operated at a low voltage. Even if it is operated at 1, it is possible to suppress a decrease in VGS of the CMOS analog switch.

(2) VGS of CMOS analog switch
Is suppressed, the ON resistance of the CMOS analog switch can be reduced.

(3) Since the ON resistance of the CMOS analog switch is reduced, the reduction of the output voltage due to the influence of the external load resistance 8 can be suppressed, and the spread of the voltage difference between the input voltage and the output voltage can be suppressed.

(4) Since the spread of the voltage difference between the input voltage and the output voltage is suppressed, it is possible to improve the conversion accuracy of the D / A converter built in the semiconductor integrated circuit operating at a low voltage.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
As shown in FIG. 5, a second inverter 19 having a booster circuit 21 connected to the power electrode side and a step-down circuit 20 on the ground electrode side.
Are connected in series with the first inverter 18 connected to the p-type MOS 17 of the CMOS analog switch 17
The same effect as described above can be obtained by a circuit configuration in which a signal is applied to the gate electrode of a and to the gate electrode of the n-type MOS 17b through the second inverter 19 only. In this case, the number of inverters is reduced by one as compared with the CMOS transmission gate 4 of the above embodiment,
The number of inverters can be reduced by about the number of switches of the D / A converter, and the area occupied by the resistance selection switch in the D / A converter can be reduced.

In the above embodiment, an example in which the present invention is applied to a semiconductor integrated circuit provided with a D / A converter has been described. However, for example, an A / D converter, an analog multiplexer, a filter circuit, etc. The present invention can be widely applied to a circuit using an analog switch, and particularly, the present invention can be applied to a semiconductor integrated circuit requiring a low voltage operation such as a digital signal processor and a microcomputer, and has a particular effect.

[0020]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the gate voltage of the p-type MOS of the CMOS analog switch which constitutes the CMOS transmission gate which serves as the resistance selection switch of the D / A converter is lowered by the step-down circuit, and the gate potential of the n-type MOS is raised by the step-up circuit. By doing so, even if the semiconductor integrated circuit is operated at a low voltage, a decrease in VGS of the CMOS analog switch and a decrease in ON resistance due to the operation are suppressed, so that the spread of the voltage difference between the input and the output can be suppressed. Therefore, it is possible to improve the conversion accuracy of the D / A converter incorporated in the low-voltage semiconductor integrated circuit.

[0022]

[Brief description of drawings]

FIG. 1 is a CMOS circuit for a resistance selection switch of a D / A converter.
It is a figure which shows the circuit structure at the time of using a transmission gate.

FIG. 2 is a diagram showing a circuit configuration of a CMOS transmission gate which is an embodiment of the present invention.

FIG. 3 is a circuit diagram of a step-down circuit according to the present invention.

FIG. 4 is a circuit diagram of a booster circuit of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a CMOS transmission gate which is another embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a resistance voltage division type D / A converter.

FIG. 7 is a diagram showing a circuit configuration of a conventional CMOS transmission gate.

[Explanation of symbols]

1 ... D / A converter, 2 ... resistor group, 3 ... connection point, 4
... CMOS transmission gate group, 4a ... C
MOS transmission gate, 5a, 5b ... p-type MOS, 6a, 6b ... n-type MOS, 7 ... decoder,
8 ... External load resistance, 9 ... CMOS analog switch, 9a ... P-type MOS, 9b ... N-type MOS, 10 ...
... first inverter, 11 ... second inverter, 12
...... Inverter, 13 ...... Step-down circuit, 13a, 13b ...
... switch, 13c ... changeover switch, 13d ... capacitor, 14 ... booster circuit, 14a, 14b ... switch, 14c ... changeover switch, 14d ... capacitor,
15 ... Resistance selection signal, 16 ... CMOS transmission gate, 17 ... CMOS analog switch, 1
7a ... p-type MOS, 17b ... n-type MOS, 18 ...
1st inverter, 19 ... 2nd inverter, 20 ...
... Step-down circuit, 21 ... Step-up circuit, 22 ... Resistance selection signal, 23 ... D / A converter, 24 ... Resistor group, 25 ...
Connection point, 26 ... Resistance selection switch, 26a ... CMO
S transmission gate, 27 ... Decoder, 28
...... External load resistance, 29 …… CMOS analog switch, 30 …… Inverter, 31 …… Resistance selection signal,

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 21/8238 27/092 H03K 17/00 E 9184-5J H03M 1/76

Claims (6)

[Claims] 1. A resistance group in which a power electrode is connected to one end and a ground electrode is connected to the other end, and a plurality of resistors having the same resistance value are connected in series, and a resistor provided in parallel at each connection point of the resistors. A selection switch group and a decoder that outputs a resistance selection signal that turns on a resistance selection switch that outputs an analog signal corresponding to the digital signal in the resistance selection switch group by inputting a digital signal. In the semiconductor integrated circuit including the D / A converter, the resistance selection switch group includes a CMOS analog switch composed of a p-type MOS and an n-type MOS connected in parallel, and a step-down circuit on the ground electrode side. A first inverter which is connected and whose output is connected to the gate electrode of the p-type MOS;
A booster circuit is connected to the power electrode side, and the output is the n-type MOS
2. A semiconductor integrated circuit comprising a CMOS transmission gate composed of a second inverter connected to the gate electrode of. 2. The step-down circuit includes a first switch and a second switch, which are provided in series between a power supply electrode and a ground electrode, and between the first switch and the second switch. 2. The semiconductor device according to claim 1, comprising a capacitor to which one electrode is connected, and a changeover switch connectable to either the other electrode of the capacitor and the ground electrode or the output. 3. The booster circuit comprises a first switch and a second switch which are provided in series between a power supply electrode and a ground electrode, and between the first switch and the second switch. 3. The semiconductor according to claim 1 or 2, comprising a capacitor to which one electrode is connected, and a changeover switch connectable to the other electrode of the capacitor and either a power supply electrode or an output. apparatus. 4. A resistor group in which a power electrode is connected to one end and a ground electrode is connected to the other end, and a plurality of resistors having the same resistance value are connected in series, and resistors provided in parallel at each connection point of the resistors. A selection switch group and a decoder that outputs a resistance selection signal that turns on a resistance selection switch that outputs an analog signal corresponding to the digital signal in the resistance selection switch group by inputting a digital signal. In the semiconductor integrated circuit including the D / A converter, the resistance selection switch group includes a CMOS analog switch composed of a p-type MOS and an n-type MOS connected in parallel, and a step-down circuit on the ground electrode side. A first inverter which is connected and whose output is connected to the gate electrode of the p-type MOS;
A booster circuit is connected to the power electrode side, and the output is the n-type MOS
And a second inverter connected to the first inverter, and a CMOS transmission gate including a second inverter connected to the first inverter. 5. The step-down circuit includes a first switch and a second switch, which are provided in series between a power supply electrode and a ground electrode, and between the first switch and the second switch. 5. The semiconductor device according to claim 4, comprising a capacitor having one electrode connected thereto, and a changeover switch connectable to the other electrode of the capacitor and either the ground electrode or the output. 6. The booster circuit comprises a first switch and a second switch which are provided in series between a power supply electrode and a ground electrode, and between the first switch and the second switch. 6. The semiconductor according to claim 4 or 5, comprising a capacitor to which one electrode is connected, and a changeover switch connectable to either the other electrode of the capacitor and the power supply electrode or the output. apparatus.