JPH01253309A - Level shift circuit - Google Patents

Abstract

PURPOSE:To reduce the element area as well as the power consumption by using a CMOS circuit where the drains of n and p type MOS FETs are con nected to each other at two stages respectively and decreasing relatively the dimensions of one of both CMOS circuits that has the smaller load connected to the drain. CONSTITUTION:A 2nd CMOS consisting of MOS FET MN2 and MP2 has its dimensions nXN1 and nXP1 equal to (n) times as much as the dimensions XN1 and XP1 of a 1st CMOS consisting of MOS FET MN1 and MP1. As a result, the fact that (load capacity CL1>> parasitic capacity CP1) is satisfied and there fore both FET MN1 and MP1 can be driven fast enough despite their small dimensions. Furthermore, the through currents of both MN1 and MP1 are re duced owing to their small dimensions. As a result, the power consumption is reduced together with the big reduction of the element area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a level shift circuit that converts a signal with a certain voltage amplitude into a signal with a different voltage amplitude. The present invention relates to a level shift circuit for a high voltage IC that converts a logic signal into a high voltage flat panel drive signal.

[Conventional technology]

Conventionally, this type of level shift circuit consists of one CMOS circuit in which the drains of an N-type MOSFET and a P-type MOSFET are connected together, and another CMOS circuit having the same element size (so-called dimension), as shown in FIG. Prepare a circuit, alternately connect the gates of the P-type MOSFETs of one CMOS circuit to the common drain of the other CMOS circuit, input a low voltage signal of opposite polarity to each gate of the N-type MOSFET, and connect the gates of the P-type MOSFETs of one CMOS circuit to the common drain of the other CMOS circuit. A high voltage signal was extracted from the

[Problem to be solved by the invention]

In the conventional technology described above, although the dimensions of the N type and P type of each CMOS are different, the corresponding ones in the two 0MO8s are the same.

Since the current capacity of N-type and P-type MOS FETs is different in dimensions such as gate length and gate width W, the dimension ratio of N-type and P-type is generally different in a single CMOS circuit. . Normally, in this type of level shift circuit, one common drain is taken out as an output or connected to the gate of another CMOS circuit, as shown in FIG. 3, and the other common drain is not connected to the outside. In this way, two-tier CMO
Since the loads connected to the common drain in each S are different, if the two stages of 0MO8 are made to have the same dimension, the dimension is determined so that it can sufficiently drive a heavy load, so it will be larger than the light load 0MO8. This results in waste and increases the device area.

Further, when a signal changes, a through current flows from the P type to the N type, and the larger the dimension, the larger this current, so an extra large dimension leads to an increase in power consumption.

[Means to solve the problem]

The level shift circuit of the present invention includes N-type and P-type MOS
Two stages of CMOS circuits are prepared in which the drains of the FETs are connected together, and the gates of the P-type MOSFETs in one CMOS circuit are connected alternately to the common drain of the other CMOS circuit, and a low voltage signal is applied to the gate of the N-type MOSFET. In a type of level shift circuit that inputs a high voltage signal and takes out a high voltage signal from a common drain, one of the two stages of CMOS circuits is
The dimension of the CMOS circuit with a smaller load connected to the drain is set relatively small.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. MN 1
, MN2 is an N-type MOS FET, and since a high voltage is applied to the drain in the circuit, a so-called off-cellar MOS structure is used in which a low concentration layer is placed in the drain to increase the withstand voltage of the drain.

MPI and MP2 are P-type MOSFETs, and a high voltage is applied to the drain and gate in the circuit, so in addition to using the above-mentioned offset structure, the gate oxide film is thickened to increase the breakdown voltage of the gate. The load capacitance C1 represents a load connected to the outside or an equivalent capacitance of the next stage circuit.

Since the gate length of a MOSFET is usually determined by the process, the gate width W changes depending on the dimension of the device. M.O.S.
First 0MO consisting of FET MNI, MPI
3 dimension X or n times the dimension n XNI r n Xpr of IIXPI as MOS F'ET
MN2. The second 0MO8(7) dimension is composed of MP2. n is approximately determined by the ratio of the load capacitance it CL□ and the parasitic capacitance ft Cp +, and n''; CLl
/ Cpl. Normally, since CLl>Cp+, n>1.

The absolute value of x, , , X, , is determined by the required speed, current capacity of the power consumption MOSFET, etc.

The low voltage signal IN and the low voltage signal IN are input to each terminal 3 and 4 as signals of opposite polarity, respectively. Now signal I
When N is logic level L and signal IN is "'H", MOS
FET MNI is off, MOS FET MN2
turns on, the gate potential of MOS FET MPI decreases, MOS FET MPI turns on, and MOS
The drain potential of FET MPI rises and the MOS
Turn off FET MP2 and connect high voltage signal terminal 5.
becomes “H”. Conversely, signal lower X is ``H'', signal IN
When the voltage is set to "L", the high voltage signal terminal 5 becomes "L".

In this way, the high voltage signal at the terminal 5 can be controlled by the low voltage signals IN, IN.

As mentioned above, load capacitance CL 1) Parasitic capacitance ft Cp
1, so even if the dimensions of the MOS FETs MNI and MPI are small, they can be driven sufficiently fast. MOSFE
When T MNI changes from off to on, MOS F
Since ET MPI is still on - there is a period of on-on, MOS FET MPI, MNI
A through current flows through the MOSFET MNI, M
By reducing the dimension of PI, this through current can be reduced and power consumption can be reduced. Further, by reducing the dimension, it is possible to significantly reduce the element area.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

Similar to the embodiment shown in FIG. 1, MOS FETs MN3°MN4. MP3. All drains of MP4 have high voltage resistance,
MOS FET MN3 and MN4) 1 gate also has a high breakdown voltage. In this embodiment, since a low voltage signal is input to the P-type MOSFET side, it can be converted into a negative high voltage signal. Similar to the embodiment shown in FIG. 1, a small level shift circuit with low power consumption can be constructed.

〔Effect of the invention〕

As explained above, in the embodiment of FIG.
S FET MNI, MPI, MN2. Match the dimension of MP2 to the capacitance connected to the drain, and connect a MOS FET with a small capacitance equivalent to a parasitic capacitance.
The dimensions of MNI and MPI are small, and the MOS FET MN2 is connected to a large load capacity. By increasing the dimension of MP2, an optimal dimension for achieving a certain speed can be configured, and a significant reduction in element area and power consumption can be realized compared to level shift circuits of conventional technology.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit diagram of one embodiment of the present invention, FIG. 2 shows an equivalent circuit diagram of another embodiment of the invention, and FIG. 3 shows an equivalent circuit diagram of a conventional circuit. MN1~6...N-type MOSFET%MP1~6
・・・・・・P-type MOSFET%CPI~CP! ...
... Parasitic capacitance, OLI ~ CL3 ... Load capacitance. 1...Ground, 2...High voltage power supply, 3...Low voltage signal tile, 4...Low voltage signal IN, 5... ...High voltage signal, 6...
・Ground, 7... High voltage negative power supply, 8...
...Low voltage signal IN, 9...Low voltage signal IN
, 10... High voltage signal, 11... Ground, 12... High voltage power supply, 13...
・Low voltage signal IN, 14...Under the low voltage signal,
15...High voltage signal. Agent: Patent Attorney Shinsuke Uchihara/Tuman 3

Claims (1)

[Claims] Two stages of CMOS circuits are prepared in which the drains of an N-type MOSFET and a P-type MOSFET are connected, and the gates of the MOSFETs of one conductivity type in one CMOS circuit are alternately connected to the common drain of the other CMOS circuit, and the gates of the MOSFETs of one conductivity type in one CMOS circuit are connected alternately to the common drain of the other CMOS circuit. Input the voltage amplitude signal at the gate of the MOSFET,
A level shift circuit that takes out signals of different voltage amplitudes from a common drain, the level shift circuit characterized by making the element size of the CMOS circuit with a smaller load connected to the drain relatively small among two stages of CMOS circuits. .