JP2655913B2 - FET semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an FET (field effect transistor) semiconductor integrated circuit, and more particularly to an FET semiconductor integrated circuit formed on a compound semiconductor substrate such as gallium arsenide. .

(Prior art) Conventionally, the technology in such a field is disclosed in
Japanese Patent Application Laid-Open No. 6412 and Japanese Patent Application Laid-Open No. 62-172817. Hereinafter, this configuration will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a conventional FET semiconductor integrated circuit described in the above document.

This FET semiconductor integrated circuit includes a level shift unit 1, which includes a diode 1a and a normally-on type FET 1b, and has an anode connected to the input terminal 2 and a cathode connected to the drain of the FET 1b. Have been. The source and the gate of the FET 1b are commonly connected to a negative reference potential VSS, and the drain is connected to a logic unit 3 which is a DCFL (Direct Coupled FET Logic) circuit via a node N1.

The logic unit 3 includes a normally-on type FET 3a and a normally-on type FET 3b whose gate is connected to the node N1. FET3a has its source at ground potential GND and its drain at node
Each is connected to N2. The FET 3b has a source connected to the positive reference potential VDD, a drain and a gate connected to the node N2, and the node N2 is connected to the level shift unit 4.

The level shift unit 4 includes a diode 4a having an anode connected to the node N2, and a normally-off FET 4b,
The cathode of the diode 4a is connected to the drain of the FET 4b. The source and the gate of the FET 4b are commonly connected to a negative reference potential VSS, and the drain is connected to the buffer unit 5.

The buffer unit 5 includes a normally-on type FET 5a in which the drain of the FET 4b is connected to the gate, and a normally-on type FET 5b.
The drain of the FET 5a is connected to the positive reference potential VDD, and the source is connected to the drain of the FET 5b via the node N3. And the source of FET5b is ground potential GND.
The gate is connected to the node N1 and the node N3 is connected to the output terminal 6.

 Next, the operation will be described.

If the input potential VI of the input terminal 2 is at “L” level, FET5
b is turned off. On the other hand, the output node N2 of the logic unit 3
Becomes “H” level and the FET5a is turned on.
An “H” level output potential OUT is output to the output terminal 6. If the input potential VI is at the “H” level, the FET 5b is in the ON state and the node N2 is at the “L” level, so that the output terminal OUT outputs the “L” level output potential OUT.

“L” level of node N2 is almost equal to ground potential GND
0.2V. However, the FET 5a does not turn off completely unless the gate voltage is lower than the threshold voltage Vtd (= −0.5 V) of the normally-on type FET. Therefore, the level shift unit 4 reduces the "L" level of the node N2, that is, 0.2 V, to a negative potential VSS of -0.5 V or less and applies the same to the gate of the FET 5a. The FET 5a is surely turned off, and the FET 5a and the FET 5b are turned on / off complementarily. This prevents a through current from flowing between the positive reference potential VDD and the ground potential GND in the buffer unit 5, thereby reducing power consumption.

However, the FET semiconductor integrated circuit shown in FIG. 2 has a drawback that the self-delay between the input / output terminals 2 and 6 becomes large because of the large number of circuit components.

Therefore, the above-mentioned document proposes an FET semiconductor integrated circuit as shown in FIG.

FIG. 3 is a circuit diagram showing another conventional FET semiconductor integrated circuit.

This FET semiconductor integrated circuit has a circuit configuration in which the normally-on type FET 5a in FIG. 2 is replaced with a normally-off type FET 5A, the level shift unit 4 in FIG. 2 is deleted, and the node N2 and the gate of the normally-off type FET 5A are directly connected. ing.

With such a circuit configuration, normally-off type FE
Since the threshold voltage of T5A is about 0.2V,
An FET semiconductor integrated circuit that can perform on / off operations complementary to the FET 5b and has a small self-delay is obtained.

(Problems to be solved by the invention) However, in the FET semiconductor integrated circuit having the above configuration,
There were the following issues.

The normally-off type FET 5A has a shallower channel than the normally-on type FET 5a.
The on-resistance becomes larger than that of the normally-on type FET 5a. For this reason, the FET semiconductor integrated circuit proposed in the above document has a problem that the driving capability is reduced.

To solve this problem, there is a solution as shown in the above-mentioned document. That is, a diode opposite to the diode 4a is connected in parallel to both ends of the diode 4a of the level shift unit 4 in FIG. 2 to function as a speed-up capacitor. However, if the capacitance of the speed-up capacitor is increased in order to increase the effect of the speed-up capacitor, problems such as an increase in the delay of the logic unit 3 in the preceding stage occur.

Therefore, it has been difficult to realize an FET semiconductor integrated circuit having a small self-delay, low power consumption, and high driving capability, in any of the above-described FET semiconductor integrated circuits.

An object of the present invention is to provide an FET semiconductor integrated circuit which solves the problems of the prior art, such as large self-delay, high power consumption, and reduced driving capability.

(Means for Solving the Problems) In the first invention, in order to solve the problems, a level shift unit that shifts one or a plurality of input potentials to a predetermined level, and a logic of an output of the level shift unit A logic unit which takes the logical result from the output side node and
Are connected in series between the positive reference potential and the ground potential of the first and second normally-on type FETs, which are turned on / off complementarily based on the output side node and the output of the level shift unit. And a buffer unit having the following features.

The logic unit is connected between the output node and a negative reference potential, and is turned on / off by an output of the level shift unit.
A normally-off type FET that is turned off, and a third normally-on type FET for a load connected between the second positive reference potential lower than the first positive reference potential and the output side node
It is composed of

According to a second aspect, in the FET semiconductor integrated circuit according to the first aspect, the second positive reference potential is equal to the ground potential.

(Operation) According to the first invention, since the FET semiconductor integrated circuit is configured as described above, the normally-off type FET of the logic unit performs on / off operation by the output of the level shift unit, and outputs the output when it is on. It works to set the side node to a potential substantially equal to the negative reference potential. In addition, the normally-on type FET of the logic section
A constant current is always supplied to the output side node by the second positive reference potential lower than the first positive reference potential. When the normally-off type FET is off, the output side node is connected to the second positive reference potential. It works to make it the same potential. Thus, the logical unit and the buffer unit work so as to be directly connected.

According to the second aspect, the second positive reference potential equal to the ground potential acts to reduce the number of reference power supplies. Therefore, the above problem can be solved.

First Embodiment FIG. 1 is a circuit diagram of an FET semiconductor integrated circuit showing a first embodiment of the present invention, which is a circuit having a function as an inverter.

This FET semiconductor integrated circuit has a level shift unit 10 for lowering an input potential VI, and the level shift unit 10 includes a diode 10a and a normally-on type FET 10b. The anode of the diode 10a is connected to the input terminal 20, and the cathode is connected to the drain of the FET 10b.
The source and the gate of the FET 10b are commonly connected to a negative reference potential VSS. Further, the drain of the FET 10b is connected to the logic unit 30 which is a DCFL circuit via the node N10.

The logic unit 30 is a circuit that takes the logic of the node N10, inverts the logic, and outputs the inverted logic from the output node N20,
Normally-off FET30 with gate connected to node N10
a, and a normally-on type FET 30b. FET30a
Has a source connected to the negative reference potential VSS and a drain connected to the node N20. Further, the drain of the FET 30b is connected to the positive reference potential VBB, the source and the gate are connected to the node N20, and the node N20 is connected to the buffer unit 40.

The buffer unit 40 is a circuit that takes in the potential of the node N20, drives the potential, and outputs the potential to the output terminal 50. . The drain of the FET 40a is at the positive reference potential VDD, the gate is at the node N20,
The sources are respectively connected to the drains of the FETs 40b via the nodes N30. The FET 40a has, for example, a gate voltage of −
It has a characteristic that it is turned off at 0.5 V or less, turned on when the gate voltage becomes larger than -0.5 V, and the current value between the source and the drain increases as the gate voltage increases. FET4
The source of 0b is connected to the ground potential GND, the gate is connected to the node N10, and the node N30 is connected to the output terminal 50 for the output potential OUT.
It is connected to the.

Here, the following relationship holds between the positive reference potentials VDD and VBB, the negative reference potential VSS, and the ground potential GND.

VSS <GND, VBB <VDD GND = VBB = 0V VSS = −VF where VF; turn-on voltage of diode 10a (0.7V) Next, when input potential VI is “L” level and “H” level (A) and (B) will be described.

(A) When VI is at “L” level (= 0 V) Since VSS = −VF, VI−VSS = VF, and the diode 10a is off. Therefore, the potential V10 of the node N10 becomes V10 = VSS (= -0.7 V), and both the FETs 30a and 40b are turned off. As a result,
Since the output potential of logic unit 30 attains an "H" level, node N2
The potential V20 of 0 is as follows: V20 = VBB (= 0V). Further, V20> VTD, where VTD; the threshold voltage of the FET 40a (≦ −0.5 V), so that the FET 40a is turned on, and the output potential OUT becomes “H” level (= VDD).

(B) When VI is at “H” level (= VDD) The potential V10 of the diode 10a is turned on. The gate voltage of the FET 30a is V10−VSS> VTE where VTE is the threshold voltage of the FET 30a, and the gate voltage V10 of the FET 40b is V10−0> VTE, so that both the FETs 30a and 40b are turned on. Since the FET 30a is turned on, the potential V20 of the node N20 is V20 = VSS + VDS = −0.6V, where VDS; the voltage between drain and source of the FET 30b (0.1
V), which is the “L” level.

Here, assuming that the output potential OUT is at the “L” level potential VOL ≒ 0 V, the gate voltage of the FET 40a is V20−VOL = −0.6V (<VTD), so that the FET 40a is completely turned off. V20-VOL
Is higher than -0.5V, the FET 40a does not turn off completely, but as long as V20-VOL does not greatly exceed -0.5V, the FET 40a
Large current does not flow between the source and the drain.

On the other hand, since the FET 40b is turned on as described above, the output potential
OUT becomes “L” level (VOL). At this time, the output potential OUT
Even if the value of is low, the FET 40a does not turn on, and no unnecessary through current flows. Therefore, FET4
VOL = 0V holds without any voltage drop at 0b.

The above-mentioned value of V20 = -0.6V varies depending on the gain of the FETs 30a and 30b. However, this type of DCFL inverter circuit using a normally-on type FET and a normally-off type FET can be sufficiently realized. is there.

 The first embodiment has the following advantages.

(1) Since the FETs 40a and 40b of the buffer section 40 in the final stage perform on / off operations complementarily, the FE
Even if the gain of T40a, 40b is increased, low power consumption can be realized.

(2) Since the FETs 40a and 40b of the buffer unit 40 are normally-on FETs having a deep channel, a large driving capability can be obtained even with a small channel width.

(3) Since the channel width of the FETs 40a and 40b of the buffer unit 40 can be reduced, the operation speed of the logic unit 30 in the preceding stage is improved.

(4) Conventionally, the level shift unit 4 required between the logic unit 3 and the buffer unit 5 is no longer necessary.
Self delay can be reduced.

(5) Since the logic amplitude VHL of the output potential OUT becomes 0.7 V,
A DCFL circuit can be driven without difficulty, and it is particularly useful when used in a circuit in which the DCFL and a BFL (Buffered FET Logic) having a buffer section in an output stage are mixed.

Second Embodiment FIG. 4 is a circuit diagram of an FET semiconductor integrated circuit showing a second embodiment of the present invention, which is a circuit having a function as a two-input NOR circuit.

This FET semiconductor integrated circuit has a circuit configuration in which the level shift unit 10 in FIG. 1 is replaced with a level shift unit 10A, and the same elements as those in FIG. 1 are denoted by the same reference numerals.

The level shift unit 10A includes diodes 10A-1, 10A-2 and a normally-on type FET 10A-3. The anodes of the diodes 10A-1, 10A-2 are connected to the input terminals 20a, 20b.
, And the cathodes of the diodes 10A-1 and 10A-2 are connected to the drain of the FET 10A-3, respectively. The source and gate of the FET 10A-3 are commonly connected to a negative reference potential VSS, and the drain is connected to the node N10. Between the node N10 and the output terminal 50,
They are connected in the same way as in FIG.

 Next, the operation will be described.

If one of the input terminals 20a, 20b also goes to "H" level, the diode 10A-1, 10A-2, which has the anode at "H" level, turns on. As a result, the node N10 goes to “H” level, so that the output potential OUT goes to “L” level. If the input terminals 20a and 20b are both at the "L" level, the diodes 10A-1 and 10A-2 are both turned off, and the FE
The negative reference potential VSS is directly applied to the node N10 via T10A-3.
And the node N10 goes to the “L” level, so that the output potential OUT goes to the “H” level. As described above, the NOR function can be realized, and the same effect as in the first embodiment can be expected.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(I) In the first embodiment, VBB = GND, but GND <V
It is also possible to set BB <VDD.

(II) In the second embodiment, a two-input NOR circuit is used. However, a multi-input NOR circuit having two or more inputs can be used. In that case, it is necessary to provide diodes in the level shift unit 10A in correspondence with the number of inputs.

(III) In FIGS. 1 and 4, the reference potentials VDD, VSS
Each FET that reverses the polarity of the corresponding circuit
Can be reversed.

(Effects of the Invention) As described in detail above, according to the first invention, the normally-on type FET and the normally-off FET connected in series between the second positive reference potential and the negative reference potential in the logic unit. Type F
Since the ET is used to set the second positive reference potential lower than the first positive reference potential, the buffer section can be constituted by a normally-on type FET having a small on-resistance, and the logic section and the buffer section are directly connected. can do. As a result, it is possible to obtain an FET semiconductor integrated circuit with low power consumption, high driving capability, and small self-delay.

According to the second aspect, since the second positive reference potential is equal to the ground potential, the number of reference power supplies can be reduced accordingly, and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an FET semiconductor integrated circuit showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional FET semiconductor integrated circuit, and FIG. 3 is a circuit of another conventional FET semiconductor integrated circuit. Figure,
FIG. 4 is a circuit diagram of an FET semiconductor integrated circuit showing a second embodiment of the present invention. 10, 10A: Level shift unit, 20, 20a, 20b: Input terminal
30 ... Logic part, 40 ... Buffer part, 50 ... Output terminal, 10
a, 10A-1,10A-2 ... Diode, 10b, 10A-3,30b, 40
a, 40b… normally on type FET, 30a… normally off type F
ET, N10, N30 …… Node, N20 …… Output node, VI ……
Input potential, OUT: Output potential, VDD: First positive reference potential, VBB: Second positive reference potential, GND: Ground potential, VS
S ... Negative reference potential.

Claims (2)

(57) [Claims] A level shifter for shifting one or more input potentials to a predetermined level; a logic unit for taking a logic of an output of the level shifter and outputting a logic result from an output node; Connected in series between the positive reference potential of
First and second complementary ON / OFF operations based on the output side node and the output of the level shift unit, respectively.
And a buffer section having a normally-on type FET of
In the ET semiconductor integrated circuit, the logic unit is connected between the output node and a negative reference potential, and operates normally on / off by an output of the level shift unit. An FET semiconductor integrated circuit, comprising: a third normally-on FET for load connected between a second positive reference potential lower than a reference potential and the output node. 2. The FET semiconductor integrated circuit according to claim 1, wherein said second positive reference potential is equal to said ground potential.
T semiconductor integrated circuit.