JPS6356016A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS6356016A JPS6356016A JP61200884A JP20088486A JPS6356016A JP S6356016 A JPS6356016 A JP S6356016A JP 61200884 A JP61200884 A JP 61200884A JP 20088486 A JP20088486 A JP 20088486A JP S6356016 A JPS6356016 A JP S6356016A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuit element
- logic
- control circuit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007704 transition Effects 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims description 47
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910044991 metal oxide Inorganic materials 0.000 claims 3
- 150000004706 metal oxides Chemical class 0.000 claims 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 description 25
- 230000007423 decrease Effects 0.000 description 11
- 230000000295 complement effect Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052700 potassium Inorganic materials 0.000 description 2
- 239000011591 potassium Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、主としてコンピュータの論理口？３の高速化
と消ｒ！Ｌ電力の低減化等の改良に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is mainly applied to computer logic ports. 3 speeding up and erasing! This article relates to improvements such as reduction of L power.
［従来の技術］
コンピュータの論理回路において、高速化と低い消費電
力を実現することは相反することであり、両者を同時に
満たすことは極めて困難である。消費電力を減少するた
めに、論理回路用の素材としてシリコンを用いる場合に
は、Ｐチャネル トランジスタとＮチャネル トランジ
スタを用いて、相補型（コンプリメンタリ）論理回路を
構成する。[Prior Art] In a computer logic circuit, achieving high speed and low power consumption are contradictory, and it is extremely difficult to satisfy both at the same time. In order to reduce power consumption, when silicon is used as a material for a logic circuit, a complementary logic circuit is constructed using a P-channel transistor and an N-channel transistor.
更に高速化と低消費電力化を実現するに：ｉ、カリウム
・ひ素等の化合物半導体を用いる必要がある。In order to achieve even higher speeds and lower power consumption, it is necessary to use compound semiconductors such as potassium and arsenic.
しかし、カリウム・ひ素を用いた論理回路がシリコンを
用いた論理回路の開発はとに順調に進行していない。そ
の理由を以下に示す。However, the development of logic circuits using potassium and arsenic and logic circuits using silicon has not proceeded smoothly. The reason is shown below.
（＋）イオン インプランテーションによるスレッシヨ
ード電圧の許容幅の標準偏差が非常に小さいので、集積
回路を製作する際の歩留まりが悪い。(+) The standard deviation of threshold voltage tolerance by ion implantation is very small, resulting in poor yields when manufacturing integrated circuits.
（２）ガリウム・ひ素を用いた論理回路は１言頼性の高
い動作を行うために、自己整合（セルフアライメント）
技術等を用いる。しかし、化合物半導体中の正孔の移動
速度が遅いので、Ｐチャネルの電界効果トランジスタを
用いると、論理の遷移動作速度が遅くなる。従って、相
補型（コンプリメンタリ〉論理回路を構成して高速化と
低消費電力化を実現することは困難である。(2) Logic circuits using gallium arsenide require self-alignment in order to operate with high reliability.
Use technology etc. However, since the movement speed of holes in a compound semiconductor is slow, when a P-channel field effect transistor is used, the logic transition operation speed becomes slow. Therefore, it is difficult to realize high speed and low power consumption by configuring a complementary logic circuit.
（３）カリウ１１・ひ素を用いた論理口′！δの論理振
幅が１ボルト付近であり、雑音の影響を受けやすいので
、（占１イ１件の高い高密度集積回路を実現することは
困難である。(3) Logic mouth using Kaliu 11 and arsenic! Since the logic amplitude of δ is around 1 volt and it is susceptible to noise, it is difficult to realize a high-density integrated circuit.
以上の欠点を除去するために、従来の論理回路を改良し
、論理振幅が大きく、高速動作を１テい、しかも消費電
力の少ない回路を開発する必要がある。In order to eliminate the above-mentioned drawbacks, it is necessary to improve conventional logic circuits and develop a circuit that has large logic amplitude, high-speed operation, and low power consumption.
［本発明の１的］
本発明の目的はコンピュータ等の論理回路において、入
力電圧を電圧シフト回路を用いてシフトした電圧に対応
して制御回路用により負荷回路用に流れる電流を制御し
、電源から接地点に直通して流れる無用な電流を除去す
ることにより、論理振幅の増加、論理遷移動作の高速化
、および低消費電力化を実現することである。[One Object of the Invention] An object of the present invention is to control the current flowing through the control circuit and the load circuit in response to the voltage shifted from the input voltage using a voltage shift circuit in a logic circuit such as a computer, thereby controlling the current flowing through the control circuit and the load circuit. By eliminating unnecessary current flowing directly from the ground to the ground, it is possible to increase logic amplitude, speed up logic transition operations, and reduce power consumption.
［従来の問題点を解決する為の手段］
論理回路の基本は反転（インバータ）回路°Ｃある。電
界効果トランジスタを用いる論理回路の基本はＤＣＦＬ
（直結形電界効果トランジスタ論理回路）である。直
結形電界効果トランジスタ論理回路では駆動回路用に直
列に負荷回路用を接続する。人力は駆動回路用に加えら
れ。駆動回路用と負荷回路用との接続点が出力である。[Means for solving conventional problems] The basic logic circuit is an inverter circuit. The basis of logic circuits using field effect transistors is DCFL.
(direct-coupled field-effect transistor logic circuit). In a direct-coupled field effect transistor logic circuit, a drive circuit is connected in series with a load circuit. Human power is added for the drive circuit. The connection point between the drive circuit and load circuit is the output.
従来の直結形電界効果トランジスタ論理回路の負荷回路
用は常に導通状態にあるので、駆動回路用が人力に応じ
て導通状態になると、Ｔｔ、源から接地点まで直通して
電流力＜ ２．ｉれることが欠点てあった。この直通電
流は論理状態の遷移動作を妨害し、しかも消費電力を増
加し、論理振幅も低減化する。この直通電流を遮断する
ために、負荷回路用と駆動回路用にＰチャネルとＮチャ
ネルの相補型電界効果トランジスタを用いる場合もある
。Since the load circuit of a conventional direct-coupled field effect transistor logic circuit is always in a conductive state, when the drive circuit becomes conductive in response to human power, Tt, the current flows directly from the source to the ground point and the current force < 2. There were some drawbacks. This direct current disturbs logic state transition operations, increases power consumption, and reduces logic amplitude. In order to cut off this direct current, P-channel and N-channel complementary field effect transistors may be used for the load circuit and the drive circuit.
しかし、Ｐチャネル電界効果トランジスタのキャリアで
ある正孔の移動速度がＮチャネルのそれに比較して遅い
ので、高速化を実現することは困難であり、集積回路の
製作の工程も複雑になる。本発明の論理回路は電子の移
動速度の速いＮチャネルの電界効果トランジスタを用い
ても、論理回路の高速化と消費電力の低減化および論理
１辰幅の増加を実現することができる。このためには、
駆動回路用が導通状態にある１ｌＪＩ間に、負荷回路用
に流れる電流を遮断することが必要である。制御回路用
により制御回路用の負荷回路用の両、）；ｔ４に電位差
を発生すれば、負荷回路用に流れる電流は遮断される。However, since the moving speed of holes, which are carriers, in a P-channel field effect transistor is slower than that in an N-channel field effect transistor, it is difficult to achieve higher speeds, and the process of manufacturing an integrated circuit becomes complicated. Even if the logic circuit of the present invention uses an N-channel field effect transistor in which electrons move at a high speed, it is possible to increase the speed of the logic circuit, reduce power consumption, and increase the logic width. For this purpose,
It is necessary to cut off the current flowing to the load circuit during 1lJI when the drive circuit is in a conductive state. If a potential difference is generated between the control circuit and the load circuit at t4, the current flowing to the load circuit is cut off.
駆動回路用が導通状態になる期間において、駆動回路用
の負荷回路用に流れる電流が遮断されると、電源から接
地点へ直通して流れる電流が極めて少なくなり、遷移動
作が高速化され、消費電力が少なくなり、論理振幅が増
加し、論理回路の特性が向上する。If the current flowing to the load circuit for the drive circuit is cut off during the period when the drive circuit is in a conductive state, the current flowing directly from the power supply to the ground point becomes extremely small, speeding up the transition operation and reducing the consumption. Less power, increased logic amplitude, and improved logic circuit performance.
［作用］
本発明の論理回路においては、駆動回路用の負荷回路用
に流れる電流を入力電圧を電圧シフトカイロを用いてシ
フトした電圧によって制御するので、制御回路用は入力
電圧に対応して導通状態と非導通状態になる。制御回路
用が導通状態になると、制御回路用の負荷回路用にも電
流が流れて制御回路用の負荷回路用に電圧降下が起る。[Function] In the logic circuit of the present invention, the current flowing in the load circuit for the drive circuit is controlled by the voltage shifted from the input voltage using the voltage shift warmer, so that the control circuit becomes conductive in accordance with the input voltage. state and becomes non-conductive. When the control circuit becomes conductive, current also flows to the control circuit load circuit, causing a voltage drop in the control circuit load circuit.
この電圧降下により、駆動回路用の負荷回路用に流れる
電流を制御する電圧は電流を減少させる方向に働く。従
って、駆動回路用の負荷回路用に流れる電流が減少して
、電源から接地点まて流れる直通電流が殆と、無くなる
ところで、論理回路の出力には、次段の駆動回路用の人
力の静電容量と次段への配線の静電容量等で構成される
寄生的な静電容量が負荷側にあり、これらを総合して寄
生的静電容はとする。寄生的静電容量に電荷を充電する
速度および寄生的静電容量に蓄え１られた放電する速度
により、論理回路の遷ｆ多動作の速度が決定される。電
源から接地点まで直通して流れろ電流が減少すると、駆
動回路用に流れる電流は負荷側の寄生的静電容量に蓄え
られた電荷を放電するために使われるので、論理状態の
ｊ二移動作が高速になる。Due to this voltage drop, the voltage that controls the current flowing through the load circuit for the drive circuit acts in the direction of decreasing the current. Therefore, when the current flowing through the load circuit for the drive circuit decreases and almost no direct current flows from the power supply to the ground point, the output of the logic circuit is There is parasitic capacitance on the load side, which is composed of the capacitance and the capacitance of the wiring to the next stage, and the parasitic capacitance is taken as a total of these. The speed at which the parasitic capacitance is charged and the speed at which the parasitic capacitance is discharged determines the speed at which the logic circuit operates. When the current flowing directly from the power source to ground decreases, the current flowing for the drive circuit is used to discharge the charge stored in the parasitic capacitance on the load side, so that the logic state j2 movement operation is reduced. becomes faster.
そのうえ、゛電源から接地点まて流れる直通電流が減少
すると、消費電力も減少する。とくに、駆動回路１；子
の導通状態が持続する期間においては、駆動回路用の１
ｉ＋、 ｉ苛回路に子から流入する電流が殆と無いので
、消ｔ′１電力は大幅に低減化される。また、電源から
接地点まで流れる直通電流が減少すると、駆ｆｆ５１１
回路用に流れろ電流は負１ｉ１ｉｒ９１１の寄生的静電
容量に蓄えられた電荷を放電するためにのみ利用される
ので、寄生的静電容量の電荷の殆ど全てが放電されるの
で、論理状態の低いレベルがさらに低下して論理振幅が
増加する。以上の結果、低消費電力と高速化が実Ｔｊｌ
され、しかも論理振幅が増加することにより信頼性の高
い集積回路を製作することが可能になる。Moreover, if the direct current flowing from the power supply to the ground point is reduced, power consumption will also be reduced. In particular, during the period when the conductive state of the drive circuit 1;
Since there is almost no current flowing into the i+, i source circuit from the child, the dissipated t'1 power is significantly reduced. Also, when the direct current flowing from the power supply to the ground point decreases, the drive ff511
Since the current flowing for the circuit is only used to discharge the charge stored in the parasitic capacitance of the negative 1i1ir911, almost all of the parasitic capacitance charge is discharged, so that the low logic state The level decreases further and the logic amplitude increases. As a result of the above, low power consumption and high speed are realized.
Moreover, the increase in logic amplitude makes it possible to fabricate highly reliable integrated circuits.
［好ましい実施例］
本発明は駆動回路用の負荷回路用の電流を制御する機能
を備えた論理回路であり、低消費電力化と高速化を実現
することができる。論理回路の基本は反転（インバータ
）回路であり、反転回路で低消費電力化と高速化が実現
されると、ＮＡＮＤ論理回路、ＮＯＲ論理回路、ＮＯＴ
論理回路、ＸＯＲ論理回路および記憶回路等のコンピュ
ータの論理回路に適用することができるので、以下では
、本発明を反転回路に適用した実施例に関して図面に基
づいて説明する。[Preferred Embodiment] The present invention is a logic circuit having a function of controlling current for a load circuit for a drive circuit, and can realize low power consumption and high speed. The basics of logic circuits are inversion (inverter) circuits, and when inversion circuits achieve lower power consumption and higher speed, they become NAND logic circuits, NOR logic circuits, and NOT logic circuits.
Since the present invention can be applied to computer logic circuits such as logic circuits, XOR logic circuits, and memory circuits, an embodiment in which the present invention is applied to an inversion circuit will be described below with reference to the drawings.
本発明を反転回路に適用した実施例を第１図に示す。第
１図のＡ点には電源が加えられており、この実施例では
Ａ点の電位は正であるとするが、負の場合も符号のみの
差異であり、本質的な動作は同しであるので、本発明は
負電源の場合も含む。An embodiment in which the present invention is applied to an inverting circuit is shown in FIG. Power is applied to point A in Figure 1, and in this example it is assumed that the potential at point A is positive, but even if it is negative, the difference is only in sign, and the essential operation is the same. Therefore, the present invention also includes the case of a negative power supply.
第１図のＢ点にも電源が加えられており、この実施例で
はＢ点の電位は負であるとするが、正の場合も符号のみ
の差異であり本質的な動作は同じであるので、本発明は
正電源の場合も含む。第１図の寄生的静電容量６は基板
と配線等の寄生的静電容量であり、特別に接続する必要
はない。第１図の入力（ＩＮＰＵＴ）の電圧に対応して
駆動回路用ｌに流れる電流が増減する。駆動回路用ｌに
流れる電流は駆動回路用の負荷回路用２を通って電源か
ら接地点に流れる。駆動回路用１と駆動回路用の負荷回
路用２の接続点から出力（ＯＵ Ｔ Ｐ Ｕ Ｔ ）電
圧が外部回路に供給される。出力側の寄生的静電容量６
を充電したり、放電する電荷の動きが論理状態の遷移動
作の速度を決定する。すなわち、駆動回路用ｌが非導通
状態ならば、駆動回路用の負荷回路用から寄生的静電容
量６に電流が供給されて、寄生的静電容量６に電荷が蓄
積され、出力の電位が上昇する。駆動回路用１が導通状
態になれば、寄生的静電容量６に蓄積された電荷が放電
されて出力の電位は下降する。従来の論理回路において
は、駆動回路用１の導通状態あるいは非導通状態にかか
わらず、駆動回路用の負荷回″Ｊ？ｉ素子２は常に導通
状態である。Power is also applied to point B in Figure 1, and in this example, the potential at point B is negative, but even if it is positive, the difference is only in sign and the essential operation is the same. , the present invention also includes the case of a positive power source. The parasitic capacitance 6 in FIG. 1 is the parasitic capacitance of the substrate, wiring, etc., and does not need to be specially connected. The current flowing through the drive circuit 1 increases or decreases in accordance with the voltage of the input (INPUT) shown in FIG. The current flowing through the drive circuit 1 flows from the power supply to the ground point through the drive circuit load circuit 2. An output (OUTPUT) voltage is supplied to an external circuit from a connection point between the drive circuit 1 and the load circuit 2 for the drive circuit. Parasitic capacitance on the output side6
The movement of charge to charge or discharge determines the speed of logic state transition operations. That is, if the drive circuit l is in a non-conducting state, current is supplied from the load circuit for the drive circuit to the parasitic capacitance 6, charge is accumulated in the parasitic capacitance 6, and the output potential changes. Rise. When the drive circuit 1 becomes conductive, the charges accumulated in the parasitic capacitance 6 are discharged, and the output potential drops. In the conventional logic circuit, the load circuit "J?i" element 2 for the drive circuit is always in a conductive state, regardless of whether the drive circuit 1 is conductive or non-conductive.
駆動回路用ｌが非導通状態である場合には、駆動回路用
の負荷回路用２に流れる電流は寄生的静電容量６に電荷
を蓄えることのみに利用されるが、駆動回路用ｌが導通
状態である場合には、駆動回路用の負荷回路用２に流れ
ろ電流は接地点まで直通するので、寄生的静電容量６に
蓄えられた電荷の放出を妨害する。この直通ｉｉ流は遷
移動作の高速化の妨げになり、無駄な電力を消費し、論
理）肩幅も減少させて、出力側の負荷駆動能力を低下す
る等の欠点をもたらし、何等の利点をもたらさない。従
って、駆動回路用１が導通状態である場合には、駆動回
路用の負荷回路用２に流れるＴＲ，ＴＲを遮断すると、
これらの欠点の全ては除去される。この為には、電圧シ
フト回路５と制御回路用３と制御回路用の負荷回路用４
を用いて、駆動回路用の負荷回路用２に流れる電流を制
御する。When the drive circuit l is in a non-conducting state, the current flowing through the load circuit 2 for the drive circuit is used only to store charge in the parasitic capacitance 6, but when the drive circuit l is in a non-conducting state, In this case, the current flowing through the load circuit 2 for the drive circuit passes directly to the ground point, thereby preventing the charge stored in the parasitic capacitance 6 from being discharged. This direct current impedes the speeding up of transition operations, consumes unnecessary power, reduces the logic shoulder width, and reduces the load driving ability on the output side. do not have. Therefore, when the drive circuit 1 is in a conductive state, if TR and TR flowing to the drive circuit load circuit 2 are cut off,
All of these drawbacks are eliminated. For this purpose, a voltage shift circuit 5, a control circuit 3, and a load circuit 4 for the control circuit are required.
is used to control the current flowing through the load circuit 2 for the drive circuit.
電圧シフト回路５を用いて入力電圧を直流的にシフトし
た電圧に依存して制御量′Ｊ３素子３は導通状態または
非導通状態になる。制御回路用３に流れる電流は制御回
路用の負荷回路用４から供給される。駆動回路用の負荷
回路用２に流れる電流は制御回路用の負荷回路用１１０
両端の電位差によって制御される。すなわち、制御回路
用の負荷回路用４の両端の電位差が大きくなれば、駆動
回路用の負荷回路用２に流れろ電流は減少する。逆に、
制御回路用の負荷回路用４の両端の電位差が小さくなれ
ば、駆動回路用の負荷回路用２に流れる電流は増加する
。駆動回路用１は入力電圧に対応し・て導通状態または
非導通状態になるが、制御回路用３は入力電圧を電圧シ
フト回路によりシフトした電圧に対応して導通状態また
は非導通状態になる。従って、駆動回路用１が導通する
場合には、制御回路用３も導通状態になり、制御回路用
３に電流が流れるので、制御回路用の負荷回路用４の両
端に電位差が発生し、駆動回路用の負荷回路用２に流れ
る電流が減少する。すなわち、駆動回路用１が導通状態
の期間において、電源から駆動回路用の負荷回路用２を
通過して供給される電流は遮断される。駆動回路用ｌが
非導通状部である期間では、制御回路用３も非導通状態
になり、制御回路用の負荷回路用４の両端の電位差が小
さくなり、駆動回路用の負荷回路用２における電流の減
少作用が発生しないので、制御回路用３と制御回路用の
負荷回路用４が存在しない反転論理回路と同じ動作を行
う。すなわち、駆動回路用１が非導通状態にあるので、
電源から駆動回路用の負荷回路用２を通過して供給され
ろ電流は寄生的静電容量６の電荷を蓄積することのみに
利用される。従って、電源から接地点に流れる直通電流
が無くなるので、無駄な電力の消費が抑えられる。この
結果、駆動回路用１が導通状態における消豐電力の低減
化と遷移動作の高速化が実現される。しかも、駆動回路
用１の電流容量を減少させることができる。なぜならば
、駆動回路用１の電流容量はそれが導通の場合に流れる
電流に基づいて決められる。従来の反転論理回路におい
ては、駆動回路用ｌに流れる電流は駆動回路用の負荷回
路用２から流れ込む電流と寄生的静電容量６に蓄えられ
た電荷の放電により流れ込む電流の和である。本発明の
論理回路においては、
む電流の和である。本発明の論理回路においては、駆動
回路用１が導通すると、駆動回路用の負荷回路用２は非
導通状態になり、電源から接地点へ直通して流れる？ｌ
ｉ流が遮断され、駆動回路用１に流れる電流は寄生的静
電容＠６に蓄積された電荷のみを放電することに使われ
て遷移動作が発生するので、電流容量の少ないトランジ
スタを使用しても寄生的静電容＠６の電荷を高速に放電
することが可能になる。駆動回路用１の電流が減少すれ
ば、人力の静電容量も小さくすることができるので、論
理回路全体の寄生的静電容量の値が減少し、しかも集積
回路のパターンも縮小されるので、さらに高速化が実現
される。Depending on the voltage obtained by DC shifting the input voltage using the voltage shift circuit 5, the controlled variable 'J3 element 3 becomes conductive or non-conductive. The current flowing to the control circuit 3 is supplied from the load circuit 4 for the control circuit. The current flowing in the load circuit 2 for the drive circuit is the load circuit 110 for the control circuit.
Controlled by the potential difference between both ends. That is, as the potential difference between both ends of the load circuit 4 for the control circuit increases, the current flowing through the load circuit 2 for the drive circuit decreases. vice versa,
If the potential difference between both ends of the load circuit 4 for the control circuit becomes smaller, the current flowing through the load circuit 2 for the drive circuit increases. The drive circuit 1 becomes conductive or non-conductive depending on the input voltage, while the control circuit 3 becomes conductive or non-conductive depending on the voltage shifted from the input voltage by the voltage shift circuit. Therefore, when the drive circuit 1 becomes conductive, the control circuit 3 also becomes conductive, and current flows through the control circuit 3, so a potential difference is generated across the load circuit 4 for the control circuit, and the drive circuit 3 becomes conductive. The current flowing through the circuit load circuit 2 decreases. That is, during the period in which the drive circuit 1 is in a conductive state, the current supplied from the power supply through the drive circuit load circuit 2 is cut off. During the period in which the drive circuit 1 is in a non-conducting state, the control circuit 3 is also in a non-conducting state, and the potential difference between both ends of the control circuit load circuit 4 becomes small, causing the drive circuit load circuit 2 to become non-conductive. Since no current reduction effect occurs, the operation is the same as that of an inverting logic circuit in which the control circuit 3 and the load circuit 4 for the control circuit do not exist. That is, since the drive circuit 1 is in a non-conductive state,
The current supplied from the power supply through the load circuit 2 for the drive circuit is used only to store the charge of the parasitic capacitance 6. Therefore, since there is no direct current flowing from the power source to the ground point, wasteful power consumption can be suppressed. As a result, it is possible to reduce the power consumption and increase the speed of the transition operation when the drive circuit 1 is in the conductive state. Moreover, the current capacity of the drive circuit 1 can be reduced. This is because the current capacity of the drive circuit 1 is determined based on the current that flows when it is conductive. In the conventional inverting logic circuit, the current flowing into the drive circuit 1 is the sum of the current flowing from the load circuit 2 for the drive circuit and the current flowing due to discharge of the charge stored in the parasitic capacitance 6. In the logic circuit of the present invention, it is the sum of the currents flowing. In the logic circuit of the present invention, when the drive circuit 1 becomes conductive, the load circuit 2 for the drive circuit becomes non-conductive, and the current flows directly from the power source to the ground point. l
The i current is cut off and the current flowing through the drive circuit 1 is used to discharge only the charge accumulated in the parasitic capacitance @6, causing a transition operation, so a transistor with low current capacity is used. It also becomes possible to quickly discharge the parasitic capacitance @6. If the current of the driving circuit 1 is reduced, the capacitance of human power can be reduced, so the parasitic capacitance value of the entire logic circuit is reduced, and the pattern of the integrated circuit is also reduced. Further speeding up is achieved.
本発明の負荷回路用の電流制御方式をＮＯＲ論理回路に
適用した実施例を第２図に示す。第２図には２個の人力
（ＩＮＰＵＴＩとＩ ＮＰＵＴ２）があり、これらの入
力信号は駆動回路用１または駆動回路用７に入る。さら
に多くの人力がある場合でも、原理的には同じ動作を行
い、本発明の負荷回路用の電流制御方式を各人力に対し
・て制御回路用と制御回路用の負荷回路用を設定し、制
御することができる。FIG. 2 shows an embodiment in which the current control method for a load circuit of the present invention is applied to a NOR logic circuit. In FIG. 2, there are two inputs (INPUTI and INPUT2), and their input signals go into drive circuit 1 or drive circuit 7. Even if there is more human power, the same operation is performed in principle, and the current control method for the load circuit of the present invention is set for each human power for the control circuit and the load circuit for the control circuit, can be controlled.
駆動回路用１または駆動回路用７のいずれかあるいは両
方が導通状態になると、出力（ＯＵＴＰＵＴ）の電圧は
接地電位に接近する。ＩＮＰＵＴＩの論理状態により駆
動回路用１が導通状態あるいは非導通状態になることは
第１図の論理回路における動作と全く同じであり、本発
明の機能により高速化と低消ｒＪ電力化および論理振幅
の増加等が実現される。第１図と異なる点はＩＮＰＵＴ
２の論理状態の変化によっても出力の論理状態が変化す
ることである。駆動回路用７はＩＮＰＵＴ２の論理状態
に対応して、導通状態あるいは非導通状態が発生する。When either or both of drive circuit 1 and drive circuit 7 becomes conductive, the voltage of the output (OUTPUT) approaches the ground potential. The driving circuit 1 becomes conductive or non-conductive depending on the logic state of INPUTI, which is exactly the same as the operation in the logic circuit shown in FIG. This will result in an increase in The difference from Figure 1 is INPUT.
The logic state of the output also changes due to a change in the logic state of the output signal. The drive circuit 7 becomes conductive or non-conductive depending on the logic state of INPUT2.
Ｉ ＮＰＵＴ ｌに人力された電圧は電圧シフト回′＃
Ｊ５により直流的に電圧がシフトされて制御回路用３に
人力される。ＩＮＰＵＴ２に人力された電圧は電圧シフ
ト回路９により直流的に電圧がシフトされて制御回路用
８に人力される。駆動回路用７が導通状態になると、制
御回路用８も導通状態になるので、制御回路用の負荷回
路用４に電流が流れて、その両端に電位差が発生する。The voltage manually applied to I NPUT l is the voltage shift circuit '#
The voltage is shifted in a direct current manner by J5 and is manually inputted to the control circuit 3. The voltage input to the INPUT 2 is shifted in a DC manner by a voltage shift circuit 9 and then input to the control circuit 8. When the drive circuit 7 becomes conductive, the control circuit 8 also becomes conductive, so a current flows through the load circuit 4 for the control circuit, and a potential difference is generated across it.
この電位差により駆動回路用の負荷回路用２が非導通状
態になり、電源から接地点へ直通して流れる電流が遮断
されるので、従来のＮＯＲ論理回路よりも論理振幅が増
加し、消費電力は減少し、遷移動作は高速になる。Due to this potential difference, the load circuit 2 for the drive circuit becomes non-conductive, and the current flowing directly from the power supply to the ground point is cut off, so the logic amplitude increases compared to the conventional NOR logic circuit, and the power consumption decreases. and the transition operation becomes faster.
駆動回路用７が非導通状態にある場合には、遷移動作は
駆動回路用７と制御回路用８と電圧シフト回路９が存在
しない場合と同しである。すなわち、第１図と全く同じ
動作をする。第２図に示す本発明のＮＯＲ論理回路への
適用例は従来のＮＯＲ論理回路に駆動回路用７と制御回
路用８と電圧シフト回路９を接続するだけの簡単な変更
で実現される。本発明においては、負荷回路用２に流れ
る電流を制御するので、本発明のＮ。When the drive circuit 7 is in a non-conductive state, the transition operation is the same as when the drive circuit 7, the control circuit 8, and the voltage shift circuit 9 are not present. That is, the operation is exactly the same as in FIG. The example of application of the present invention to the NOR logic circuit shown in FIG. 2 can be realized by a simple change in which a drive circuit 7, a control circuit 8, and a voltage shift circuit 9 are connected to a conventional NOR logic circuit. In the present invention, since the current flowing through the load circuit 2 is controlled, N of the present invention.
Ｒ論理回路は従来の相補型ＮＯＲ論理回路よりも論理状
態の遷移動作が高速になる。なぜならば、従来の相補型
ＮＯＲ論理回路は複数個のＰチャネル トランジスタを
直列に接続するので、Ｐチャネル トランジスタのキャ
リアである正孔の移動速度が遅いうえに、それらの直列
接続はソースとトレイン間の電圧が低下するので、論理
状態の遷移動作の速度が低下する。The R logic circuit has a faster logic state transition operation than the conventional complementary NOR logic circuit. This is because conventional complementary NOR logic circuits connect multiple P-channel transistors in series, so the movement speed of holes, which are carriers of P-channel transistors, is slow, and their series connection is Since the voltage on the logic state decreases, the speed of the logic state transition operation decreases.
第３図は本発明に用いられる電圧シフト回路の一実施例
を示す。 電圧Ｅよりも電圧Ｆの電圧が充分に高い場合
には電圧シフト回路のダイオード１１が導通状態になり
、電圧シフト回路の抵抗１０にＭ、流が流れる。このと
き、電圧シフト回路のダイオード１１の両端のＦとＧの
間にはダイオードの順方向電圧である約帆６ボルトの電
圧降下が発生し、電圧Ｇは電圧Ｆよりも直流的に電圧が
シフトされる。この電圧シフト回路により、制御回路用
３と制御回路用８のトランジスタのスレッシヨード電圧
の設定が容易になることおよび制御回路用３と制御回路
用８のトランジスタのゲートの漏れ電流を少なくするこ
とができる。FIG. 3 shows an embodiment of the voltage shift circuit used in the present invention. When the voltage F is sufficiently higher than the voltage E, the diode 11 of the voltage shift circuit becomes conductive, and a current M flows through the resistor 10 of the voltage shift circuit. At this time, a voltage drop of approximately 6 volts, which is the forward voltage of the diode, occurs between F and G across the diode 11 of the voltage shift circuit, and the voltage G shifts more than the voltage F in a DC manner. be done. This voltage shift circuit makes it easy to set the threshold voltages of transistors 3 and 8 for control circuits, and reduces leakage current at the gates of transistors 3 and 8 for control circuits. .
［提案する論理回路の特徴］
本発明の論理回路はキャリアの移動速度が大きいＮチャ
ネル電界効果トランジスタのみを用いて構成することが
できるので、この場合には製造工程の単純さと高速化等
が実現される。本発明の特徴を以下に記述する。[Characteristics of the proposed logic circuit] The logic circuit of the present invention can be constructed using only N-channel field effect transistors with high carrier movement speed, so in this case, the manufacturing process can be simplified and increased in speed. be done. The features of the present invention will be described below.
（１）Ｎチャネル電界効果トランジスタのみを用いて論
理回路を構成することができるので、Ｐチャネル トラ
ンジスタと混在するように構成する論理回路よりも高速
動作をさせることができる。(1) Since a logic circuit can be configured using only N-channel field effect transistors, it can operate faster than a logic circuit configured to include a mixture of P-channel transistors.
（２）Ｎチャネル電界効果トランジスタのみを用いて論
理回路を構成することができるので、Ｐチャネル トラ
ンジスタも用いた相補型論理回路よりも製造工程は簡略
になる。(2) Since a logic circuit can be constructed using only N-channel field effect transistors, the manufacturing process is simpler than a complementary logic circuit that also uses P-channel transistors.
（３）Ｎチャネル電界効果トランジスタのみを用いて論
理回路を構成することができるので、相補型論理回路の
入力電圧と出力電圧にあるＰＮＰとＮＰＮの寄生的トラ
ンジスタのサイリスタ構造によるラッチアップ現象もな
く、安定した動作が可能になる。(3) Since the logic circuit can be configured using only N-channel field effect transistors, there is no latch-up phenomenon caused by the thyristor structure of PNP and NPN parasitic transistors in the input voltage and output voltage of the complementary logic circuit. , stable operation becomes possible.
（４）Ｎチャネル電界効果トランジスタのみを用いて論
理回路を構成することができるので、Ｐチャネル トラ
ンジスタとの分離頭載を設ける必要が無いので、構造が
簡単になる。(4) Since the logic circuit can be configured using only N-channel field effect transistors, there is no need to provide a separate overhead structure from P-channel transistors, which simplifies the structure.
（５）駆動回路用の負荷回路用の電流を制御回路用て制
御するので、ｆ、源から接地まで直通して流れろ電流が
極めて少ないので、消費電力は減少する。従って、本発
明の論理回路は発熱量も少なくなり、高密度集積回路に
適する。(5) Since the current for the load circuit for the drive circuit is controlled by the control circuit, the current flowing directly from the source to the ground is extremely small, so power consumption is reduced. Therefore, the logic circuit of the present invention generates less heat and is suitable for high-density integrated circuits.
（６）駆動回路用が導通状態の期間において、駆動回路
用の負荷回路用が非導通状態であるので、寄生的静電容
量の電荷を殆と完全に駆動回路用に流れる電流によって
放電することができるので、−理据輻は大きくなり、電
源電圧の利用度も向上し、雑音やトランジスタのバラツ
キの影響を受けにくい論理回路を製作することができ、
集積回路の信頼性が向上する。(6) During the period when the drive circuit is in a conductive state, the load circuit for the drive circuit is in a non-conductive state, so that the parasitic capacitance can be almost completely discharged by the current flowing to the drive circuit. As a result, it is possible to create logic circuits that are less susceptible to noise and transistor variations, increasing the amount of engineering space available, improving the utilization of power supply voltage, and
Improved reliability of integrated circuits.
（７）駆動回路用が導通状態になると、駆動回路用の負
荷回路用が非導通状態になり、電源から接地点へ直通に
流れろ電流が無いので、駆動回路用の電流容量が少ない
トランジスタを使用することができる。これは入力の静
電容量が減少し、配線パターンも縮小するごとができる
ので、最適設計を実施するとさらに高速化が実現される
。(7) When the drive circuit becomes conductive, the load circuit for the drive circuit becomes non-conductive, and no current flows directly from the power supply to the ground point, so a transistor with low current capacity is used for the drive circuit. can do. This reduces the input capacitance and allows the wiring pattern to be reduced in size, so implementing an optimal design will further increase speed.
（８）駆動回路用が導通状態になれば、駆動回路用の負
荷回路用が非導通状態になるので、駆動回路用の負荷回
路用から駆動回路用へ流れ込む電流が殆と無くなり、出
力側に接続された負荷からの電流だけが駆動回路用に流
れ込むので、
負荷駆動能力が大きくなる。(8) When the drive circuit becomes conductive, the drive circuit's load circuit becomes non-conductive, so almost no current flows from the drive circuit's load circuit to the drive circuit, and the output side Only current from the connected load flows into the drive circuit, increasing load drive capability.
（９）駆動回路用が導通状態の場合には、駆動回路用の
電流によって、寄生的静電容量の電荷が放電される。寄
生的静電容量の電荷の放電により、出力電圧が下降する
と、駆動回路用の負荷回路用は非導通状態から導通状態
に移行を始めて負荷電流の制御能力が低下するが、制御
回路用に負電源を接続することにより、駆動回路用の負
荷回路用の電流遮断能力を保持することができるので、
出力状態のいかなる変化に対しても電源から接地点へ直
通に流れる電流を阻止することが可能になる。(9) When the drive circuit is in a conductive state, the parasitic capacitance is discharged by the drive circuit current. When the output voltage drops due to the discharge of parasitic capacitance, the load circuit for the drive circuit begins to transition from a non-conducting state to a conductive state, reducing the ability to control the load current. By connecting the power supply, it is possible to maintain the current interrupting ability for the load circuit for the drive circuit.
It becomes possible to prevent current from flowing directly from the power supply to the ground point in response to any change in the output state.
（１０） 電源から接地点への直通電流を大幅に減少
させることができるので、消費電力が小さくなる。(10) Since the direct current flowing from the power source to the ground point can be significantly reduced, power consumption is reduced.
とくに、駆動回路用が導通状態の場合における静的消費
電力は非常に減少する。In particular, static power consumption when the drive circuit is in a conductive state is greatly reduced.
（１１） Ｐチャネル トランジスタとＮチャネル ト
ランジスタを用いた従来の相補型ＮＯＲ論理回路はＰチ
ャネル トランジスタを直列に接続するので、１個当た
りのゲートとソース間の電圧は半分に減少し、それらを
流れる電流も減少するので、高速動作が困難になる。し
かし、本発明の論理回路は負荷回路用の直列接続が無く
、制御回路のワイヤードＯｒ＜回路（配線によるＯＲ論
理回路）により負荷回路用の電流を制御することができ
るので、論理回路は簡単になり、しかも、高速動作をさ
せることが可能になる。(11) Conventional complementary NOR logic circuits using P-channel transistors and N-channel transistors connect the P-channel transistors in series, so the voltage between the gate and source of each is reduced by half, and the voltage flowing through them is reduced by half. Since the current also decreases, high-speed operation becomes difficult. However, the logic circuit of the present invention does not have a series connection for the load circuit, and the current for the load circuit can be controlled by the wired OR< circuit (OR logic circuit using wiring) of the control circuit, so the logic circuit can be easily constructed. Moreover, it becomes possible to operate at high speed.
第１図は本発明の一実施例であり、駆動回路用の負荷回
路用の？ｆ流を人力の論理状態に対応して制御する反転
（インバータ）回路である。第２図も本発明の一実施例
であり、駆動回路用の負荷回路用の電流を論理状態に対
応して制御するＮＯＲ論理回路である。第３図は本発明
に用いる電圧シフト回路の一実施例である。
ｌ・・駆動回路用、
２・・駆動回路用の負荷回路用、
３・・制御回路用、
４・・制御回路用の負荷回路用、
５・・電圧シフト回路、
６・・寄生的静電容量、
７・・駆動回路用、
８ ・・制御回路用、
９・・電圧シフト回路、
１０・・電圧シフト回路の抵抗、
１１・・電圧シフト回路のダイオード。FIG. 1 shows one embodiment of the present invention, and shows a load circuit for a drive circuit. This is an inverter circuit that controls the f flow according to the human logic state. FIG. 2 also shows an embodiment of the present invention, and is a NOR logic circuit that controls the current for the load circuit for the drive circuit in accordance with the logic state. FIG. 3 shows an embodiment of the voltage shift circuit used in the present invention. l...For the drive circuit, 2...For the load circuit for the drive circuit, 3...For the control circuit, 4...For the load circuit for the control circuit, 5...Voltage shift circuit, 6...Parasitic static electricity Capacitance, 7...For drive circuit, 8...For control circuit, 9...Voltage shift circuit, 10...Resistance of voltage shift circuit, 11...Diode of voltage shift circuit.
Claims (47)
加し、入力電圧の大きさに依存して駆動回路素子と制御
回路素子に導通状態と非導通状態を発生させ、駆動回路
素子が導通状態の期間において、制御回路素子も導通状
態になり、制御回路素子に流れる制御電流によって制御
回路用の負荷回路素子の両端に発生する電圧降下を利用
して、駆動回路用の負荷回路素子に流れる電流を減少す
ることにより、論理状態の遷移の高速化と論理振幅の増
加と導通・非導通のスイッチング動作の高速化と電圧変
化の増加および消費電力の低減化を実現することを特徴
とする駆動回路素子と駆動回路用の負荷回路素子と入力
電圧のシフト回路と制御回路素子と制御回路用の負荷回
路素子を有する論理回路。(1) Applying a voltage shift to the input voltage and applying it to the control circuit element, depending on the magnitude of the input voltage, generates a conductive state and a non-conductive state in the drive circuit element and the control circuit element, so that the drive circuit element becomes conductive. During this period, the control circuit element also becomes conductive, and the voltage drop generated across the control circuit load circuit element by the control current flowing through the control circuit element is used to cause the control current to flow to the drive circuit load circuit element. A drive characterized by realizing faster logic state transitions, increased logic amplitude, faster conduction/non-conduction switching operations, increased voltage changes, and reduced power consumption by reducing current. A logic circuit having a circuit element, a load circuit element for a drive circuit, an input voltage shift circuit, a control circuit element, and a load circuit element for the control circuit.
路用の負荷回路素子の接続点から制御回路用の負荷回路
素子を通過して流れる特許請求の範囲第１項記載の論理
回路。(2) The logic circuit according to claim 1, wherein the control current of the control circuit element flows from a connection point between the drive circuit element and the load circuit element for the drive circuit, passing through the load circuit element for the control circuit.
素子に供給する電源から制御回路用の負荷回路素子を通
過して流れる特許請求の範囲第１項記載の論理回路。(3) The logic circuit according to claim 1, in which the control current of the control circuit element flows from the power source supplied to the load circuit element for the drive circuit through the load circuit element for the control circuit.
して流れる制御電流が駆動回路用の負荷回路素子に供給
する電源と異なる電源に流れ込む特許請求の範囲第１項
記載の論理回路。(4) The logic circuit according to claim 1, wherein the control current flowing through the load circuit element for the control circuit and the control circuit element flows into a power source different from the power source supplied to the load circuit element for the drive circuit.
体電界効果トランジスタ）を用いて構成する特許請求の
範囲第１項記載の論理回路。(5) The logic circuit according to claim 1, which is constructed using a MOSFET (metal oxide semiconductor field effect transistor) as a drive circuit element.
界効果トランジスタ）を用いて構成する特許請求の範囲
第１項記載の論理回路。(6) The logic circuit according to claim 1, which is configured using MESFET (metal semiconductor field effect transistor) as a drive circuit element.
ｉｃ Ａｍｏｒｐｈｏｕｓ Ｓｉｌｉｃｏｎ ｇａｔｅ
電界効果トランジスタ）を用いて構成する特許請求の範
囲第１項記載の論理回路。(7) MASFET (Metal
ic Amorphous Silicon gate
2. The logic circuit according to claim 1, which is constructed using a field effect transistor.
金属酸化半導体電界効果トランジスタ）を用いて構成す
る特許請求の範囲第１項記載の論理回路。(8) MOSFET (
2. The logic circuit according to claim 1, which is constructed using a metal oxide semiconductor field effect transistor.
金属半導体電界効果トランジスタ）を用いて構成する特
許請求の範囲第１項記載の論理回路。(9) MESFET (
2. The logic circuit according to claim 1, which is constructed using a metal semiconductor field effect transistor.
（Ｍｅｔａｌｌｉｃ Ａｍｏｒｐｈｏｕｓ Ｓｉｌｉｃ
ｏｎ ｇａｔｅ電界効果トランジスタ）を用いて構成す
る特許請求の範囲第１項記載の論理回路。(10) MASFET as a load circuit element for the drive circuit
(Metallic Amorphous Silic
2. The logic circuit according to claim 1, wherein the logic circuit is configured using an on-gate field effect transistor.
導体電界効果トランジスタ）を用いて構成する特許請求
の範囲第１項記載の論理回路。(11) The logic circuit according to claim 1, which is constructed using a MOSFET (metal oxide semiconductor field effect transistor) as a control circuit element.
電界効果トランジスタ）を用いて構成する特許請求の範
囲第１項記載の論理回路。(12) The logic circuit according to claim 1, which is constructed using MESFET (metal semiconductor field effect transistor) as a control circuit element.
−ｌｉｃ Ａｍｏｒｐｈｏｕｓ Ｓｉｌｉｃｏｎ ｇａ
ｔｅ電界効果トランジスタ）を用いて構成する特許請求
の範囲第１項記載の論理回路。(13) MASFET (Metal
-lic Amorphous Silicon ga
2. The logic circuit according to claim 1, which is constructed using a TE field effect transistor.
果トランジスタを用いて構成する特許請求の範囲第１項
記載の論理回路。(14) The logic circuit according to claim 1, which is configured using an enhancement type field effect transistor as a drive circuit element.
果トランジスタを用いて構成する特許請求の範囲第１項
記載の論理回路。(15) The logic circuit according to claim 1, which is configured using a depletion field effect transistor as a drive circuit element.
ント型電界効果トランジスタを用いて構成する特許請求
の範囲第１項記載の論理回路。(16) The logic circuit according to claim 1, which is configured using an enhancement type field effect transistor as a load circuit element for a drive circuit.
ョン型電界効果トランジスタを用いて構成する特許請求
の範囲第１項記載の論理回路。(17) The logic circuit according to claim 1, which is configured using a depletion field effect transistor as a load circuit element for a drive circuit.
果トランジスタを用いて構成する特許請求の範囲第１項
記載の論理回路。(18) The logic circuit according to claim 1, which is constructed using an enhancement type field effect transistor as a control circuit element.
果トランジスタを用いて構成する特許請求の範囲第１項
記載の論理回路。(19) The logic circuit according to claim 1, which is constructed using a depletion field effect transistor as a control circuit element.
ント型電界効果トランジスタを用いて構成する特許請求
の範囲第１項記載の論理回路。(20) The logic circuit according to claim 1, which is configured using an enhancement type field effect transistor as a load circuit element for the control circuit.
ョン型電界効果トランジスタを用いて構成する特許請求
の範囲第１項記載の論理回路。(21) The logic circuit according to claim 1, which is constructed using a depletion field effect transistor as a load circuit element for the control circuit.
構成する特許請求の範囲第１項記載の論理回路。(22) The logic circuit according to claim 1, which is configured using a resistor as a load circuit element for the control circuit.
ンジスタを用いて構成する特許請求の範囲第１項記載の
論理回路。(23) The logic circuit according to claim 1, which is constructed using an N-channel field effect transistor as a drive circuit element.
電界効果トランジスタを用いて構成する特許請求の範囲
第１項記載の論理回路。(24) The logic circuit according to claim 1, which is configured using an N-channel field effect transistor as a load circuit element for the drive circuit.
ンジスタを用いて構成する特許請求の範囲第１項記載の
論理回路。(25) The logic circuit according to claim 1, which is constructed using an N-channel field effect transistor as a control circuit element.
電界効果トランジスタを用いて構成する特許請求の範囲
第１項記載の論理回路。(26) The logic circuit according to claim 1, which is configured using an N-channel field effect transistor as a load circuit element for the control circuit.
ンジスタを用いて構成する特許請求の範囲第１項記載の
論理回路。(27) The logic circuit according to claim 1, which is configured using a P-channel field effect transistor as a drive circuit element.
電界効果トランジスタを用いて構成する特許請求の範囲
第１項記載の論理回路。(28) The logic circuit according to claim 1, which is configured using a P-channel field effect transistor as a load circuit element for the drive circuit.
ンジスタを用いて構成する特許請求の範囲第１項記載の
論理回路。(29) The logic circuit according to claim 1, which is constructed using a P-channel field effect transistor as a control circuit element.
電界効果トランジスタを用いて構成する特許請求の範囲
第１項記載の論理回路。(30) The logic circuit according to claim 1, which is configured using a P-channel field effect transistor as a load circuit element for the control circuit.
たＭＥＳＦＥＴ（金属半導体電界効果トランジスタ）を
用いて構成する特許請求の範囲第１項記載の論理回路。(31) The logic circuit according to claim 1, which is constructed using MESFET (metal semiconductor field effect transistor) manufactured by self-alignment technology as a drive circuit element.
たＭＡＳＦＥＴ（Ｍｅｔａｌｌｉｃ Ａｍｏｒｐｈｏｕ
ｓ Ｓｉｌｉ−ｃｏｎ ｇａｔｅ電界効果トランジスタ
）を用いて構成する特許請求の範囲第１項記載の論理回
路。(32) MASFET (Metallic Amorphous) manufactured using self-alignment technology as a drive circuit element.
2. The logic circuit according to claim 1, wherein the logic circuit is configured using a S Sili-con gate field effect transistor.
により製作したＭＥＳＦＥＴ（金属半導体電界効果トラ
ンジスタ）を用いて構成する特許請求の範囲第１項記載
の論理回路。(33) The logic circuit according to claim 1, which is constructed using MESFET (metal semiconductor field effect transistor) manufactured by self-alignment technology as a load circuit element for a drive circuit.
により製作したＭＡＳＦＥＴ（Ｍｅｔａｌｌｉｃ Ａｍ
ｏｒｐｈｏｕｓ Ｓｉｌｉｃｏｎ ｇａｔｅ電界効果ト
ランジスタ）を用いて構成する特許請求の範囲第１項記
載の論理回路。(34) MASFET (Metallic Am
2. The logic circuit according to claim 1, wherein the logic circuit is constructed using an orthorous silicon gate field effect transistor.
たＭＥＳＦＥＴ（金属半導体電界効果トランジスタ）を
用いて構成する特許請求の範囲第１項記載の論理回路。(35) The logic circuit according to claim 1, which is constructed using MESFET (metal semiconductor field effect transistor) manufactured by self-alignment technology as a control circuit element.
たＭＡＳＦＥＴ（Ｍｅｔａｌｌｉｃ Ａｍｏｒｐｈｏｕ
ｓＳｉｌｉｃｏｎ ｇａｔｅ電界効果トランジスタ）を
用いて構成する特許請求の範囲第１項記載の論理回路。(36) MASFET (Metallic Amorphous) manufactured using self-alignment technology as a control circuit element.
2. The logic circuit according to claim 1, which is constructed using a sSilicon gate field effect transistor.
により製作したＭＥＳＦＥＴ（金属半導体電界効果トラ
ンジスタ）を用いて構成する特許請求の範囲第１項記載
の論理回路。(37) The logic circuit according to claim 1, which is constructed using MESFET (metal semiconductor field effect transistor) manufactured by self-alignment technology as a load circuit element for a control circuit.
により製作したＭＡＳＦＥＴ（ＭｅｔａｌｌｉｃＡｍｏ
ｒｐｈｏｕｓ Ｓｉｌｉｃｏｎ ｇａｔｅ電界効果トラ
ンジスタ）を用いて構成する特許請求の範囲第１項記載
の論理回路。(38) MASFET (MetallicAmo) manufactured using self-alignment technology as a load circuit element for the control circuit.
2. The logic circuit according to claim 1, wherein the logic circuit is configured using a silicon gate field effect transistor.
イオードと抵抗を用いて構成する特許請求の範囲第１項
記載の論理回路。(39) The logic circuit according to claim 1, which is configured using a Schottky diode and a resistor as a voltage shift circuit for input voltage.
素子と複数個の制御回路素子に導通状態と非導通状態を
発生させ、１個でも駆動回路素子が導通状態になれば、
最低１個の制御回路素子が導通状態になり、その制御回
路素子に流れる制御電流によって制御回路用の負荷回路
素子の両端に発生する電圧降下を利用して、駆動回路用
の負荷回路素子に流れる電流を減少するＮＯＲ回路（否
定的論理和回路）において、制御回路素子を駆動回路用
の負荷回路素子に接続して構成する特許請求の範囲第１
項記載の論理回路。(40) Generate conduction and non-conduction states in a plurality of drive circuit elements and a plurality of control circuit elements depending on the magnitude of the input voltage, and if even one drive circuit element becomes conduction,
At least one control circuit element becomes conductive, and the control current flowing through that control circuit element causes the voltage drop generated across the load circuit element for the control circuit to flow to the load circuit element for the drive circuit. Claim 1, which is configured by connecting a control circuit element to a load circuit element for a drive circuit in a NOR circuit (negative OR circuit) that reduces current.
Logic circuit described in section.
素子と制御回路素子に導通状態と非導通状態を発生させ
、全ての駆動回路素子が導通状態の期間においてのみ、
制御回路素子も導通状態になり、制御回路素子に流れろ
制御電流によって制御回路用の負荷回路素子の両端に発
生する電圧降下を利用して、駆動回路用の負荷回路素子
に流れる電流を減少するＮＡＮＤ回路（否定的論理積回
路）において、制御回路素子を駆動回路用の負荷回路素
子に接続して構成する特許請求の範囲第１項記載の論理
回路。(41) Generate a conductive state and a non-conductive state in a plurality of drive circuit elements and control circuit elements depending on the magnitude of the input voltage, and only during a period in which all drive circuit elements are in a conductive state.
The control circuit element also becomes conductive, and the voltage drop that occurs across the control circuit load circuit element due to the control current is used to reduce the current flowing to the drive circuit load circuit element. 2. The logic circuit according to claim 1, wherein the circuit (negative AND circuit) is configured by connecting a control circuit element to a load circuit element for a drive circuit.
御回路素子に導通状態と非導通状態を発生させ、駆動回
路素子が導通状態の期間においてのみ、制御回路素子も
導通状態になり、制御回路素子に流れる制御電流によっ
て制御回路用の負荷回路素子の両端に発生する電圧降下
を利用して、駆動回路用の負荷回路素子に流れる電流を
減少するＮＯＴ回路（否定回路）を構成する特許請求の
範囲第１項記載の論理回路。(42) generating conduction and non-conduction states in the drive circuit element and the control circuit element depending on the magnitude of the input voltage, and only during the period in which the drive circuit element is in the conduction state, the control circuit element is also in the conduction state; A patent that configures a NOT circuit (NOT circuit) that reduces the current flowing to a load circuit element for a drive circuit by utilizing the voltage drop that occurs across the load circuit element for the control circuit due to the control current flowing to the control circuit element. Logic circuit according to claim 1.
素子と複数個の制御回路素子に導通状態と非導通状態を
発生させ、１個でも駆動回路素子が導通状態になれば、
最低１個の制御回路素子が導通状態になり、その制御回
路素子に流れる制御電流によって制御回路用の負荷回路
素子の両端に発生する電圧降下を利用して、駆動回路用
の負荷回路素子に流れる電流を減少するＯＲ回路（論理
和回路）において、複数個の制御回路素子を駆動回路用
の負荷回路素子に接続して構成する特許請求の範囲第１
項記載の論理回路。(43) Generate conduction and non-conduction states in a plurality of drive circuit elements and a plurality of control circuit elements depending on the magnitude of the input voltage, and if even one drive circuit element becomes conduction,
At least one control circuit element becomes conductive, and the control current flowing through that control circuit element causes the voltage drop generated across the load circuit element for the control circuit to flow to the load circuit element for the drive circuit. Claim 1, which is configured by connecting a plurality of control circuit elements to a load circuit element for a drive circuit in an OR circuit (logical sum circuit) that reduces current.
Logic circuit described in section.
素子と制御回路素子に導通状態と非導通状態を発生させ
、全ての駆動回路素子が導通状態の期間においてのみ、
制御回路素子も導通状態になり、制御回路素子に流れる
制御電流によって制御回路用の負荷回路素子の両端に発
生する電圧降下を利用して、駆動回路用の負荷回路素子
に流れる電流を減少するＡＮＤ回路（論理積回路）にお
いて、制御回路素子を駆動回路用の負荷回路素子に接続
して構成する特許請求の範囲第１項記載の論理回路。(44) Generate a conductive state and a non-conductive state in a plurality of drive circuit elements and control circuit elements depending on the magnitude of the input voltage, and only during a period in which all drive circuit elements are in a conductive state.
The control circuit element also becomes conductive, and the voltage drop that occurs across the load circuit element for the control circuit due to the control current flowing through the control circuit element is used to reduce the current flowing to the load circuit element for the drive circuit. 2. The logic circuit according to claim 1, wherein the circuit (AND circuit) is configured by connecting a control circuit element to a load circuit element for a drive circuit.
素子と制御回路素子に導通状態と非導通状態を発生させ
、駆動回路素子が導通状態の期間においてのみ、制御回
路素子も導通状態になり、制御回路素子に流れる制御電
流によって制御回路用の負荷回路素子の両端に発生する
電圧降下を利用して、駆動回路用の負荷回路素子に流れ
る電流を減少するＸＯＲ回路（排他的論理和回路）にお
いて、制御回路素子を駆動回路用の負荷回路素子に接続
して構成する特許請求の範囲第１項記載の論理回路。(45) Generate a conductive state and a non-conductive state in a plurality of drive circuit elements and control circuit elements depending on the magnitude of the input voltage, and only during the period when the drive circuit element is in a conductive state, the control circuit element is also in a conductive state. The XOR circuit (exclusive OR circuit) reduces the current flowing to the load circuit element for the drive circuit by utilizing the voltage drop that occurs across the load circuit element for the control circuit due to the control current flowing to the control circuit element. 2. The logic circuit according to claim 1, wherein the logic circuit is configured by connecting a control circuit element to a load circuit element for a drive circuit in the circuit.
御回路素子に導通状態と非導通状態を発生させ、駆動回
路素子が導通状態の期間においてのみ、制御回路素子も
導通状態になり、制御回路素子に流れる制御電流によっ
て制御回路用の負荷回路素子の両端に発生する電圧降下
を利用して、駆動回路用の負荷回路素子に流れる電流を
減少する論理回路を複数個だけ用いてフリップフロップ
を構成する特許請求の範囲第１項記載の論理回路。(46) generating conduction and non-conduction states in the drive circuit element and the control circuit element depending on the magnitude of the input voltage, and only during the period in which the drive circuit element is in the conduction state, the control circuit element is also in the conduction state; A flip-flop is created using only a plurality of logic circuits that reduce the current flowing to the load circuit element for the drive circuit by utilizing the voltage drop that occurs across the load circuit element for the control circuit due to the control current flowing to the control circuit element. A logic circuit according to claim 1, which constitutes a logic circuit.
御回路素子に導通状態と非導通状態を発生させ、駆動回
路素子が導通状態の期間においてのみ、制御回路素子も
導通状態になり、制御回路素子に流れる制御電流によっ
て制御回路用の負荷回路素子の両端に発生する電圧降下
を利用して、駆動回路用の負荷回路素子に流れる電流を
減少する論理回路を複数個だけ用いて記憶回路を構成す
る特許請求の範囲第１項記載の論理回路。(47) Generating conduction and non-conduction states in the drive circuit element and the control circuit element depending on the magnitude of the input voltage, and only during the period in which the drive circuit element is in the conduction state, the control circuit element is also in the conduction state; A memory circuit using only a plurality of logic circuits that reduces the current flowing to the load circuit element for the drive circuit by utilizing the voltage drop that occurs across the load circuit element for the control circuit due to the control current flowing to the control circuit element. A logic circuit according to claim 1, which constitutes a logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61200884A JP2556684B2 (en) | 1986-08-26 | 1986-08-26 | Logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61200884A JP2556684B2 (en) | 1986-08-26 | 1986-08-26 | Logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6356016A true JPS6356016A (en) | 1988-03-10 |
| JP2556684B2 JP2556684B2 (en) | 1996-11-20 |
Family
ID=16431842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61200884A Expired - Fee Related JP2556684B2 (en) | 1986-08-26 | 1986-08-26 | Logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2556684B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4967105A (en) * | 1988-05-30 | 1990-10-30 | Sharp Kabushiki Kaisha | Load current control-type logic circuit |
| JP2002335153A (en) * | 2001-05-11 | 2002-11-22 | Semiconductor Energy Lab Co Ltd | Pulse output circuit, shift register and display |
| US7081786B2 (en) | 2002-08-01 | 2006-07-25 | Samsung Sdi Co., Ltd. | Level shifter and flat panel display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS526457A (en) * | 1975-07-07 | 1977-01-18 | Hitachi Ltd | Inverter circuit |
| JPS55115731A (en) * | 1979-02-28 | 1980-09-05 | Toshiba Corp | Semiconductor circuit |
-
1986
- 1986-08-26 JP JP61200884A patent/JP2556684B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS526457A (en) * | 1975-07-07 | 1977-01-18 | Hitachi Ltd | Inverter circuit |
| JPS55115731A (en) * | 1979-02-28 | 1980-09-05 | Toshiba Corp | Semiconductor circuit |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4967105A (en) * | 1988-05-30 | 1990-10-30 | Sharp Kabushiki Kaisha | Load current control-type logic circuit |
| US8786533B2 (en) | 2001-05-11 | 2014-07-22 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US7710384B2 (en) | 2001-05-11 | 2010-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US8264445B2 (en) | 2001-05-11 | 2012-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US20130057161A1 (en) | 2001-05-11 | 2013-03-07 | Semiconductor Energy Laboratory Co., Ltd. | Pulse Output Circuit, Shift Register and Display Device |
| JP2002335153A (en) * | 2001-05-11 | 2002-11-22 | Semiconductor Energy Lab Co Ltd | Pulse output circuit, shift register and display |
| US9105520B2 (en) | 2001-05-11 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US9496291B2 (en) | 2001-05-11 | 2016-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US9812218B2 (en) | 2001-05-11 | 2017-11-07 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US10109368B2 (en) | 2001-05-11 | 2018-10-23 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US10424390B2 (en) | 2001-05-11 | 2019-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US10916319B2 (en) | 2001-05-11 | 2021-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, shift register and display device |
| US7081786B2 (en) | 2002-08-01 | 2006-07-25 | Samsung Sdi Co., Ltd. | Level shifter and flat panel display |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2556684B2 (en) | 1996-11-20 |
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