JP2013198064A - Digital-analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To furthermore suppress occurrence of a distortion of an analog output signal due to an on resistance value of a switch.SOLUTION: A feedback switch section 240 comprises a plurality of complementary MOS transistors connectable between one end of a sampling capacitive element section 250 and an output terminal of an operational amplification section 12. A clock generation section 11 supplies a first clock transitioning between a first high voltage level and a first low voltage level lower than the first high voltage level to gate terminals of first MOS transistors, and supplies a second clock transitioning between a second high voltage level and a second low voltage level lower than the second high voltage level to gate terminals of second MOS transistors other than the first MOS transistors. The feedback switch section 240 can adjust the first high voltage level and the second low voltage level.

Description

  The present invention relates to a digital-to-analog converter, and more particularly to a switched capacitor type digital-to-analog converter that converts a digital input signal into an analog output signal.

In general, in a digital / analog converter used in the audio field, a demand for distortion is severe, and a slight conversion error of an analog output signal causes deterioration of characteristics.
In the digital-analog converter, the capacitive element is charged according to the signal level of the digital input signal, and the operational amplifier outputs an analog output signal according to the charging voltage of the capacitive element. In the digital-analog converter having such a configuration, in order to realize low distortion, the connection between the input terminal of the digital input signal and the capacitive element and the output terminal of the operational amplifier when the capacitive element and the operational amplifier are connected. What is comprised so that it may connect is disclosed by patent document 1, for example.

  FIG. 1 is a circuit configuration diagram of a digital / analog converter disclosed in Patent Document 1. FIGS. 2A to 2D are control waveforms of switches in the digital / analog converter 100 shown in FIG. The vertical axis represents “H” or “L” of the level of the control clock signal CK1, and the horizontal axis represents time. 2A shows the waveform of the control clock signal CK1 input to the switch unit 110, FIG. 2B shows the waveform of the control clock signal CK2 input to the switch 120, and FIG. FIG. 2D shows the waveform of the control clock signal CK4 input to the switch unit 140. FIG. In the figure, reference numeral 1 denotes a control clock generator, and 2 denotes an operational amplifier.

  The switches 110 and 120 (SW 1 and SW 2) are turned on while CK 1 and CK 2 are “H”, and the capacitance corresponding to the signal level of the digital input signal is charged in the sampling capacitor 150 (Cs). Next, after the switches SW1 and SW2 are turned off, the switches 130 and 140 (SW3 and SW4) are turned on while the CK3 and CK4 are “H” to connect the sampling capacitor element Cs and the integral capacitor element 160 (Ci) in series. And the sampling capacitor Cs and the output terminal Vout of the operational amplifier are connected, and the potential of the output terminal Vout changes. In such a digital-analog converter, a configuration having a MOS transistor is generally used as a switch.

  That is, the switches and switches 120 and 130 included in the switch units 110 and 140 are both turned on when the control signal is “H” and turned off when the control signal is “L”. In addition, a period in which the switch unit 110 and the switch 120 are turned on is a first period, and a period in which the switch 130 and the switch unit 140 are turned on is a second period.

The digital-analog converter 100 described above constitutes a direct transmission type digital-analog converter. The digital-analog converter 100 may perform digital-analog conversion after delta-sigma modulation of the digital input signal.
FIG. 3 is a diagram showing a MOS transistor that constitutes the fourth switch unit shown in FIG. 1, and shows a MOS transistor that constitutes the feedback switch 140 (SW4) that connects the capacitive element Cs and the output terminal Vout. . 4A and 4B are diagrams showing control clock waveforms of the MOS transistor shown in FIG.

As shown in FIG. 3, the feedback switch SW4 includes a P-type MOS transistor 140P and an N-type MOS transistor 140N. The source terminals or drain terminals of the P-type MOS transistor 140P and the N-type MOS transistor 140N are connected to the output terminal of the operational amplifier 2.
The PMOS control waveform is CK-P, and the NMOS control waveform is CK-N. When CK-P becomes “L” level and CK-N becomes “H” level, SW4 is turned on. In general, the “L” level is the ground level, and the “H” level is the power supply voltage level.

  The resistance values (ON resistance) when the switches SW3 and SW4 are in the ON state are Rsw3 and Rsw4. The output terminal Vout exhibits a transient characteristic depending on a time constant (Rsw3 + Rsw4) * Ci * Cs / (Ci + Cs) due to serial connection of Ci, Cs and Rsw3 and Rsw4. However, the on-resistance Rsw3 of the MOS transistor of the switch SW3 does not change with respect to the potential of the output terminal Vout, but the on-resistance Rsw4 of the MOS transistor of the switch SW4 is the potential of the output terminal Vout that is the source (or drain) terminal of the MOS. It is known to change depending on

JP-A-11-55121 (Patent No. 3852721)

However, as described in Patent Document 1 described above, the transient characteristics change due to fluctuations in the on-resistance value of the MOS transistor that constitutes the switch SW4 that connects the capacitive element Cs and the output terminal Vout, thereby causing distortion. There is a problem that the characteristics deteriorate.
FIG. 5 is a graph showing changes in the on-resistance value Rsw4 of the MOS transistor constituting the switch SW4 that connects the capacitive element Cs and the output terminal Vout. The graph shown in the lower part of FIG. 5 shows how the voltage at the output terminal Vout fluctuates with a constant amplitude, and the graph shown in the upper part of FIG. 5 outputs like the graph shown in the lower part. It is a figure which shows the change of ON resistance value Rsw4 when the voltage of the terminal Vout changes. As shown in FIG. 5, when the voltage of Vout varies, the on-resistance value Rsw4 greatly changes accordingly.

  FIG. 6 is an enlarged graph showing the transient characteristics of the output terminal Vout when the on-resistance value Rsw4 of the MOS transistor shown in FIG. 5 is the maximum value “a” and the minimum value “b”. As shown in FIG. 5, the transient characteristics are different between “a” and “b” having different on-resistance values. In this way, the transient characteristic changes due to the change of the on-resistance value of the switch, and thereby the distortion characteristic deteriorates.

  That is, FIG. 6 is a diagram showing the relationship between the analog output signal Vout and time. The vertical axis represents the analog output signal Vout, and the horizontal axis represents time. A curve La in FIG. 6 shows the relationship between the analog output signal Vout and time when the on-resistance value Rsw4 of the switch unit SW4 is indicated by the point a shown in FIG. A curve Lb shows the relationship between the analog output signal VAout and time when the on-resistance value Rsw4 of the switch unit SW4 is indicated by a point b shown in FIG.

As is apparent from the curves La and Lb shown in FIG. 6, the transient characteristics differ when the on-resistance values of the switches used in the digital-analog converter are different. The degree of the difference between the transient characteristics is represented by a length d generated between the curve La and the curve Lb. Further, the difference in the transient characteristic of the analog output signal Vout appears as deterioration of the distortion characteristic of the digital-analog converter.
The present invention has been made in view of such problems, and an object of the present invention is to provide a digital circuit that can further suppress the occurrence of distortion of an analog output signal due to the on-resistance value of a switch with a simple circuit configuration. • To provide an analog converter.

The present invention has been made to achieve such an object, and the invention according to claim 1 is a digital / analog capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch. A converter, a sampling capacitor element section (Cs) comprising a plurality of sampling capacitor elements provided corresponding to a plurality of input terminals to which a plurality of bit signals constituting a digital signal are respectively input, and the sampling capacitor An operational amplifier (12) connected to the element section (Cs), and a plurality of complementary MOSs connectable between one end of the sampling capacitor element section (Cs) and an output terminal of the operational amplifier section (12) Connection is possible between a feedback switch unit (SW4) composed of a transistor and the other end of the sampling capacitor unit (Cs) and an input terminal of the operational amplifier unit (12). A first summing node switch unit (SW3) and a gate terminal of one of the plurality of complementary MOS transistors having a first conductivity type, a first high voltage level and a first high voltage level lower than the first high voltage level. A first clock that transitions between a first low voltage level and a second high voltage level is connected to the second MOS transistor of a conductivity type opposite to the first MOS transistor. A control clock generator (11) for supplying a second clock that transitions between a second low voltage level lower than the high voltage level, and at least the first high voltage level and the second low voltage level It is comprised so that adjustment can be carried out. (FIG. 7; Example 1)
According to a second aspect of the present invention, in the first aspect of the invention, the first high voltage level is at least a level higher than a power supply voltage level, and the second constant voltage level is at least a ground level. It is characterized by a lower level.

  According to a third aspect of the present invention, there is provided a digital-to-analog converter capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch, wherein a plurality of bit signals constituting the digital signal are converted. A plurality of input terminals (D1 to DN) to which corresponding signals are respectively input, a sampling capacitor element section (Cs) comprising a plurality of sampling capacitor elements provided corresponding to the plurality of input terminals, and the sampling capacitor A first switch unit (SW1) that switches connection and disconnection between the one input terminal of the element section (Cs) and the corresponding input terminals; the other terminal of the sampling capacitor element section (Cs); A second switch (SW2) that switches connection and disconnection with the voltage source (Vr1), and a second reference voltage source (Vr2) connected to the non-inverting input terminal (+). The operational amplifier (12) to which a reference voltage is applied and the other terminal of the sampling capacitor element (Cs) and the operational amplifier according to disconnection and connection in switching of the first switch unit (SW1) A third switch (SW3) that switches connection and disconnection with the inverting input terminal (−) and connection and disconnection between the other terminal of the sampling capacitor element section (Cs) and one terminal of the integrating capacitor element (Ci). And connection and disconnection of the one terminal of the sampling capacitor element section (Cs), connection and disconnection of the one terminal of the sampling capacitor element section (Cs) and the output terminal of the operational amplifier, and the sampling A fourth switch unit that switches connection and disconnection between the capacitive element section (Cs) and the other terminal of the integrating capacitive element (Ci) ( W4), a clock for controlling the first switch unit (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch unit (SW4) are generated. A control clock generator (11), a fourth switch unit (SW4), a first level adjustment circuit (13a) capable of adjusting at least the first high voltage level, and the second low voltage level. A second level adjustment circuit (13b) that can be adjusted, and two clocks (CK-P and CK-N in FIG. 8) that control the PMOS transistor and NMOS transistor that constitute the fourth switch unit (SW4) , Respectively, by adjusting the potentials of the “L” level and the “H” level, respectively. (FIG. 7; Example 1)

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the level of the clock that controls the gate terminals of the PMOS transistor and the NMOS transistor that constitute the fourth switch unit (SW4) is the PMOS. Only the level of the clock (CK-P in FIG. 8) that controls the gate terminal of the transistor is made lower than the ground level, and the potential of the clock (CK-N in FIG. 8) that controls the gate terminal of the NMOS transistor is the power supply voltage level. The level of the clock (CK-P in FIG. 8) for controlling the gate terminal of the PMOS transistor is set to the ground level, and only the level of the clock (CK-N in FIG. 8) for controlling the gate terminal of the NMOS transistor is used as the power source. It is characterized by being higher than the voltage level.

  According to a fifth aspect of the present invention, in the third aspect of the present invention, the level of a clock that controls the gate terminals of the PMOS transistor and the NMOS transistor that constitute the fourth switch unit (SW4) is the PMOS. The potential of the clock (CK-P in FIG. 8) that controls the gate terminal of the transistor is lower than the ground level, and the level of the clock (CK-N in FIG. 8) that controls the gate terminal of the NMOS transistor is the power supply voltage level. It is characterized by making it higher.

  According to a sixth aspect of the present invention, there is provided a digital-to-analog converter capable of suppressing the occurrence of distortion of an analog output signal due to the on-resistance value of a switch. A plurality of input terminals (D1a to DNa, D1b to DNb) to which corresponding signals are respectively input, a plurality of sampling capacitor elements (Csa, Csb) provided corresponding to the plurality of input terminals, and the plurality A plurality of first switch units (SW1a, SW1b) for switching connection and disconnection between one terminal of the sampling capacitor element portions (Csa, Csb) and the corresponding input terminals, and the plurality of sampling capacitor element portions A plurality of second switches for switching connection and disconnection between the other terminal of (Csa, Csb) and the reference voltage source (Vr1a, Vr1b). H (SW2a, SW2b), an operational amplifier (22) in which the reference voltage source (Vr1a, Vr1b) is applied to the non-inverting input terminal (+) or the inverting input terminal (−), and the first switch unit ( In accordance with disconnection and connection in switching of SW1a and SW1b), connection and disconnection between the other terminal of the plurality of sampling capacitor elements (Csa, Csb) and the inverting input terminal (−) of the operational amplifier, and the plurality A plurality of third switches (SW3a, SW3b) for switching connection and disconnection between the other terminal of the sampling capacitor element section (Csa, Csb) and one terminal of the integrating capacitor element (Ci), and the plurality of sampling Mutual connection and disconnection of the one terminals of the capacitive element portions (Csa, Csb) and the plurality of sampling capacitive element portions (Csa, Cs) and b) connecting and disconnecting the one terminal and the output terminal of the operational amplifier, and connecting the plurality of sampling capacitor elements (Csa, Csb) and the other terminal of the plurality of integral capacitors (Cia, Cib). A plurality of fourth switch units (SW4a, SW4b) for switching between connection and disconnection, the first switch units (SW1a, SW1b), the second switches (SW2a, SW2b), and the third switches (SW3a, SW3b) and a control clock generator (21) for generating a clock for controlling the fourth switch unit (SW4a, SW4b), and a PMOS constituting the fourth switch unit (SW4a, SW4b) Two clocks (CK-P and C in FIG. 8) that control the transistor and the NMOS transistor With regard to (K−N), the “L” level potential and the “H” level potential are adjusted. (FIG. 14; Example 2)

  According to the present invention, it is possible to obtain an effect of suppressing distortion and noise of an analog output signal due to a change in on-resistance value of a switch with a simple configuration. Further, distortion of the analog output signal can be prevented without adding a new switch or element to the signal path and without affecting the response speed allowed in the digital / analog converter.

2 is a circuit configuration diagram of a digital / analog converter disclosed in Patent Document 1. FIG. (A) thru | or (d) is a figure which shows the control waveform of the switch in the digital-analog converter shown in FIG. It is a figure which shows the MOS transistor which comprises the 4th switch unit shown in FIG. (A), (b) is a figure which shows the control clock waveform of the MOS transistor shown in FIG. It is a figure which shows the change of ON resistance value Rsw4 of the MOS transistor which comprises switch SW4 which connects the capacitive element Cs and the output terminal Vout in a graph. FIG. 6 is an enlarged graph showing the transient characteristics of the output terminal Vout when the on-resistance value Rsw4 of the MOS transistor shown in FIG. 5 is a maximum value “a” and a minimum value “b”. It is a circuit block diagram for demonstrating Example 1 of the digital-analog converter based on this invention. FIG. 8 is a diagram showing a control clock generation circuit for PMOS and NMOS transistors constituting the fourth switch unit in the digital-analog converter shown in FIG. 7. (A), (b) is a figure which shows the 1st level adjustment circuit in the control clock generation circuit shown in FIG. (A), (b) is a figure which shows the 2nd level adjustment circuit in the control clock generation circuit shown in FIG. (A), (b) is a figure which shows the control clock waveform of the MOS transistor shown to Fig.10 (a), (b). It is a figure which shows the change of ON resistance value Rsw4 of the MOS transistor which comprises switch SW4 which connects the capacitive element Cs and the output terminal Vout in a graph. FIG. 13 is an enlarged graph showing the transient characteristics of the output terminal Vout when the on-resistance value Rsw4 of the MOS transistor shown in FIG. 12 is a maximum value “a” and a minimum value “b”. It is a circuit block diagram for demonstrating Example 2 of the digital-analog converter based on this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a circuit configuration diagram for explaining the first embodiment of the digital-analog converter according to the present invention. In the figure, reference numeral 11 denotes a control clock generator, and 12 denotes an operational amplifier.
The digital / analog converter 200 according to the present invention is a digital / analog converter capable of suppressing the occurrence of distortion of an analog output signal due to the on-resistance value of a switch.

The sampling capacitor element unit Cs includes a plurality of sampling capacitor elements provided corresponding to a plurality of input terminals to which a plurality of bit signals constituting a digital signal are respectively input. In addition, the operational amplification unit 12 is connected to the sampling capacitor element unit Cs.
The feedback switch unit SW4 is composed of a plurality of complementary MOS transistors connectable between one end of the sampling capacitor element unit Cs and the output terminal of the operational amplifier unit 12. Further, the summing node switch unit SW3 can be connected between the other end of the sampling capacitor element unit Cs and the input terminal of the operational amplifier unit 12.

Further, the control clock generator 11 has a first high voltage level and a first low voltage lower than the first high voltage level at the gate terminal of one of the plurality of complementary MOS transistors. A first clock that transitions between the voltage levels is supplied, and the second high voltage level and the second high voltage level are connected to the gate terminal of the second MOS transistor having the other conductivity type than the first MOS transistor. And a second clock that transitions between a lower second low voltage level. And at least the first high voltage level and the second low voltage level can be adjusted. With such a configuration, distortion and noise of the analog output signal due to fluctuations in the on-resistance value of the switch can be suppressed with a simple configuration. It is possible to realize a digital-analog converter that can do this.

  In the digital-analog converter according to the present invention, the plurality of input terminals D1 to DN are respectively input with a plurality of bit signals constituting a digital signal. The sampling capacitor element section Cs includes a plurality of sampling capacitor elements 250 (251 to 25N (Cs1 to CsN)) provided corresponding to the plurality of input terminals D1 to DN.

In addition, the first switch unit 210 (SW1) switches connection and disconnection between a plurality of input terminals D1 to DN corresponding to one terminal of the sampling capacitor element portion 250 (Cs). The second switch 220 (SW2) switches connection and disconnection between the other terminal of the sampling capacitor element portion Cs and the first reference voltage source Vr1.
In the operational amplifier 12, the second reference voltage of the second reference voltage source Vr2 is applied to the non-inverting input terminal (+).

The third switch 230 (SW3) connects and disconnects the other terminal of the sampling capacitor element section Cs and the inverting input terminal (−) of the operational amplifier 12 according to disconnection and connection in switching the first switch unit SW1. Disconnection and connection and disconnection of the other terminal of the sampling capacitor element section Cs and one terminal of the integrating capacitor element Ci are switched.
The fourth switch unit 240 (SW4) connects and disconnects one terminal of the sampling capacitor element unit Cs, and connects and disconnects one terminal of the sampling capacitor element unit Cs and the output terminal of the operational amplifier 12. In addition, the connection and disconnection of the sampling capacitor element section Cs and the other terminal of the integration capacitor element 260 (Ci) are switched.

The control clock generator 11 generates a clock for controlling the first switch unit SW1, the second switch SW2, the third switch SW3, and the fourth switch unit SW4.
That is, as shown in FIG. 7, the digital-analog converter 200 of the first embodiment is a switched capacitor type digital-analog converter. The digital-analog converter 100 receives input signals VDin1, VDin2,... VDinN corresponding to digital data, and outputs an analog output signal Vout.

  The digital-analog converter 100 includes input terminals D1, D2, ... DN and input terminals D1, D2, ... DN to which input signals VDin1, VDin2, ... VDinN corresponding to digital data are inputted. Sampling capacitive elements 250 (251, 252,... 25N) provided in a one-to-one relationship with the input terminals D1, D2,... DN, and input terminals D1, D2,. .., 125N provided between the sampling capacitor elements 251, 252,... 125N associated therewith.

The sampling capacitors 251, 252,... 25N may all have the same capacitance (CS1 = CS2 =... CSN). Further, the capacitance may be set to CSi = 2 ^i-1 CS (i-1) so that the capacitance ratio of the sampling capacitive elements 251, 252,... 25N becomes a binary ratio (2 ^i-1 times). . .., 25N are connected to a switch 230 (SW3) and a switch 220 (SW2). The switch 220 is connected to the sampling capacitors 251, 252,... , And the power supply applies the reference voltage Vr1 to the sampling capacitors 251, 252,... 25N.

The digital-analog converter 200 includes an operational amplifier 12. The switch 230 electrically connects and disconnects the inverting input terminal of the operational amplifier 12 and the sampling capacitors 251, 252,... 25N. The switch 230 connected to the inverting input terminal is also referred to as a summing node switch.
A power source is connected to the non-inverting input terminal of the operational amplifier 12, and a reference voltage Vr2 is applied to the non-inverting input terminal by the power source. The output terminal of the operational amplifier 12 is connected to the output terminal of the digital-analog converter 200 and outputs an analog output signal Vout. The reference voltage Vr1 and the reference voltage Vr2 may be the same value.

  An integrating capacitive element 260 is provided between the output terminal and the inverting input terminal of the operational amplifier 12. The output terminal of the operational amplifier 12 is further connected between the switches 211, 212,... 21N and the sampling capacitors 251, 252,. , 21N and sampling capacitors 251, 252,... 25N are provided with switches 240 (241, 242,... 24N). The analog output signal Vout is returned from the output terminal of the operational amplifier 12 to the switches 211, 212,... 21N and the sampling capacitors 251, 252,. Also called a switch.

  In the above configuration, all the switches are configured using MOS transistors. The switches 211, 212,... 21N are referred to as a switch unit 210 (SW1). Further, the switches 241, 242,... 24N are referred to as a switch unit 240 (SW4). Further, the sampling capacitive elements 251, 252,..., 25N are defined as sampling capacitive element units 250 (Cs).

  SW1, SW4, switch SW2, and switch SW3 are turned on and off by control clock signals CK1 to CK4 generated by the control clock generator 11. At this time, the switches 211, 212,... 21N included in the switch unit 210 are turned on and off at the same time, and the on-resistance value Rsw4 when the switches 211, 212,. ... combining each on-resistance value of 21N. The switches 241, 242,... 24N included in the switch unit 240 are simultaneously turned on and off, and the on-resistance value Rsw4 when the switches 241, 242,... 24N are turned on is the switches 241, 242,. The on-resistance values of 24N are synthesized. The on-resistance value of the switch 230 is Rsw3, and the on-resistance value of the switch 220 is Rsw2.

In the digital-analog converter 200 shown in FIG. 7, the number of switches included in the input terminals D1, D2,... DN, sampling capacitance elements 251, 252,. (N: N is a natural number) are the same number.
FIG. 8 is a diagram showing a control clock generation circuit for PMOS and NMOS transistors constituting the fourth switch unit in the digital-analog converter shown in FIG. The circuit configuration of the fourth switch unit is shown in FIG. 3, and FIG. 8 shows the generation of the control clock for generating the gate control clocks “CK_P” and “CK_N” of this MOS transistor.

The fourth switch unit SW4 includes a first level adjustment circuit 13a that can adjust at least the first high voltage level and a second level adjustment circuit 13b that can adjust the second low voltage level.
Further, the potentials of the “L” level and the “H” level are adjusted for the two clocks CK-P and CK-N that control the PMOS transistor and the NMOS transistor constituting the fourth switch unit SW4.

  Further, the level of the clock for controlling the gate terminals of the PMOS transistor and NMOS transistor constituting the fourth switch unit SW4 is set such that only the level of the clock CK-P for controlling the gate terminal of the PMOS transistor is lower than the ground level. The potential of the clock CK-N for controlling the gate terminal of the transistor may be the power supply voltage level, the level of the clock CK-P for controlling the gate terminal of the PMOS transistor is set to the ground level, and the clock for controlling the gate terminal of the NMOS transistor. Only the level of CK-N may be higher than the power supply voltage level.

That is, 1) CK-P <GND and CK-N> VDD, 2) CK-P <GND and CK-N = VDD, and 3) CK-P = GND and CK-N> VDD. Also good.
With such a configuration, when the first switch unit SW1 and the second switch SW2 are connected, the plurality of sampling capacitors are charged according to the signal levels of the plurality of bit signals constituting the digital input signal. After that, when the first switch unit SW1 and the second switch SW2 are disconnected and the third switch SW3 and the fourth switch unit SW4 are connected, the sampling capacitor element Cs, the integration capacitor element Ci, the operational amplifier 12, Is formed, and the operational amplifier outputs a voltage corresponding to the charging voltage of the sampling capacitor Cs as an analog output signal.

  At this time, assuming that the on-resistances of the third switch SW3 and the fourth switch unit SW4 are Rsw3 and Rsw4, the analog output signal is a time constant (Rsw3 + Rsw4) * Ci * Cs / by serial connection of Ci, Cs and Rsw3, Rsw4. The transient characteristic depending on (Ci + Cs) is shown. Here, in the configuration of the present invention, when turning on the PMOS transistor and the NMOS transistor constituting the fourth switch unit SW4, the level of the clock CK-P for controlling the gate terminal of the PMOS transistor is lower than the ground level, and By making the level of the clock CK-N for controlling the gate terminal of the NMOS transistor higher than the power supply voltage level, the fluctuation range in which the on-resistance Rsw4 of the fourth switch unit SW4 changes with respect to the level of the analog output signal Vout is increased. Since it can be adjusted to be small, the occurrence of distortion can be suppressed.

In addition, distortion of the analog output signal can be prevented without adding a new switch or element to the signal path and without affecting the response speed allowed in the digital / analog converter.
That is, the digital-to-analog converter shown in FIG. 7 is a switched capacitor type digital-to-analog converter, and a plurality of input terminals Di (i = i = 10) to which a plurality of bit signals constituting a digital input signal are respectively input. 1 to N) and a plurality of sampling capacitance elements Csi (i = 1 to N) provided corresponding to the plurality of input terminals Di. The sampling capacitor Csi is charged to the first reference voltage Vr1 according to the signal level (voltage Vref + or Vref−) of the bit signal input from the corresponding input terminal Di. A first switch unit SW1i (i = 1 to N) that switches between connection and disconnection with one terminal of a plurality of sampling capacitor elements Csi corresponding to a plurality of input terminals Di to which a plurality of bit signals are respectively input. However, a second switch SW2 for switching between connection and disconnection is provided between the first reference voltage source Vr1 and the other terminal of the sampling capacitor Csi, and each switch is constituted by a MOS transistor. ing.

  Further, the digital / analog converter includes an operational amplifier (op-amp) that outputs an analog output signal Vout based on the charging voltage of the sampling capacitor Csi. The sampling capacitor Csi is applied to the inverting input terminal of the operational amplifier, and the second reference voltage source Vr2 is applied to the non-inverting input terminal of the operational amplifier. The second reference voltage source Vr1 may be the same as the first reference voltage source Vr2 (Vr1 = Vr2).

The sampling capacitance elements Csi may all have the same capacitance (Cs1 = Cs2 =... = CsN), or a capacitance such that the capacitance ratio of each sampling capacitance element Csi is a binary ratio (2 _i-1 times). (Csi = 2 _i-1 Cs (i-1)) may be included.
The digital / analog converter includes a fourth switch unit SW4i (i = 1 to N) provided between one terminal of the sampling capacitor Csi and the output terminal of the operational amplifier, and the sampling capacitor Csi. A third switch SW3 provided between the other terminal and the inverting input terminal of the operational amplifier is included.

A plurality of input terminals Di, a sampling capacitor Csi, a first switch unit SW1i, and a fourth switch unit SW4i to which a plurality of bit signals constituting a digital input signal are respectively input are provided in the same number (N). Yes.
The first switch unit SW1i (i = 1 to N) will be collectively referred to as SW1, and the fourth switch unit SW4i (i = 1 to N) will be collectively referred to as SW4. When the first switch unit SW1 and the second switch SW2 are connected, the sampling capacitor Csi is charged to the first quasi-voltage source Vr1 according to the signal level of the bit signal input from the input terminal Di (first voltage source Vr1). 1 period). Next, the first switch unit SW1 and the second switch SW2 are disconnected, and the third switch SW3 and the fourth switch unit SW4 are connected, so that an analog output is made based on the charging voltage of the sampling capacitor Csi. The signal Vout changes (second period). The first period and the second period are alternately performed periodically. Thus, the digital / analog converter 1 of the present embodiment constitutes an integral type digital / analog converter.

  In the second period, the third switch SW3, the fourth switch unit SW4, the sampling capacitor element Csi, and the integration capacitor element Ci are connected in series to form a closed loop. If the on-resistance of the MOS transistor constituting the third switch SW3 is Rsw3 and the combined on-resistance of all the MOS transistors constituting the fourth switch unit SW4 is Rsw4, the closed loop time constant is (Rsw3 + Rsw4) * Ci * Cs / (Ci + Cs), and the analog output signal Vout exhibits a transient characteristic depending on the time constant of the closed loop.

  Here, the on-resistance Rsw4 of the MOS transistor constituting the fourth switch unit SW4 will be described in more detail. The fourth switch unit SW4 includes a PMOS transistor and an NMOS transistor. These MOS transistors have a characteristic that the on-resistance value decreases as the voltage between the gate terminal as the control terminal and the source terminal or drain terminal as the main terminal exceeds the threshold voltage of the MOS transistor (the voltage dependence of the on-resistance value). ). Therefore, in the second period of this embodiment, when the fourth switch unit SW4 is connected, the source terminal and the drain terminal of the MOS transistor constituting the fourth switch unit SW4 become the potential of the analog output signal Vout. Therefore, the on-resistance value changes depending on the potential of the analog output signal Vout.

  Further, the on-resistance Rsw4 of the fourth switch unit SW4 will be described in detail. Assuming that the threshold voltages of the PMOS transistor and NMOS transistor constituting the fourth switch unit SW4 are Vth_P and Vth_N, respectively, and the potentials of the gate terminals of the PMOS transistor and NMOS transistor in the second period of this embodiment are VG_P and VG_N, respectively. When the potential of the analog output signal Vout, which is the potential of the source (drain) terminal of the MOS transistor constituting the switch unit SW4 of FIG. 4, approaches VG_P-Vth_P and VG_N-Vth_N, "c" and "a" in FIG. As shown in FIG. 2, the on-resistance value suddenly increases, and the fluctuation range of the on-resistance Rsw4 is increased due to this characteristic.

On the other hand, regarding the on-resistance Rsw3 of the MOS transistor constituting the third switch SW3, the potentials of the source terminal and the drain terminal of the MOS transistor constituting the third switch SW3 do not change depending on the signal level in the second period of the present embodiment. Therefore, the on-resistance value is a constant value.
The time constant of the closed loop is (Rsw3 + Rsw4) * Ci * Cs / (Ci + Cs). As Rsw4 changes depending on the potential of the analog output signal Vout, the time constant of the closed loop also changes, and the analog output signal Vout The transient characteristics change depending on the potential of Vout, leading to the generation of distortion.

  In the present embodiment, the control clock generator 11 of the fourth switch unit SW4 in the control clock generator 11 for generating a clock includes a first level adjusting circuit 13a and a second level adjusting circuit as shown in FIG. A circuit 13b is provided. The first level adjustment circuit 13a adjusts the level VG_P of the PMOS gate terminal constituting the fourth switch unit SW4 in the second period of this embodiment, that is, the “L” level of the control clock CK-P. The second level adjustment circuit 13b is the level VG_N of the gate terminal of the NMOS transistor constituting the fourth switch unit SW4 in the second period of the present embodiment, that is, the “H” level of the control clock CK-N. It is a circuit that adjusts.

FIGS. 9A and 9B are diagrams showing a first level adjustment circuit in the control clock generation circuit shown in FIG. FIG. 9A shows a case where CK4 ′ = “L”, and FIG. 9B shows a case where CK4 ′ = “H”.
CK4 ′ shown in FIG. 8 is a clock that becomes “H” level in the second period of this embodiment, and the first level adjustment circuit 13a shown in FIG. 9 has a clock CK4N ′ obtained by inverting CK4 ′. Entered. The first level adjustment circuit 13a includes a capacitive element CP connected to the input CK4N ′, a switch that switches connection and disconnection between the other terminal CKP ′ of the capacitive element CP and the third reference voltage Vr3, and the other of the capacitive element CP. A switch for switching connection and disconnection between the terminal CKP ′ and the output terminal CK-P, and a switch for switching connection and disconnection between the output terminal CK-P and the power supply voltage VDD. The level of the third reference voltage Vr3 is set to the power supply voltage VDD or lower.

  FIG. 9A shows a state in a period in which CK4 'is "L" other than the second period of the present embodiment. At this time, the input CK4N 'becomes "H" level, that is, the level of the power supply voltage VDD. During this time, the other terminal CKP ′ of the capacitive element CP is connected to the third reference voltage Vr3, and a potential difference of VDD−Vr3 is generated between both ends of the capacitive element CP. The output terminal CK-P is disconnected from the other terminal CKP 'of the capacitive element CP and connected to the power supply voltage VDD, and outputs the level of VDD.

  Next, FIG. 9B shows a state in which the CK4 'in the second period of this embodiment is "H". At this time, the input CK4N ′ is at the “L” level, that is, the level of the ground VSS. At this time, the other terminal CKP ′ of the capacitive element CP and the third reference voltage Vr3, and the output terminal CK-P and the power supply voltage VDD are disconnected, and the other terminal CKP ′ and the output terminal CK− of the capacitive element CP are disconnected. P is connected. Here, since the charge of the capacitive element CP is ideally held, CKP ′ is at a level of VSS− (VDD−Vr3). Therefore, the output terminal CK-P outputs a level of VSS- (VDD-Vr3) lower than the level of the ground VSS.

  As described above, the first level adjustment circuit 13a outputs the “H” level of the clock CK-P that controls the gate terminal of the PMOS transistor constituting the fourth switch unit SW4 at the level of the power supply voltage VDD. It has a function of outputting the “L” level at a level lower than the level of the ground VSS. FIG. 9 is an example of the first level adjustment circuit 13a, and the first level adjustment circuit may be configured by other circuits having the same function.

10A and 10B are diagrams showing the second level adjustment circuit in the control clock generation circuit shown in FIG. 8, and FIG. 10A shows the case where CK4 ′ = “L”. 10 (b) shows a case where CK4 ′ = “H”.
The second level adjustment circuit 13b shown in FIG. 8 receives a clock CK4 ′ that becomes “H” level in the second period of this embodiment. The second level adjustment circuit 13b includes a capacitive element CN connected to the input CK4 ′, a switch that switches connection and disconnection between the other terminal CKN ′ of the capacitive element CN and the fourth reference voltage Vr4, and the other of the capacitive element CP. A switch for switching connection and disconnection between the terminal CKN ′ and the output terminal CK-N, and a switch for switching connection and disconnection between the output terminal CK-N and the ground VSS. The level of the fourth reference voltage Vr4 is not less than the level of the ground VSS.

  FIG. 10A shows a state in which the CK 4 ′ is “L” other than the second period of the present embodiment. At this time, the input CK4 'is at the level of the ground VSS. During this time, the other terminal CKN 'of the capacitive element CN and the fourth reference voltage Vr4 are connected, and a potential difference of Vr4-VSS is generated at both ends of the capacitive element CN. The output terminal CK-N is disconnected from the other terminal CKN ′ of the capacitor CN and connected to the ground VSS, and outputs the level of VSS.

  Next, FIG. 10B shows a state in which the CK4 'in the second period of this embodiment is "H". At this time, the input is at the level of the power supply voltage VDD. At this time, the other terminal CKN ′ and the fourth reference voltage Vr4 of the capacitor element CN and the output terminal CK-N and the ground VSS are disconnected, and the other terminal CKN ′ and the output terminal CK-N of the capacitor element CN. And are connected. Here, since the charge of the capacitor CN is ideally held, CKN ′ is at a level of VDD + (Vr4−VSS). Therefore, the output terminal CK-N outputs a level of VDD + (Vr4-VSS) higher than the level of the power supply voltage VDD.

  As described above, the second level adjustment circuit 13b outputs the "L" level of the clock CK-N that controls the gate terminal of the NMOS transistor constituting the fourth switch unit SW4 at the level of the ground VSS. It has a function of outputting the H "level at a level higher than the level of the power supply voltage VDD. FIG. 10 is an example of the second level adjustment circuit, and the second level adjustment circuit may be configured by another circuit having the same function.

  The control clock generation circuit of the fourth switch unit SW4 in the control clock generator 11 shown in FIG. 7 includes only the first level adjustment circuit 13a, and only the level VG_P of the gate terminal of the PMOS transistor is grounded. The level VG_N of the gate terminal of the NMOS transistor may be a power supply voltage level. Alternatively, only the second level adjustment circuit 13b may be provided, the level VG_P of the gate terminal of the PMOS transistor may be set to the ground level, and only the level VG_N of the gate terminal of the NMOS transistor may be set higher than the power supply voltage level. Alternatively, both the first level adjustment circuit and the second level adjustment circuit are provided, the level VG_P of the gate terminal of the PMOS transistor is lower than the ground level, and the level VG_N of the gate terminal of the NMOS transistor is higher than the power supply voltage level. It is good to do.

  11 (a) and 11 (b) are diagrams showing control clock waveforms of the MOS transistors shown in FIGS. 10 (a) and 10 (b). As an example, the case where the level VG_P of the gate terminal of the PMOS transistor is lower than the ground level and the level VG_N of the gate terminal of the NMOS transistor is higher than the power supply voltage level is shown. As described above, when the potential of the analog output signal Vout approaches VG_P-Vth_P and VG_N-Vth_N, the on-resistance Rsw4 of the fourth switch unit SW4 increases rapidly.

  FIG. 12 is a graph showing changes in the on-resistance value Rsw4 of the MOS transistor constituting the switch SW4 connecting the capacitive element Cs and the output terminal Vout. Here, in this embodiment, by setting VG_P to a lower level and VG_N to a higher level than in the prior art, as shown in “a” and “c” shown in FIG. The point where the resistance value becomes high can be shifted outside the maximum amplitude range of the analog signal output Vout, and the fluctuation range of the on-resistance Rsw4 within the maximum amplitude range of the analog signal output Vout can be suppressed small.

FIG. 13 is an enlarged graph showing the transient characteristics of the output terminal Vout when the on-resistance value Rsw4 of the MOS transistor shown in FIG. 12 is the maximum value “a” and the minimum value “b”. Thereby, as shown in FIG. 13, the change depending on the ON resistance Rsw4 of the analog signal output Vout can be suppressed, and the occurrence of distortion can be suppressed.
That is, as is apparent from the curves La and Lb shown in FIG. 13, the length d1 generated between the curves La and Lb is the curves La and Lb of the digital-analog converter 100 shown in FIG. Shorter than the length d generated between the two. Therefore, the present embodiment can suppress the change in the transient characteristic of the analog output signal due to the change in the on-resistance value Rsw4 and suppress the occurrence of distortion.

In this embodiment, the integrating capacitive element 260 may not be provided between the output terminal and the inverting input terminal of the operational amplifier 12. In that case, the summing node switch 230 may be replaced with a resistor.
Thus, in the present embodiment, only the gate terminal of the fourth switch unit SW4 and the control clock generation circuit of the fourth switch unit SW4 inside the control clock generator 11 are set to a level lower than the ground level, or This is a method of operating at a level higher than the power supply voltage level, and operating the other circuits at the ground level or the power supply voltage level in the same manner as in the past, and distorts without adding a new switch or element to the signal transmission path. Can be prevented. Further, it is possible to prevent the distortion of the analog output signal from occurring without adversely affecting the response speed allowed in the digital / analog converter.

FIG. 14 is a circuit configuration diagram for explaining Example 2 of the digital-analog converter according to the present invention. In the figure, reference numeral 21 denotes a control clock generator, and 22 denotes an operational amplifier. In addition, the same code | symbol is attached | subjected to the component which has the same function as the component shown in FIG.
The digital / analog converter 300 (300A, 300B) according to the present invention is a digital / analog converter capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch.

The plurality of input terminals D1a to DNa and D1b to DNb are inputted with a plurality of bit signals constituting a digital signal, respectively. The plurality of sampling capacitor elements 350a and 350b (Csa and Csb) are provided corresponding to the plurality of input terminals D1a to DNa and D1b to DNb.
The plurality of first switch units 310a, 310b (SW1a, SW1b) are connected to one terminal of the plurality of sampling capacitor elements Csa, Csb and the plurality of input terminals D1a to DNa, D1b to DNb. Switch disconnection. The plurality of second switches 320a and 320b (SW2a and SW2b) switch connection and disconnection between the other terminals of the plurality of sampling capacitor elements Csa and Csb and the reference voltage sources Vr1a and Vr1b.

In the operational amplifier 22, reference voltage sources Vr1a and Vr1b are applied to the non-inverting input terminal (+) or the inverting input terminal (−).
The plurality of third switches 330a and 330b (SW3a and SW3b) are connected to the other terminals of the plurality of sampling capacitor elements Csa and Csb in accordance with disconnection and connection in switching the first switch units SW1a and SW1b. The connection and disconnection with the inverting input terminal (−) of the operational amplifier 22 and the connection and disconnection between the other terminal of the plurality of sampling capacitor elements Csa and Csb and one terminal of the integrating capacitor element Ci are switched.

  The plurality of fourth switch units 340a and 340b (SW4a and SW4b) are connected to and disconnected from one terminal of the plurality of sampling capacitor elements Csa and Csb and one of the plurality of sampling capacitor elements Csa and Csb. Are switched between connection and disconnection between the first terminal and the output terminal of the operational amplifier 22 and connection and disconnection between the plurality of sampling capacitor elements Csa and Csb and the other terminals of the plurality of integral capacitor elements Cia and Cib.

The control clock generator 21 also provides a clock for controlling the first switch units SW1a and SW1b, the second switches SW2a and SW2b, the third switches SW3a and SW3b, and the fourth switch units SW4a and SW4b. Occur.
For the two clocks CK-P and CK-N that control the PMOS transistor and NMOS transistor constituting the fourth switch units SW4a and SW4b, the potentials of the “L” level and “H” level are adjusted.

  As shown in FIG. 14, the digital-to-analog converter in the present embodiment is different from the above-described second embodiment in that the operational amplifier is a differential operational amplifier, and each of the two input terminals is connected to the first and second embodiments. The same charging voltage is input. Specifically, the inverting input terminal of the differential operational amplifier has the same configuration as that of the first embodiment (indicated by adding “a” to each symbol in FIG. 14) and displays the bit signal Dia constituting the digital input signal. Accordingly, the charging voltage of the sampling capacitor Csia is input, and the non-inverted analog output signal Vout + is output from the non-inverted output terminal of the differential operational amplifier. Further, the non-inverting input terminal of the differential operational amplifier also has the same configuration as that of the first embodiment (indicated by adding b to each symbol in FIG. 14), and according to the same bit signal Dib as the inverting input terminal side. The charging voltage of the sampling capacitor Csib is input, and the inverted analog output signal Vout− is output from the inverting output terminal of the differential operational amplifier.

In this way, by configuring a fully differential digital-to-analog converter, in-phase noise can be removed, and digital-to-analog conversion can be performed with higher accuracy.
In this embodiment, the control clock generation circuit of the fourth switch units SW4a and SW4b in the control clock generator 22 for generating a clock is provided with the first level adjustment as shown in FIG. A circuit and a second level adjustment circuit. The first level adjustment circuit adjusts the level VG_P of the PMOS gate terminal constituting the fourth switch units SW4a and SW4b in the second period of the present embodiment, that is, the “L” level of the control clock CK-P. The second level adjustment circuit is a level VG_N of the gate terminal of the NMOS transistor constituting the fourth switch units SW4a and SW4b in the second period of the present embodiment, that is, the control clock CK-N “H” "The circuit that adjusts the level.

  The first level adjustment circuit outputs the “H” level of the clock CK-P that controls the gate terminals of the PMOS transistors constituting the fourth switch units SW4a and SW4b at the level of the power supply voltage VDD, and the “L” level. May be constituted by a circuit as shown in FIG. 9 having a function of outputting at a level lower than the level of the ground VSS, or may be constituted by another circuit having a similar function.

  The second level adjustment circuit outputs the “L” level of the clock CK-N that controls the gate terminals of the NMOS transistors constituting the fourth switch units SW4a and SW4b at the level of the ground VSS, and sets the “L” level. The circuit shown in FIG. 10 having a function of outputting at a level higher than the level of the power supply voltage VDD may be used, or another circuit having a similar function may be used.

  The control clock generation circuit of the fourth switch units SW4a and SW4b inside the control clock generator 22 shown in FIG. 14 includes only the first level adjustment circuit, and only the level VG_P of the gate terminal of the PMOS transistor is provided. The level VG_N of the gate terminal of the NMOS transistor may be set to a power supply voltage level lower than the ground level. Alternatively, only the second level adjustment circuit may be provided, the level VG_P of the gate terminal of the PMOS transistor may be set to the ground level, and only the level VG_N of the gate terminal of the NMOS transistor may be set higher than the power supply voltage level. Alternatively, both the first level adjustment circuit and the second level adjustment circuit are provided, the level VG_P of the gate terminal of the PMOS transistor is lower than the ground level, and the level VG_N of the gate terminal of the NMOS transistor is higher than the power supply voltage level. It is good to do.

  In this example, by setting VG_P to a lower potential and VG_N to a higher voltage than in the prior art, the on-resistance value rapidly increases as indicated by “a” and “c” shown in FIG. It is possible to shift the higher point outside the maximum amplitude range of the analog signal output Vout, and to suppress the fluctuation range of the on-resistance Rsw4 within the maximum amplitude range of the analog signal output Vout. Thereby, the change depending on the on-resistance Rsw4 of the analog signal output Vout can be suppressed, and the occurrence of distortion can be suppressed.

  As described above, in this embodiment, only the gate terminals of the fourth switch units SW4a and SW4b and the control clock generation circuit of the fourth switch unit SW4 inside the control clock generator are set to a level lower than the ground level or the power supply. This is a method of operating at a level higher than the voltage level, and operating the other circuits at the ground level or the power supply voltage level in the same manner as in the past, and without adding a new switch or element to the signal transmission path, It is possible to prevent the occurrence. Further, it is possible to prevent the distortion of the analog output signal from occurring without adversely affecting the response speed allowed in the digital / analog converter.

1,11,21 control clock generator (first to fourth switch control clock generation circuit)
2, 12, 22 Operational amplifier 13a (LVLSFT1) CK-P "L" level adjustment circuit 13b (LVLSFT2) CK-N "H" level adjustment circuit 100, 200, 300A, 300B Digital / analog converters 110, 210 (SW1), 310a (SW1a), 310b (SW1b) First switch units 120, 220 (SW2), 320a (SW2a), 320b (SW2b) Second switches 130, 230 (SW3), 330a (SW3a), 330b ( SW3b) Third switches 140, 240 (SW4), 340a (SW4a), 340b (SW4b) Fourth switch units 151 to 15N, 151 to 25N, 351a to 35Na, 351b to 351b (Csi, Csia, Csib (i = 1) N) Sampling capacity 150, 250 (Cs), 350a (Csa), 350b (Csb) All sampling capacitance elements 160, 260 (Ci), 360a (Cia), 360b (Cib) Integration capacitance element Vr1 First reference voltage source Vr2 Second reference voltage Sources Di, Dia, Dib (i = 1 to N) Multiple bit signals (digital input signals)
Rsw3, Rsw3a, Rsw3b Synthetic on resistance Rsw4, Rsw4a, Rsw4b of the third switch Synthetic on resistance CK1 of the fourth switch CK1 First switch unit control clock signal CK2 Second switch control clock signal CK3 Third switch control clock signal CK4 Fourth switch Unit control clock signals Vout, Vout +, Vout- Analog output signal CK-P PMOS control clock signal CK-N constituting the fourth switch unit NMOS control clock signal VG_P CK-P constituting the fourth switch unit "L" “H” level “VG_N CK-N” level Vr3 Third reference voltage source Vr4 in LVLFTFT Fourth reference voltage source CP in LVSFT2 Capacitance element CN in LVLFTFT1 Capacitance element in CLVLSFT2

Claims (6)

A digital-to-analog converter capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch,
A sampling capacitor element portion composed of a plurality of sampling capacitor elements provided corresponding to a plurality of input terminals to which a plurality of bit signals constituting a digital signal are respectively input;
An operational amplifier connected to the sampling capacitor element;
A feedback switch unit composed of a plurality of complementary MOS transistors connectable between one end of the sampling capacitor element unit and an output terminal of the operational amplifier unit;
A summing node switch unit connectable between the other end of the sampling capacitor unit and an input terminal of the operational amplifier unit;
Transition between the first high voltage level and the first low voltage level lower than the first high voltage level at the gate terminal of the first MOS transistor of one conductivity type among the plurality of complementary MOS transistors. A first clock is supplied, and a second high voltage level and a second low voltage lower than the second high voltage level are applied to the gate terminal of the second MOS transistor having the other conductivity type than the first MOS transistor. A control clock generator for supplying a second clock that transitions between levels,
A digital-to-analog converter characterized in that at least the first high voltage level and the second low voltage level can be adjusted.   The digital analog according to claim 1, wherein the first high voltage level is at least higher than a power supply voltage level, and the second constant voltage level is at least lower than a ground level. converter. A digital-to-analog converter capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch,
A plurality of input terminals to which a plurality of bit signals constituting a digital signal are respectively input;
A sampling capacitor element portion comprising a plurality of sampling capacitor elements provided corresponding to the plurality of input terminals;
A first switch unit that switches connection and disconnection with the plurality of input terminals corresponding to one terminal of the sampling capacitor element;
A second switch that switches connection and disconnection between the other terminal of the sampling capacitor element unit and the first reference voltage source;
An operational amplifier in which the second reference voltage of the second reference voltage source is applied to the non-inverting input terminal;
According to disconnection and connection in switching of the first switch unit, connection and disconnection between the other terminal of the sampling capacitor element unit and an inverting input terminal of the operational amplifier, and the other terminal of the sampling capacitor element unit And a third switch for switching between connection and disconnection with one terminal of the integrating capacitance element;
Mutual connection and disconnection of the one terminal of the sampling capacitor element unit, connection and disconnection of the one terminal of the sampling capacitor element unit and the output terminal of the operational amplifier, and connection of the sampling capacitor element unit and the integral capacitor element A fourth switch unit that switches connection and disconnection with the other terminal;
A control clock generator for generating a clock for controlling the first switch unit, the second switch, the third switch, and the fourth switch unit;
A first level adjustment circuit that can adjust at least the first high voltage level, and a second level adjustment circuit that can adjust the second low voltage level, which constitutes the fourth switch unit;
A digital-to-analog converter characterized in that the potentials of "L" level and "H" level are adjusted for two clocks controlling the PMOS transistor and NMOS transistor constituting the fourth switch unit, respectively.   The clock level for controlling the gate terminals of the PMOS transistor and NMOS transistor constituting the fourth switch unit is such that only the clock level for controlling the gate terminal of the PMOS transistor is lower than the ground level, and the gate of the NMOS transistor is set. The clock potential for controlling the terminal is set to the power supply voltage level, the clock level for controlling the gate terminal of the PMOS transistor is set to the ground level, and only the clock level for controlling the gate terminal of the NMOS transistor is set higher than the power supply voltage level. The digital-to-analog converter according to claim 3.   The level of the clock for controlling the gate terminals of the PMOS transistor and NMOS transistor constituting the fourth switch unit is lower than the ground level for the clock for controlling the gate terminal of the PMOS transistor, and the gate of the NMOS transistor 4. The digital / analog converter according to claim 3, wherein a level of a clock for controlling the terminal is set higher than a power supply voltage level. A digital-to-analog converter capable of suppressing the occurrence of distortion of the analog output signal due to the on-resistance value of the switch,
A plurality of input terminals to which a plurality of bit signals constituting a digital signal are respectively input;
A plurality of sampling capacitor elements provided corresponding to the plurality of input terminals;
A plurality of first switch units for switching connection and disconnection with the plurality of input terminals corresponding to one terminal of the plurality of sampling capacitor elements;
A plurality of second switches for switching connection and disconnection between the other terminals of the plurality of sampling capacitor elements and a reference voltage source;
An operational amplifier in which the reference voltage source is applied to a non-inverting input terminal or an inverting input terminal;
According to disconnection and connection in switching of the first switch unit, connection and disconnection between the other terminal of the plurality of sampling capacitor elements and an inverting input terminal of the operational amplifier, and connection of the plurality of sampling capacitor elements A plurality of third switches for switching connection and disconnection between the other terminal and one terminal of the integrating capacitive element;
Mutual connection and disconnection of the one terminal of the plurality of sampling capacitor elements, connection and disconnection of the one terminal of the plurality of sampling capacitor elements and the output terminal of the operational amplifier, and the plurality of sampling capacitor elements A plurality of fourth switch units that switch connection and disconnection between the first and the other terminals of the plurality of integral capacitance elements;
A control clock generator for generating a clock for controlling the first switch unit, the second switch, the third switch, and the fourth switch unit;
A digital-to-analog converter characterized in that the potentials of "L" level and "H" level are adjusted for two clocks controlling the PMOS transistor and NMOS transistor constituting the fourth switch unit, respectively.

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