JP2014082664A - Digital-analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital-analog converter that suppresses a distortion in an analog output signal due to an on resistance value of a MOS transistor.SOLUTION: A switch drive circuit 403 includes: a second MOS transistor 401d for generating a reference current depending on a control voltage input into a gate terminal; a voltage holding circuit 401a, 401c for holding a voltage applied to a drain terminal of the second MOS transistor as a reference voltage; a first current source 401b for supplying a current having the same value as the reference current to the second MOS transistor; third MOS transistors 402a, 402b for generating a proportional current proportional to the current flowing through the first current source; and fourth MOS transistors 403a, 403b open-drain-connected to the respective third MOS transistors to be supplied with the proportional current.

Description

  The present invention relates to a digital-analog converter that converts a digital input signal into an analog output signal, and more particularly to a switched capacitor type digital-analog converter.

  Conventionally, a conversion error when a digital-analog converter converts a digital signal into an analog signal causes distortion in the output signal. Therefore, the characteristics of the device in which the digital-analog converter is mounted are deteriorated. There is a problem of inviting. In particular, in the field of audio equipment, signal distortion has a greater influence on the characteristics of the equipment than in other fields. For this reason, digital-analog converters mounted on audio equipment are required to perform digital-analog conversion with higher accuracy than other fields with respect to signal distortion.

FIG. 8 is a circuit configuration diagram for explaining a conventional digital-analog converter. An example of a conventional digital-analog converter is a switched capacitor circuit shown in FIG.
The digital-analog converter illustrated in FIG. 8 includes a sampling capacitor element unit 905 including N sampling capacitor elements 905 — i (i = 1 to N) and N charging the sampling capacitor elements 905 — i (i = 1 to N). A switch 901 and a switch 902 including switch units 901_i (i = 1 to N) are provided.

  The sampling capacitor element portion 905 is connected to the inverting input terminal 906a of the operational amplifier 906 via the switch 903. The output terminal 906c and the inverting input terminal 906a of the operational amplifier 906 are connected via an integration capacitor element 907. The output terminal 906c is connected between the switch 901 and the sampling capacitor element unit 905 to form a feedback path f. Such a feedback path f is a path provided to reduce distortion of the output signal in the digital-analog converter shown in FIG. In the configuration illustrated in FIG. 8, a switch 904 including N switch units 904 — i (i = 1 to N) is provided in the feedback path f.

Further, the switches 901, 902, 903, and 904 of the digital-analog converter shown in FIG. 8 perform an on / off operation (hereinafter also referred to as a switching operation) according to any one of the clock signals φ1 to φ3, CK_P, and CK_N. To do. The clock signals φ1 to φ3, CK_P, and CK_N are generated by the clock signal generation unit 910 and input to each switch.
According to the digital-analog converter shown in FIG. 8, the sampling capacitor 905_i (i = 1 to N) is charged according to the signal level of the input signal VDini (i = 1 to N) corresponding to the digital data, The operational amplifier 906 outputs an analog output signal VAout in accordance with the charging voltage of the sampling capacitor 905_i (i = 1 to N). As a switch of such a digital-analog converter, a MOS transistor is generally used.

FIG. 9 is a diagram for explaining the MOS transistor of the feedback switch included in the feedback switch unit shown in FIG. 8, and FIG. 10 is a clock signal (hereinafter referred to as a control clock) for controlling the MOS transistor shown in FIG. It is a figure for demonstrating.
The feedback switch 904 is configured by combining a P-type MOS transistor and an N-type MOS transistor. The control clock CK_P shown in FIG. 10 is a control clock for controlling the P-type MOS transistor. The control clock CK_N is a control clock for controlling the N-type MOS transistor.
When the control clock CK_P is Low (hereinafter referred to as L level) and the control clock CK_N is High (hereinafter referred to as H level), each unit 904_i (i = 1 to N) of the switch is turned on.

  FIG. 11 is a diagram for explaining a conventional switch driving circuit, and is a diagram illustrating a general example of a circuit that outputs control clocks CK_P and CK_N. A NOT gate 301 for inverting the input clock, a switch drive circuit 302, and a switch drive circuit 303 are included. Although not shown, the switch drive circuits 302 and 303 generally have a configuration in which two NOT gates are connected in series.

  Here, the combined on-resistance value of the switch 904_i (i = 1 to N) in which the MOS transistor is used is Rsw4, and the on-resistance value of the switch 903 is Rsw3. The analog output signal VAout output from the terminal 906c illustrated in FIG. 8 is a transient that depends on the time constant τ due to the sampling capacitor element 905, the integration capacitor 907, the switch 903, and the switch 904 being connected in series. Show properties. The time constant τ is expressed by the following formula (1).

    τ = (Rsw3 + Rsw4) × Ci × Cs / (Ci + Cs) (1)

  In the above formula (1), Ci is the capacitance of the integrating capacitor element 907, and Cs is the total capacitance of the sampling capacitor element portion 905. In Expression (1), the on-resistance value RSW3 of the switch unit 904 is not changed by the potential of the output terminal 906c. On the other hand, it is known that the on-resistance value RSW4 of the switch unit 904 changes depending on the potential of the output terminal 906c.

  Further, at the initial operation when the analog output signal VAout changes greatly, the control clock CK_P and the control clock CK_N for controlling the MOS transistor are not instantaneously at the H level or the L level, but are at the H level with a certain slope. Or it reaches L level. The state during which the control clock CK_P and the control clock CK_N reach the H level from the L level or the L level to the H level is referred to as a “transient state” in this specification. In the transient state of the control clock CK_P and the control clock CK_N, the characteristic of the combined resistance value Rsw4 also changes transiently and greatly affects the transient characteristic of the analog output signal VAout.

FIG. 12 is a diagram for explaining the relationship between the control clock and the analog output signal shown in FIG. 10, and is a diagram for explaining the relationship between the above-described control clocks CK_P and CK_N and the analog output signal VAout. The upper graph in FIG. 12 shows the transient characteristics of the analog output signal VAout output from the output terminal 906c shown in FIG. 1, where the horizontal axis indicates time and the vertical axis indicates the analog output signal VAout. Further, the lower diagram of FIG. 12 shows a control clock for controlling the MOS transistors constituting the switch unit 904 shown in FIG.
When the control clocks CK_P and CK_N are initially moved, their values change in a finite band with a certain slope. For this reason, the control clock CK_P and the control clock CK_N have a transient state period that does not reach the L level or the H level.

  FIG. 13 is a diagram for explaining a change in the combined resistance value of the P-type MOS transistor and the N-type MOS transistor during the transient period shown in FIG. 12, and during the transient period shown in FIG. It is a figure for demonstrating the change of synthetic | combination resistance value Rsw4 which synthesize | combined the ON resistance value of the P-type MOS transistor and N type MOS transistor which comprise the switch part 904 in the time a.

  The graph shown in the lower part of FIG. 13 is a graph showing that the value of the analog output signal VAout oscillates with a constant amplitude. The horizontal axis indicates the value of the analog output signal VAout, and the vertical axis indicates time. Is shown. The graph of Rsw4-1 shown in the upper part of FIG. 13 shows the combined resistance value Rsw4 when the analog output signal VAout varies as shown in the lower part of FIG. The horizontal axis of FIG. 13 indicates the analog output signal VAout, and the vertical axis indicates the combined resistance value Rsw4.

  FIG. 14 is a diagram showing the relationship between the analog output signal shown in FIG. 8 and time, and is a diagram showing the relationship between the analog output signal VAout and time. The vertical axis represents the analog output signal VAout, and the horizontal axis represents time. Curves La and Lb shown in FIG. 14 show the transient characteristics of the analog output signal VAout in an enlarged manner. A curve La in FIG. 14 shows the relationship between the analog output signal VAout and time when the on-resistance value Rsw4 of the switch unit SWu4 is indicated by the point a shown in FIG. A curve Lb shows the relationship between the analog output signal VAout and time when the on-resistance value Rsw4 of the switch unit SWu4 is indicated by the point b shown in FIG.

  As is apparent from the curves La and Lb shown in FIG. 14, the transient characteristics differ when the on-resistance values of the switches used in the digital-analog converter are different. The degree of the difference between the transient characteristics is represented by a length d generated between the curve La and the curve Lb. Further, the difference in the transient characteristic of the analog output signal VAout appears as deterioration of the distortion characteristic of the digital-analog converter.

  As shown in FIG. 13, the combined resistance value Rsw4-1 varies greatly according to the value of the analog output signal VAout. For this reason, at the initial operation when the analog output VAout changes greatly, the combined resistance value Rsw4 changes greatly according to the value of the analog output signal VAout, greatly affecting the transient characteristics of the analog output signal VAout, and the analog output signal VAout. Cause distortion characteristics deterioration.

Japanese Patent Laid-Open No. 11-055121 (Patent No. 3852721)

  However, since the switch driving circuit and the switch 904 as shown in FIG. 11 are circuits using MOS transistors, when the threshold voltage Vth of the MOS transistor varies due to process variation, the PMOS transistor constituting the switch unit 904 The relationship of the on-timing between the NMOS transistor and the NMOS transistor varies. As a result, the combined resistance value Rsw4 in the transitional state exhibits different characteristics depending on the process, as indicated by Rsw4-2 in FIG. Therefore, the difference in the transient characteristics of the analog output signal VAout as indicated by d in FIG. 14 varies depending on the process, and the distortion characteristics vary.

In this way, at the initial operation when the analog output signal VAout changes greatly, the combined resistance value Rsw4 exhibits different characteristics depending on the process variation. Therefore, the transient response characteristic of the analog output signal VAout varies depending on the process variation. It is difficult to obtain characteristics.
The present invention has been made in view of such problems, and the object of the present invention is to change the distortion characteristics of the analog output signal due to the change in the on-timing of the MOS transistor used for the switch due to the process change. It is an object of the present invention to provide a digital-analog converter that suppresses noise.

  The present invention has been made to achieve such an object. The invention according to claim 1 is a digital-analog converter in which the change timing of the analog signal output is determined by the on-timing of the switch. A switch driving circuit (403 in FIG. 3) for driving the gate terminals of the first MOS transistors (201 and 202 in FIG. 9) constituting the switch is provided, and the switch driving circuit (403 in FIG. 3) has a control voltage. , A second MOS transistor (401d) that generates a reference current corresponding to the control voltage input to the gate terminal, and a voltage applied to the drain terminal of the second MOS transistor (401d) Voltage holding circuits (401a, 401c) for holding the voltage as a reference voltage and the second MOS transistor (401d) A first current source (401b) for supplying a current having the same value as the reference current, and a plurality of second currents each generating a proportional current proportional to the current flowing through the first current source (401b). A plurality of third MOS transistors (402a, 402b,...) Functioning as current sources and the same conductivity type as the second MOS transistor (401d), and the third MOS transistors (402a, 402b) ,..., And a plurality of fourth MOS transistors (403a, 403b,...) That are open drain connected and receive the proportional current, and the fourth MOS transistors (403a, 403b). ,... Are a gate terminal connected to the source terminal of the fourth MOS transistor in the previous stage, and a gate terminal of the fourth MOS transistor in the subsequent stage. A source terminal connected in a multi-stage, and a clock signal is input to the gate terminal of the foremost fourth MOS transistor (403a), and the kth (k is an even number of 2 or more) fourth signal. A delay signal delayed for a predetermined time from the clock signal is output from the drain terminal of the first MOS transistor to the gate terminal of the first MOS transistor (401b). (Fig. 1, Fig. 3)

  According to a second aspect of the present invention, in the first aspect of the present invention, the voltage holding circuit (401a, 401c) has a drain terminal connected to the drain terminal of the second MOS transistor (401d). , A fifth MOS transistor (401c) whose source terminal is connected to the first current source, and a reference voltage is supplied to one input terminal, and the other input terminal is the fifth MOS transistor (401c). An amplifier (401a) connected to the drain terminal and having an output terminal connected to the gate terminal of the fifth MOS transistor (401c) is provided.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the first current source has the same conductivity type as the third MOS transistor (402a, 402b,...). When the sixth MOS transistor (401b) has a gate width W1, the third MOS transistor (402a, 402b,...) Is W1 / m. A current having a current value 1 / m times the reference current is generated (m is an integer constant of 2 or more), and the gate width of the first MOS transistor (201, 202) is set to W3. , The fourth MOS transistors (403a, 403b,...) Each have a gate width of W1 / n (n is an integer constant of 1 or more), and between m and n, that there is a relationship of m> n. And butterflies.

  According to a fourth aspect of the present invention, a sampling capacitor element (105) for sampling a signal input from the input terminal (108), and a signal sampled by the sampling capacitor element (105) are input. An operational amplifier (106) having an input terminal (106a), a summing node switch (103) for connecting and separating the sampling capacitor element portion (105) and the input terminal (106a) of the operational amplifier (106); A MOS transistor having a first polarity and a second polarity complementary to the first polarity, and between the sampling capacitor element portion (105) and the input terminal (106a), and the operational amplifier (106 ) And a feedback switch section (104) provided on a feedback path (f) connecting the output terminal (106c) of the A clock signal generation unit (110) for supplying a first clock signal and a second clock signal (CK, CKN) to the switch unit (104), wherein the clock signal generation unit (110) includes the first clock signal; And a switch drive circuit (403) according to any one of claims 1 to 3, which generates a second clock signal and drives at least one of the MOS transistors of the feedback switch section (104). And (Figure 1)

  According to a fifth aspect of the present invention, in the invention according to the fourth aspect, the operational amplifier (106) includes a first input terminal (606a) and a second input terminal (606b), It is a differential amplification type operational amplifier (606) having an output terminal (606cA) and a second output terminal (606cB), and the sampling capacitor element portion (105) is connected to the first input terminal (606a). A first sampling capacitor element portion (105A) to be connected and a second sampling capacitor element portion (105B) to be connected to the second input terminal (606b); and the summing node switch (103) A first summing node switch (1) that connects and disconnects one sampling capacitor element portion (105A) and the first input terminal (606a) of the differential amplification type operational amplifier (606); 3A) and a second summing node switch (103B) that connects and separates the second sampling capacitor element portion (105B) and the second input terminal (606b) of the differential amplification type operational amplifier (606). The feedback switch unit (104) includes a first sampling capacitor element unit (105A) and the first input terminal (606a), and the first output terminal (606cA). A first feedback switch unit (104A) provided on a feedback path connecting the second sampling capacitor element unit (105B) and the second input terminal (606b); And a second feedback switch unit (104B) provided on a feedback path connecting the output terminal (606cB). (Fig. 7)

ADVANTAGE OF THE INVENTION According to this invention, the digital-analog converter which suppresses the fluctuation | variation of the distortion characteristic of an analog output signal resulting from fluctuation | variation of the ON timing of the MOS transistor used for a switch by process fluctuation | variation can be provided.
That is, the analog signal output timing is determined by the ON timing of the MOS transistor. At this time, the transient characteristic of the analog output signal shows a transient characteristic depending on the on-resistance of the MOS transistor (for example, the switch 104 shown in FIG. 1) provided in the signal output path, and this affects the distortion characteristic. . In particular, at the initial operation when the analog output signal changes, the on-resistance greatly depends on the on-timing of the MOS transistor, so that the distortion characteristics are affected by the on-timing of the MOS transistor.

  However, according to the present invention, in the circuit for driving the gate terminal of the MOS transistor, the ON timing of the MOS transistor is controlled so as to depend only on the threshold voltage and the current amount of either the NMOS transistor or the PMOS transistor. Since a signal is output, there are few factors that affect the on-timing of the MOS transistor with respect to process variations, and the on-timing of the MOS transistor can be secured stably. Therefore, it is possible to provide a digital-analog converter in which the distortion characteristics hardly change with respect to process variations.

It is a circuit block diagram for demonstrating Example 1 of the digital-analog converter based on this invention. It is a figure which shows the waveform of the clock signal output from the clock signal generation part shown in FIG. It is a figure for demonstrating the switch drive circuit of Example 1 of this invention. It is a figure for demonstrating the example which produced | generated the control clock by the switch drive circuit shown in FIG. It is a figure for demonstrating the example which produced | generated the control clock by the switch drive circuit shown in FIG. It is a figure for demonstrating the example which produced | generated the control clock by the switch drive circuit shown in FIG. It is a circuit block diagram for demonstrating Example 2 of the digital-analog converter based on this invention. It is a circuit block diagram for demonstrating the conventional digital-analog converter. It is a figure for demonstrating the MOS transistor of the feedback switch contained in the feedback switch unit shown in FIG. It is a figure for demonstrating the clock signal which controls the MOS transistor shown in FIG. It is a figure for demonstrating the conventional switch drive circuit. It is a figure for demonstrating the relationship between the control clock shown in FIG. 10, and an analog output signal. It is a figure for demonstrating the change of the combined resistance value of a P-type MOS transistor and an N-type MOS transistor during the transient period shown in FIG. It is the figure which showed the relationship between the analog output signal shown in FIG. 8, and time.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining a first embodiment of a digital-analog converter according to the present invention. The digital-analog converter according to the first embodiment includes a sample hold circuit 100 and a clock signal generation unit 110 that generates a control clock input to a switch of the sample hold circuit 100.
The sample hold circuit 100 connects the sampling capacitor element unit 105, the operational amplifier 106 having an inverting input terminal 106a connected to one end of the sampling capacitor unit unit 105, and the sampling capacitor element unit 105 and the inverting input terminal 106a. The summing node switch 103 is separated, and the feedback switch section 104 is provided between the output terminal 106 c of the operational amplifier 106 and the other end of the sampling capacitor element section 105.

  The feedback switch unit 104 includes a plurality of feedback switches 104_i (i = 1 to N) connected in parallel to each other. In the first embodiment, each switch included in the feedback switch unit 104 includes a P-type MOS transistor and an N-type MOS transistor complementary to the P-type MOS transistor. The P-type MOS transistor and the N-type MOS transistor have the same configuration as the P-type MOS transistor 201 and the N-type MOS transistor 202 in the feedback switch unit 904 shown in FIG.

  Further, the sample hold circuit 100 according to the first embodiment includes an input terminal unit 108 to which an input signal VDini (i = 1 to N) corresponding to digital data is input, and the input terminal unit 108 includes N pieces of input terminal units 108. The input terminal 108_i (i = 1 to N) is provided. The input terminal 108 — i (i = 1 to N) corresponds to each of N-bit signals constituting the digital signal. Each of the sampling capacitor elements 105 — i (i = 1 to N) included in the sampling capacitor element unit 105 corresponds to one of the input terminals 108 — i (i = 1 to N).

The sampling capacitors 105 — i (i = 1 to N) may all have the same capacitance Cs (Cs = Cs1 = Cs2 =... = Cs3) or may have different capacitances. When each of the sampling capacitor elements 105_i (i = 1 to N) has a different capacity, the ratio of the capacitance Csi of each sampling capacitor element 105_i (1 ≦ i ≦ N) is equal to the binary ratio (2 ⁱ⁻¹ times). It may be made to become. When the capacitance of the sampling capacitor 105_i (i = 1 to N) has a binary ratio, the capacitance Csi of the sampling capacitor 105_i is expressed by the following equation (2).

Csi = 2 ⁱ⁻¹ · Cs (i−1) (2)

  Between the input terminal portion 108 and the sampling capacitor element portion 105, a switch 101 portion is provided. The switch unit 101 includes switches 101_i (i = 1 to N) connected to each of the input terminals 108_i (i = 1 to N) and each of the sampling capacitor elements 105_i (i = 1 to N). . In addition, the feedback switch 104_1 included in the feedback switch unit 104 is connected between the input terminal 108_1 and the sampling capacitor 105_1. The feedback switch 104_2 is connected between the input terminal 108_2 and the sampling capacitor 105_2, and the feedback switch 104_N is connected between the input terminal 108_N and the sampling capacitor 105_N. Therefore, the number of input terminals included in the input terminal unit 108, sampling capacitor elements included in the sampling capacitor element unit 105, and feedback switches included in the feedback switch unit 104 are all N.

  Further, an integration capacitor element 107 is connected between the inverting input terminal 106 a and the output terminal 106 c of the operational amplifier 106. A path between the output terminal 106c and the feedback switch unit 104 is referred to as a feedback path f. The non-inverting input terminal 106b of the operational amplifier is connected to a terminal of a power supply (not shown) that supplies the reference voltage Vr1. A terminal of the sampling capacitor 105_i (i = 1 to N) included in the sampling capacitor 105 that is not connected to the feedback switch 104 is connected to and separated from the reference voltage Vr2 via the switch 102. The reference voltage Vr1 and the reference voltage Vr2 may be the same or different.

As described above, FIG. 9 is a diagram for explaining, for example, a MOS transistor included in the feedback switch 104_1 among the feedback switches 104_i (i = 1 to N) included in the feedback switch unit 104 illustrated in FIG. It is. Note that the feedback switch 104_i (i = 1 to N) has the same configuration, and thus the description of the feedback switch 104_1 is replaced with the description of the other switches included in the feedback switch unit 104.
As illustrated, the feedback switch 104_1 includes a P-type MOS transistor 201 and an N-type MOS transistor 202. The source terminals or drain terminals of the P-type MOS transistor 201 and the N-type MOS transistor 202 are connected to the terminal 203, and the terminal 203 is connected to the output terminal 106c shown in FIG.

  The digital-analog converter according to the first embodiment includes the sample-and-hold circuit 100 and the clock signal generation unit 110 described above. The clock signal generation unit 110 generates clock signals φ5, φ6, φ7, CK_P, and CK_N and inputs them to the switch of the sample hold circuit 100. CK_P has a polarity opposite to that of CK_N. Each switch of the sample hold circuit 100 operates according to any of the input clock signals φ5, φ6, φ7, CK_P, and CK_N.

In the first embodiment, the clock signal φ5 is input to the switch 101_i (i = 1 to N) of the switch unit 101. The clock signal φ6 is supplied to the switch 102, and the clock signal φ7 is supplied to the summing node switch 103. Further, the clock signal φ8 is supplied to a feedback switch 104_i (i = 1 to N) included in the feedback switch unit 104.
2 is a diagram illustrating waveforms of clock signals output from the clock signal generation unit illustrated in FIG. 1, and illustrates waveforms of clock signals φ5, φ6, φ7, and CK_N output from the clock signal generation unit 110. is there. The vertical axis in FIG. 9 indicates whether the signal is at H level or L level, and the horizontal axis indicates time. While the clock signals φ5 and φ6 are at the H level, the switch 101_i (i = 1 to N) included in the switch unit 101 and the switch 102 are turned on. At this time, the sampling capacitor 105_i (i = 1 to N) included in the capacitor unit 105 is charged with a capacitor according to the level of the input signal VDini (i = 1 to N) corresponding to the digital data. Then, after the clock signals φ5 and φ6 are switched to L and the switches included in the switch unit 101 and the switch 102 are turned off, the clock signals φ7 and CK_N become H.

  When the clock signals φ7 and CK_N become H level, the feedback switch 104_i (i = 1 to N) included in the feedback switch unit 104 and the summing node switch 103 are turned on. At this time, the sampling capacitor 105_i (i = 1 to N) and the integrating capacitor 107 are connected in series. Further, the sampling capacitor 105_i (i = 1 to N) is connected to the output terminal 106c of the operational amplifier 106, and the potential of the output terminal 106c changes.

The clock signal generation unit 110 adjusts the ON / OFF timing (hereinafter also referred to as switch timing) of the P-type MOS transistor 201 and the N-type MOS transistor 202, and the P-type MOS transistor 201 and the N-type MOS transistor. A control clock output circuit 400 having a mechanism for suppressing the timing at which 202 is turned on from changing from a predetermined timing due to process variations is included.
Although not shown, the control clock output circuit 400 of the first embodiment replaces the switch drive circuit 303 of the switch drive circuit 300 shown in FIG. 11 with a switch drive circuit 403 as shown in FIG. The configuration is replaced with a switch drive circuit 402 (not shown).

  FIG. 3 is a diagram for explaining the switch drive circuit according to the first embodiment of the present invention. The switch drive circuit 403 shown in FIG. 3 includes M (M is a natural number) PMOS transistors and M NMOS transistors that form a pair of inverters. In the first embodiment, description will be made assuming that M = 2. In the first embodiment, an inverter constituted by an NMOS transistor and a PMOS transistor is referred to as a pull-up connection circuit.

In FIG. 3, the first to second PMOS transistors are denoted by reference numerals 402a to 402b, and the first to second NMOS transistors are denoted by reference numerals 403a and 403b. The NMOS transistor and the PMOS transistor described above are connected to the transistors with the same alphabetical characters to form a pull-up connection circuit. In the first embodiment, for example, a pull-up connection circuit including a PMOS transistor 402b and an NMOS transistor 403b is also referred to as a pull-up connection circuit b.
A connection between a pair of NMOS transistors and PMOS transistors included in one pull-up connection circuit is called an open drain connection. It is also possible to connect the NMOS transistor and the PMOS transistor by other methods without departing from the meaning of open drain connection.

  The switch drive circuit 403 includes an operational amplifier 401a, PMOS transistors 401b and 401c, and an NMOS transistor 401d. One of the two input terminals of the operational amplifier 401a receives a constant reference voltage VBG, and the other is connected to the drain terminal of the PMOS transistor 401b. The NMOS transistor 401d generates a current source current Is, and its gate terminal is connected to a voltage source that supplies a reference voltage VDD.

  The output terminal of the operational amplifier 401a is connected to the gate terminal of the PMOS transistor 401c to form a feedback loop in which the drain voltage of the NMOS transistor 401d serving as a constant current source is equal to the reference voltage VBG. A current of the same current value Is as that of the NMOS transistor 401d flows through the PMOS transistor 401b serving as a current source according to Kirchhoff's current law.

  The PMOS transistors 402a and 402b connected to the PMOS transistor 401b in a current mirror manner operate as current sources for flowing a current of (1 / k) Is, ignoring the secondary effect due to the drain voltage. Note that k is a positive constant. The drain terminals of the PMOS transistors 402a and 402b are pulled up to the drain nodes of the NMOS transistors 403a and 403b.

  In the NMOS transistors 403a and 403b, the clock signal φ8 is input to the gate of the first stage NMOS transistor 403a. The drain node of the NMOS transistor 403a is connected to the gate terminal of the subsequent NMOS transistor 403b. Further, the drain node of the NMOS transistor 403 b is connected to the gate terminal of the NMOS transistor 202 that constitutes the feedback switch unit 104.

  From the NMOS transistor 403a, a delay amount depending on the threshold value and current amount of the NMOS transistor is added to the clock signal φ8, and the inverted delay clock φ8a is added to the clock signal φ8. A delay clock CK_N to which a delay amount depending on the threshold value of the NMOS transistor and the amount of current is added is output. The delay clocks φ8a and CK_N are collectively referred to as a delay clock group.

The size of each illustrated transistor is designed as follows.
Wn: gate width of NMOS transistor 401d Ln: gate length of NMOS transistors 401d, 403a, 403b, 202 Wp: gate width of PMOS transistors 401b, 401c Lp: gate length of PMOS transistors 401b, 401c, 402a, 402b Wn (1 / n): Gate width of the gate length of the NMOS transistors 403a and 403b Wp (1 / m): Gate width of the PMOS transistors 402a and 402b where m is a positive constant of 2 or more and n is a positive constant of 1 or more. In this case, m and n have a relationship of m> n. Vnth means the threshold value of the NMOS transistors 401d, 403a, 403b, and 202, and Vpth shows the threshold value of the PMOS transistors 401b, 401c, 402a, and 402b.

That is, when the gate width of the MOS transistor 401b is W1, the MOS transistors 402a, 402b,... Each have a gate width of W1 / m and generate a current having a current value 1 / m times the reference current. (Where m is an integer constant of 2 or more), and when the gate width of the MOS transistors 201 and 202 is W3, the MOS transistors 403a, 403b,... Each have a gate width of W1 / n (n is There is a relationship of m> n between m and n.
Further, the switch drive circuit 403 seems to have changed the MOS transistor size appropriately by replacing the PMOS transistor with the NMOS transistor, the NMOS transistor with the PMOS transistor, replacing VDD with VSS = 0V, and VSS = 0V with VDD in FIG. It has become a structure.

  Next, the operation of the digital-analog converter having the above-described configuration will be described below. The operations of the sample and hold circuit and the digital-analog converter according to the first embodiment are classified into a first period and a second period. Note that the first period and the second period are alternately repeated periodically. Such a digital-analog converter of the first embodiment is an integral type digital-analog converter.

Hereinafter, operations of the sample hold circuit and the digital-analog converter will be described for each of the first period and the second period.
(1) First Period In the first period, the switch 101_i (i = 1 to N) and the switch 102 of the switch unit 101 illustrated in FIG. 1 are turned on. At this time, the sampling capacitor 105_i (i = 1 to N) is in accordance with the level (voltage Vref ⁺ or voltage Vref ⁻ ) of the bit signal input from the corresponding input terminal 108_i (i = 1 to N). The battery is charged up to the reference voltage Vr1.

(2) Second Period In the second period, the switch unit 101 and the switch 102 are disconnected, and the feedback switch 104_i (i = 1 to N) and the summing node switch 103 are connected. At this time, the analog output signal VAout changes based on the charging voltage of the sampling capacitor 105_i (i = 1 to N).

  In the second period, the feedback switch unit 104, the summing node switch 103, and the sampling capacitor 105_i (i = 1 to N) are connected in series to form a closed loop. The closed loop time constant τ is expressed by the following equation (3).

    τ = (Rsw3 + Rsw4) × Ci × Cs / (Ci + Cs) (3)

  In Equation (3), the on-resistance value of the summing node switch 103 is Rsw3, and the combined resistance value of the MOS transistors of the feedback switch 104_i (i = 1 to N) included in the feedback switch unit 104 is Rsw4. The analog output signal VAout exhibits a transient characteristic depending on the time constant of the closed loop.

  Here, the combined resistance value Rsw4 of the MOS transistors of the feedback switch 104_i (i = 1 to N) and the on-resistance value of the summing node switch 103 will be described in more detail. The MOS transistor constituting the feedback switch 104_i (i = 1 to N) has an on-resistance value that changes in accordance with a voltage change between the gate terminal that is the control terminal and the source terminal or the drain terminal that is the main terminal. Such a characteristic is called voltage dependency of the on-resistance value.

  In the second period, when the feedback switch 104_i (i = 1 to N) is connected, the potential of the source terminal and the drain terminal of the MOS transistor constituting the feedback switch 104_i (i = 1 to N) is the output terminal 106c. And the same potential. Therefore, in the second period, the on-resistance value of the feedback switch unit 104 varies depending on the potential of the analog output signal VAout due to the voltage dependence of the on-resistance value. On the other hand, in the second period, the on-resistance value of the summing node switch 103 is a constant value because the source terminal and the drain terminal of the MOS transistor are not changed by the analog output signal VAout.

The time constant τ of the closed loop formed in the second period is expressed by Expression (3). Therefore, the time constant τ changes as the combined resistance value Rsw4 changes depending on the potential of the analog output signal VAout.
The transient characteristic of the analog output signal VAout changes depending on the value of the analog output signal VAout. The analog output signal VAout leads to signal distortion. In particular, at the initial operation of the digital-analog converter in which the analog output signal VAout changes greatly, the control clock for controlling the feedback switch unit 104 changes in a finite band. For this reason, the transient characteristic of the analog output signal VAout largely depends on the combined resistance value Rsw4 until the feedback switch 104_i (i = 1 to N) of the feedback switch unit 104 is completely turned on. For this reason, the on-resistance value Rsw4 until the feedback switch 104_i (i = 1 to N) is completely turned on greatly contributes to the distortion of the analog output signal VAout.

  In the first embodiment, as described above, the circuit 400 that outputs the control clocks CK_P and CK_N for controlling the feedback switch unit 104 is configured to use the switch drive circuit as shown in FIG. The characteristic of the combined resistance value Rsw4 until (i = 1 to N) is completely turned on can be made difficult to change due to process variations. According to the first embodiment, it is possible to suppress the distortion characteristics generated in the analog output signal VAout from changing due to process variations.

Next, the operation of the switch drive circuit shown in FIG. 3 will be described below.
For simplicity of explanation, it is assumed that the NMOS transistors 403a and 403b are turned on when a gate voltage higher than Vnth is applied and the drain potential is higher than 0 and a constant current Is (1 / n) flows. Further, when the gate voltage is lower than Vnth, it is turned off and no current flows. On the other hand, when the drain potential is lower than VDD, the PMOS transistors 402a and 402b are turned on to pass a constant current Is (1 / m). When the drain potential is VDD, it is in an off state and no current flows.
Here, since the NMOS transistor 401d operates in the triode region, the following equation is established.

Is = Vds · μn · Cox · (Wn / Ln) · (VDD−Vnth)
... Formula (4)

  In equation (4), μn represents the electron mobility, and Vds represents the drain node voltage of the NMOS transistor 401d. Further, Vds = VBG (= constant) is fixed by a feedback loop formed by the operational amplifier 401a and the PMOS transistor 401c.

  FIGS. 4A and 4B are diagrams for explaining an example in which a control clock is generated by the switch drive circuit shown in FIG. 3, and among the switch drive circuits shown in FIG. It is a figure for demonstrating the change of the gate voltage of the included NMOS transistor. 4A shows the gate voltage of the pull-up connection circuit b constituted by the PMOS transistor 402b and the NMOS transistor 403b, and FIG. 4B shows the change of the gate voltage of the NMOS transistor 202.

  The switch drive circuit 403 receives the clock signal φ8. Assuming that the drive capability of the clock signal φ8 is sufficiently high, the gate voltage Vφ8 of the NMOS transistor 403a immediately changes from 0 V to VDD and is turned on. At this time, the output of the pull-up connection circuit a is input to the gate of the NMOS transistor 403b, and the gate voltage of the NMOS transistor 403b becomes Vφ8a. The change in the gate voltage Vφ8a is expressed by the following equation. The time t is set so that t = 0 when the clock signal φ8 rises.

    Vφ8a = VDD−∫ [{(1 / n) − (1 / m)} · Vds · μn · Cox · (Wn / Ln) · (VDD−Vnth) · (n / Cox · Ln · Wn)] dt · ..Formula (5)

  If the initial condition is Vφ8a = VDD at t = 0, equation (5) becomes equation (6).

Vφ8a = VDD− {1- (n / m)} · Vds · μn · Ln− ² · (VDD−Vnth) · t (6)

  In the equation (6), when the time when Vφ8a = Vnth is T1, T1 is expressed by the following equation (7).

T1 = [{1- (n / m)} · Vds · μn · Ln ⁻² ] ⁻¹ ∝Ln ²
... Formula (7)

From equation (7), the time T1 when the gate voltage of the NMOS transistor 403b becomes equal to or lower than Vnth is made constant by sufficiently increasing Ln of the NMOS transistors 401d, 403a, and 403b and sufficiently reducing the process variation. It can be seen that it is possible. That is, the pull-up connection circuit a composed of the NMOS transistor 403a and the PMOS transistor 402a outputs a falling edge in which a constant delay amount T1 is added to the subsequent stage with respect to the rising edge of the input clock signal φ8. . When the falling edge is input, the NMOS transistor 403b is turned off.
Further, the gate voltage of the NMOS transistor 202 is set to VCK_N. The change in the voltage VCK_N is expressed by the following equation (8) when the rising edge of CLK is t = 0.

    VCK_N = ∫ {(1 / m) · Vds · μn · Cox · (Wn / Ln) · (VDD−Vnth) · (n / Cox · Ln · Wn)} dt (8)

  In equation (8), if n is sufficiently smaller than m, the initial value condition is VCK_N = 0 at t = T1, so VCK_N can be obtained by the following equation.

VCK_N = (n / m) .Vds..mu.n.Ln- ^2. (VDD-Vnth). (T-T1) (9)

  When the time when VCK_N = Vnth is T1 + T2,

T2 = (m · Ln ² · Vnth) / {(n · Vds · μn) · (VDD−Vnth)} (10)

  Further, the following equation is obtained from the equations (4) and (10).

    T2 = (m / n) · (Ln · Vnth / Is) (11)

  By the expression (11), the time T2 when the gate voltage of the NMOS transistor 202 becomes equal to or higher than the Vnth is obtained by making the Ln of the NMOS transistors 401d and 403a, 403b, 202 sufficiently large and sufficiently reducing the process variation to Vnth / It turns out that it becomes a linear function of Is. Here, from Equation (4), Is monotonously decreases with increasing Vnth and monotonically increases with decreasing Vnth, so that Vnth / Is monotonically increases with increasing Vnth and decreases Vnth. On the other hand, it decreases monotonously.

  That is, T2 monotonously increases with increasing Vnth and monotonically decreases with decreasing Vnth. For this reason, the pull-up connection circuit b composed of the NMOS transistor 403b and the PMOS transistor 402b monotonously increases with an increase in Vnth and monotonously decreases with a decrease in Vnth with respect to the input falling edge. The rising edge to which the amount T2 is added is output to the subsequent pull-up connection circuit. In the delay clock CK_N, a rising edge to which a delay amount (T1 + T2) that monotonously increases with increasing Vnth and monotonously decreases with decreasing Vnth appears with respect to the rising edge of the clock signal φ8. Thus, at t = T1 + T2, the NMOS transistor 202 is turned on.

FIGS. 5A and 5B are diagrams for explaining an example in which the control clock is generated by the switch driving circuit shown in FIG. 3, and the PMOS transistor has a Vpth ′ lower than the Vpth shown in FIG. It is a figure for demonstrating the change of the gate voltage in having. As in FIG. 4, FIG. 5A shows the pull-up connection circuit b, and FIG. 5B shows the gate voltage change for the NMOS transistor 202.
As shown in FIG. 5B, the delay amount T2 of the switch drive circuit is determined only by the timing at which the NMOS transistor is turned on. For this reason, as shown in the equation (10), the delay amount T2 becomes a constant value without depending on the decrease in Vpth.

FIGS. 6A and 6B are diagrams for explaining an example in which the control clock is generated by the switch driving circuit shown in FIG. 3, in which the NMOS transistor has Vnth ′ lower than Vnth shown in FIG. It is a figure for demonstrating the change of the gate voltage in having. Similar to FIG. 4, FIG. 6A shows the pull-up connection circuit b, and FIG. 6B shows the gate voltage change for the NMOS transistor 202.
As shown in FIG. 6B and Expression (11), the delay amount T2 ′ of the switch drive circuit increases with the increase of Vnth (T2 ′> T2). In the timing chart of FIG. 4, it is a timing chart when the Vnth is large. From equation (11), as shown in FIG. 6, T2 increases as Vnth increases to T2 ′ (T2 ′> T2).

As described above, in the switch drive circuit 403, the rising edge of the delay clock signal CK_N is delayed by T1 + T2 with respect to the rising edge of the input clock signal φ8, and the delay amount is only the threshold value and current amount of the NMOS transistor. Therefore, it becomes possible to secure a more stable delay amount against process variations.
In the first embodiment, an example in which two stages of pull-up connection circuits each including an NMOS transistor and a PMOS transistor are provided has been described. However, the present invention is not limited to such a configuration, and an arbitrary number of pull-up connection circuits are provided. A circuit can be provided.

  In addition, the switch drive circuit 402 in the switch drive circuit 403 replaces the PMOS transistor with an NMOS transistor, replaces the NMOS transistor with a PMOS transistor, replaces VDD with VSS = 0V, replaces VSS = 0V with VDD, and appropriately changes the MOS transistor size. This is a switch drive circuit that depends only on the threshold value and current amount of the PMOS transistor. Since the operation principle is the same as that of the switch drive circuit 403, description thereof will be omitted.

  As described above, the on-timing of the NMOS transistor 202 constituting the feedback switch unit 104 depends only on the threshold value and the current amount of the NMOS transistor, and the on-timing of the PMOS transistor 201 constituting the feedback switch unit 104 is the PMOS transistor. Therefore, it is possible to secure a more stable delay relationship with respect to process variations. Therefore, since it is possible to suppress the combined on-resistance Rsw4 from changing depending on the process variation in the transient state until the feedback switch unit 104 is completely turned on, the signal distortion of the analog output signal VAout varies due to the process variation. Can be suppressed.

  As described above, the first embodiment can suppress the signal distortion of the analog output signal VAout from fluctuating due to the process variation only by adjusting the clock generation circuit input to the sample hold circuit 100. For this reason, it is not necessary to add an element such as a switch or a new signal path to a signal path sensitive to characteristics in the existing digital-analog converter.

  FIG. 7 is a circuit configuration diagram for explaining a digital-analog converter according to a second embodiment of the present invention. In the digital-analog converter of the second embodiment, a differential operational amplifier 606 is used in place of the operational amplifier 106 shown in FIG. The differential operational amplifier 606 is provided with an inverting input terminal 606a and a non-inverting input terminal 606b, and an inverting output terminal 606cA and a non-inverting output terminal 606cB. Note that, in the configuration illustrated in FIG. 7, configurations similar to the configurations illustrated in FIG. 1 are denoted by the same reference numerals, and description thereof is partially omitted.

The digital-analog converter according to the second embodiment has a configuration in which circuits 600A and 600B obtained by removing the operational amplifier 106 from the sample and hold circuit 100 shown in FIG.
That is, the circuit 600A includes a switch part 101A, a feedback switch part 104A, a sampling capacitor element part 105A, a summing node switch 103A, a switch 102A, and an integral capacitor element 107A. The circuit 600B includes a switch unit 101B, a feedback switch unit 104B, a sampling capacitor element unit 105B, a summing node switch 103B, a switch 102B, and an integration capacitor element 107B. The subscript “A” attached to the configuration included in the circuit 600A and the subscript “B” attached to the configuration included in the circuit 600B are added only to distinguish the circuit 600A from the circuit 600B. Yes, the configurations having the same reference numerals other than the subscript “A” and the subscript “B” are the same.

In the digital-analog converter according to the second embodiment, a charging voltage is input to the sampling capacitor elements 105_1 to 105_N of the sampling capacitor elements 105A and 105B in accordance with the bit signal constituting the digital input signal. The non-inverted analog output signal VAout ⁺ is also output from the non-inverted output terminal 606b of the differential operational amplifier 606. The charging voltage corresponding to the same bit signal as that of the inverting input terminal 606a is also input to the non-inverting input terminal 606b of the differential operational amplifier 606. From the inverting output terminal 606cA of the differential operational amplifier 606, the inverted analog output signal VAout ^- is output.

  In the second embodiment, the effects obtained by the first embodiment described above can be obtained. In addition, by configuring a fully differential digital-analog converter in this way, in-phase noise can be removed and digital-analog conversion can be performed with higher accuracy.

  The present invention is suitable for a digital-analog converter in which the change timing of the analog signal output is determined by the ON timing of the MOS transistor. For example, in a switched capacitor filter type digital-analog converter and a current output type digital-analog converter, the output timing of an analog signal is determined by the ON timing of a MOS transistor, and the timing affects the characteristics. Therefore, it is necessary to ensure a predetermined on timing with respect to process variations.

100 Sample hold circuit 101, 101A, 101B Switch part 101_1-101_N Switch 102, 102A, 102B Switch 103, 103A, 103B Summing node switch 104, 104A, 104B Feedback switch part 104_1-104_N Feedback switch 105, 105A, 105B Sampling capacitance element Unit 105_1 to 105_N sampling capacitor element 106 operational amplifier 106a, 606a inverting input terminal 106b, 606b non-inverting input terminal 106c output terminal 107, 107A, 107B integrating capacitor element 108 input terminal unit 108_1 to 108_N input terminal 110 clock signal generation unit 606cA inversion Output terminal 606cB Non-inverting output terminal 201 PMOS transistor 202 NMOS transistor 203 Terminal 30 0, 400 Clock output circuit 301 NOT gate 302, 303, 403 Switch drive circuit 401a Operational amplifier 401d, 403a, 403b NMOS transistor 401b, 401c, 402a, 402b PMOS transistor 606 Differential operational amplifier

Claims (5)

In a digital-to-analog converter in which the change timing of the analog signal output is determined by the ON timing of the switch
A switch driving circuit for driving the gate terminal of the first MOS transistor constituting the switch;
The switch driving circuit includes:
A gate terminal to which a control voltage is input; a second MOS transistor that generates a reference current according to the control voltage input to the gate terminal;
A voltage holding circuit for holding a voltage applied to a drain terminal of the second MOS transistor as a reference voltage;
A first current source for supplying a current having the same value as the reference current to the second MOS transistor;
A plurality of third MOS transistors functioning as a plurality of second current sources each generating a proportional current proportional to a current flowing through the first current source;
A plurality of fourth MOS transistors having the same conductivity type as the second MOS transistors, each of the third MOS transistors being connected to each other by an open drain and receiving the proportional current;
The fourth MOS transistor is
A gate terminal connected to the source terminal of the fourth MOS transistor in the previous stage and a source terminal connected to the gate terminal of the fourth MOS transistor in the subsequent stage are connected in multiple stages,
A clock signal is input to the gate terminal of the foremost fourth MOS transistor, and a delay that is delayed for a predetermined time from the clock signal from the drain terminal of the fourth MOS transistor of the kth (k is an even number of 2 or more). A digital-analog converter characterized in that a signal is output to the gate terminal of the first MOS transistor. The voltage holding circuit is
A fifth MOS transistor having a drain terminal connected to the drain terminal of the second MOS transistor and a source terminal connected to the first current source;
An amplifier in which a reference voltage is supplied to one input terminal, the other input terminal is connected to a drain terminal of the fifth MOS transistor, and an output terminal is connected to the gate terminal of the fifth MOS transistor. The digital-analog converter according to claim 1. The first current source includes a sixth MOS transistor having the same conductivity type as the third MOS transistor;
When the gate width of the sixth MOS transistor is W1, each of the third MOS transistors has a gate width of W1 / m and generates a current having a current value 1 / m times the reference current. m is an integer constant greater than or equal to 2, and when the gate width of the first MOS transistor is W3, each of the fourth MOS transistors has a gate width of W1 / n (n is an integer greater than or equal to 1). 3. The digital-analog converter according to claim 1, wherein there is a relationship of m> n between m and n. A sampling capacitor element for sampling a signal input from the input terminal;
An operational amplifier having an input terminal to which a signal sampled by the sampling capacitor element unit is input;
A summing node switch for connecting and separating the sampling capacitor element unit and the input terminal of the operational amplifier;
A MOS transistor having a first polarity and a second polarity complementary to the first polarity, and connecting between the sampling capacitor element section and the input terminal and an output terminal of the operational amplifier A feedback switch provided on the feedback path;
A clock signal generator for supplying a first clock signal and a second clock signal to the feedback switch;
4. The switch drive circuit according to claim 1, wherein the clock signal generation unit generates the first clock signal and the second clock signal, and drives at least one of the MOS transistors of the feedback switch unit. 5. A digital-analog converter characterized by comprising: The operational amplifier is a differential amplification type operational amplifier having a first input terminal and a second input terminal, a first output terminal and a second output terminal,
The sampling capacitor element unit includes a first sampling capacitor element unit connected to the first input terminal and a second sampling capacitor element unit connected to the second input terminal,
The summing node switch includes a first summing node switch that connects and separates the first sampling capacitor element unit and the first input terminal of the differential amplification type operational amplifier, and the second sampling capacitor element unit. And a second summing node switch for connecting and separating the second input terminal of the differential amplification type operational amplifier,
The feedback switch unit includes a first feedback switch unit provided on a feedback path connecting the first sampling capacitor element unit and the first input terminal and the first output terminal; And a second feedback switch section provided on a feedback path connecting the second sampling capacitor element section and the second input terminal and the second output terminal. The digital-analog converter according to claim 4.

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