JP3310796B2 - Boost circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit device, and more particularly to a booster circuit device capable of achieving low-voltage boosting with high efficiency and excellent boosting characteristics, such as a semiconductor integrated circuit (IC). The present invention relates to a booster circuit device suitable for use in a power supply.

[0002]

2. Description of the Related Art In recent years, equipment using a battery as a drive source,
As the demand for so-called battery-powered devices has increased, the power supply voltage of semiconductor integrated circuits has also been increased from 0.9 to 1.8.
There is an increasing movement to set the voltage to a low voltage of about V. When such a low voltage is used as a power supply, a relatively high operating voltage is supplied to a required circuit portion, for example, a circuit for reducing the ON resistance of a MOS transistor or a circuit portion for improving a level transfer characteristic. For this reason, a booster circuit device that boosts a low voltage of a power supply to a required voltage has been used.

FIG. 10 is a circuit configuration diagram showing an example of the configuration of such a known booster circuit device. For example, FIG. 10 is a diagram showing the configuration of "1993 IEEE Custom Integra.
rated Circuit Conf "pp. 25.
4.1-pp. This is shown in 25.4.4. FIG. 11 is a voltage waveform diagram showing an operation state of each part of the known booster circuit device.

In FIG. 10, reference numeral 81 denotes a first boosting capacitor; 82, a second boosting capacitor; 83, a first power supply N-channel MOS transistor;
A power supply N-channel MOS transistor 85; a diode-connected first charge transfer N-channel MOS transistor 85;
Transistor 86 is also a diode connected second
N-channel MOS transistor for charge transfer, 87 for an N-channel MOS transistor for voltage clamping, 88 for a voltage generating circuit, 89 for a load capacitor representing an equivalent load capacitance, 90 for a boosted clock signal input terminal, and 91 for an inverted boosted clock signal An input terminal, 92 is a first voltage output terminal, 9
3 is a second voltage output terminal, 94 is a power supply voltage supply terminal, 9
5 is a common voltage output terminal, and 96 is a load side output terminal.

The first boosting capacitor 81 is
Step-up clock signal input terminal 90 and first voltage output terminal 9
2, the second boosting capacitor 82 is connected between the inverted boosted clock signal input terminal 91 and the second voltage output terminal 93, respectively. The first power supply N-channel MOS transistor 83 is connected between the power supply voltage supply terminal 94 and the first voltage output terminal 92, and the second power supply N-channel MOS transistor 84 is connected to the power supply voltage supply terminal 9.
4 and the second voltage output terminal 93. The first charge transfer N-channel MOS transistor 85 is connected between the first voltage output terminal 92 and the common voltage output terminal 95, and the second charge transfer N-channel MOS transistor 86 is connected to the second voltage output terminal. 93 and a common voltage output terminal 95 respectively. The voltage-clamping N-channel MOS transistor 87 is connected to a common voltage output terminal 95 and a load-side output terminal 96, and the voltage generation circuit 88 is connected to the gate of the voltage-clamping N-channel MOS transistor 87. The load capacitor 89 is connected between the load output terminal 96 and the ground.

The operation of the booster circuit device having the above configuration will be described with reference to FIG.

First, on the first boosting capacitor 81 side, at time t0, the boosted clock signal (CK) is at a low level, that is, at the ground level (L), the inverted boosted clock signal (CKN) is at a high level, That is, the power supply voltage level (H)
Then, the first boosting capacitor 81 is precharged by the supply voltage (Vcc) of the power supply voltage supply terminal 94 supplied through the first power supply N-channel MOS transistor 83. This precharge is performed at time t1.
And the voltage on the first voltage output terminal 92 side of the first boosting capacitor 81 becomes a voltage equal to (Vcc-Vthn) (in this case, Vthn is the threshold voltage of the N-channel MOS transistor). . Then, at time t1,
When the boosted clock signal (CK) goes high (H) and the inverted boosted clock signal (CKN) goes low (L),
Since the voltage on the boost clock signal input terminal 90 side of the first boost capacitor 81 has risen from the ground voltage to the power supply voltage (Vcc), the first voltage output terminal 92 side of the first boost capacitor 81 also has the same voltage. It rises by an amount equal to the power supply voltage (Vcc), and its voltage value is ideally (Vcc-Vt).
hn + Vcc) = (2Vcc-Vthn), but in reality, there are various wiring capacitances and parasitic capacitances such as inter-electrode capacitances of the first power supply N-channel MOS transistor 83. The boost level is stabilized at a voltage value slightly lower than the voltage value (2Vcc-Vthn).

On the other hand, on the second boosting capacitor 82 side, at time t0, when the boosted clock signal (CK) goes low (L) and the inverted boosted clock signal (CKN) goes high (H), For the same reason as described for the first boosting capacitor 81 side, the voltage value of the second boosting capacitor 82 on the second voltage output terminal 93 side is
The value is slightly lower than (2Vcc-Vthn). Subsequently, at time t1, when the boosted clock signal (CK) goes high (H) and the inverted boosted clock signal (CKN) goes low (L), the inverted boosted clock signal input terminal of the second boosting capacitor 82. The voltage on the 91 side is the power supply voltage (Vc
c) to the ground voltage, the second voltage output terminal 93 side of the second boosting capacitor 82 also drops by the same amount as the power supply voltage (Vcc), so that its voltage value becomes (2Vcc). −Vthn−Vcc) = (V
cc-Vthn).

The above description is based on the step-up clock signal (CK)
And the operation in the first cycle of the change in the inverted boosted clock signal (CKN), and in the next cycle in the subsequent change in the boosted clock signal (CK) and the inverted boosted clock signal (CKN). Also, on the first boosting capacitor 81 side and the second boosting capacitor 82 side, the same operation as that in the first cycle described above is performed, and further, in each cycle after the next one cycle. Also, on the first boosting capacitor 81 side and the second boosting capacitor 82 side, the same operation as the operation in the first cycle described above is performed.

Then, the voltage obtained at the first voltage output terminal 92 and the voltage obtained at the second voltage output terminal 93 are:
The voltages are transmitted to a common voltage output terminal 95 via a first charge transfer N-channel MOS transistor 85 and a second charge transfer N-channel MOS transistor 86, respectively. First
And second charge transfer N-channel MOS transistor 8
5 and 86, the voltage value Vo is gradually increased by the charge pumping action. The voltage value Vo finally boosted depends on the capacity (CL) of the load capacitor 89 and the first boost capacitor 8.
1 (or second boost capacitor 82)
It is determined by the ratio with (C2) and is represented by the following equation.

Vo = Vcc-2Vthn + ｛C1 / (C
1 + CL)｝ Vcc Further, the voltage value of the load side output terminal 96 is connected to the voltage clamping N-channel MOS transistor 87 provided between the common voltage output terminal 95 and the load side output terminal 96 and its gate. If the output voltage of the voltage generation circuit 88 is set to VB by the voltage generation circuit 88, (VB−Vth
n) can be suppressed to a value having the upper limit.

[0012]

In the known booster circuit device, the precharge voltage obtained by the first and second boosting capacitors 81 and 82 is smaller than the power supply voltage (Vcc) by the N-channel MOS transistor. Threshold voltage (Vth
n), and becomes a voltage (Vcc-Vthn) lower by the amount corresponding to the common voltage output terminal 9 during the operation of the charge pump.
5 also becomes lower by the threshold voltage (Vthn) of the N-channel MOS transistor, so that the charge transfer amount (charge packet) to the common voltage output terminal 95 during the operation of the charge pump is reduced. However, there is a problem that the boosting efficiency and the boosted voltage level of the boosting circuit device must be reduced.

Generally, in order to increase the boosting efficiency of the booster circuit device, first and second boosting capacitors 81,
It is known that the capacity (C1, C2) of the capacitor 82 may be designed to be sufficiently larger than the capacity (CL) of the load capacitor 89. First and second boost capacitors 81 and 82
Occupied by the first and second boosting capacitors 81 and 82 is increased, and the overall size is increased.

Further, the known booster circuit device uses a voltage generating circuit 88 for generating the output voltage VB in order to limit the voltage value generated at the load-side output terminal 96 from rising above a certain value. Since the voltage generating circuit 88 cannot be operated with a low-voltage power supply, there is a problem that a power supply that generates a relatively high voltage is separately required.

An object of the present invention is to solve all of the above problems, and an object of the present invention is to increase the boosting efficiency and boosting voltage level and to make the whole compact.
An object of the present invention is to provide a booster circuit device capable of boosting a low voltage of 1.8 V or less with high efficiency.

[0016]

In order to achieve the above object, a booster circuit device according to the present invention comprises a first booster capacitive element connected between a booster clock signal input terminal and a first voltage output terminal. A second boost capacitor connected between the inverted boost clock signal input terminal and the second voltage output terminal;
The first P-channel MOS transistor for switching, power supply voltage supply terminal and the second switching P-channel connected between a second voltage output terminal the power supply voltage supply terminal and connected between the first voltage output terminal A MOS transistor, connected between a boosted clock signal input terminal and a gate electrode of a first switching P-channel MOS transistor, and connected to the first switching P-channel MOS transistor in response to the boosted clock signal;
A first gate drive circuit for turning on / off the P-channel MOS transistor, connected between an inverted boosted clock signal input terminal and a gate electrode of a second switching P-channel MOS transistor, and responsive to the inverted boosted clock signal; A second for turning on / off the second switching P-channel MOS transistor switch in a state opposite to the on / off state of the first switching P-channel MOS transistor;
Gate drive circuit, a first voltage output terminal and a second voltage
Voltage transmission circuit connected between the voltage output terminal and the load side output terminal.
And a road, the power supply voltage of the first gate driving circuit supplying the first voltage output terminal, the power supply of the second gate drive circuit
A voltage transmitting circuit for supplying a voltage from a second voltage output terminal;
Are the third and fourth switching P-channel MOS transistors.
A third switching P-channel M including a transistor
The gate of the OS transistor is connected to the first voltage output terminal,
4 switching P-channel MOS transistor
Ports are respectively connected to the second voltage output terminals, and the third and
And fourth switching P-channel MOS transistor
Has first means connected to the load-side output terminal .

In order to achieve the above object, a booster circuit device according to the present invention includes a booster capacitor connected between a booster clock signal input terminal and a voltage output terminal, and a booster capacitor connected between a power supply voltage supply terminal and a voltage output terminal. First switch connected to
Switching P-channel MOS transistor, boosted clock signal input terminal, and first switching P-channel MOS transistor
A gate drive circuit connected between the gate electrodes of the transistors for turning on / off the first P-channel MOS transistor in response to a boosted clock signal ; a voltage output terminal and a load
And a voltage transmission circuit connected between the side output terminal and
Supply the power supply voltage of the gate drive circuit from the voltage output terminal,
A voltage transmission circuit is connected between the voltage output terminal and the load side output terminal. The voltage transmission circuit includes a level shift circuit in which the power supply voltage is supplied from the load side output terminal, a drain connected to the voltage output terminal, a source and a substrate. Are connected to the output terminal on the load side, and the gate is connected to one output terminal of the level shift circuit.
It is composed of the switching P-channel MOS transistor, precharging - the di period output a high level
During the boosting period, the low level is set to the second switching P-channel.
Second means for supplying to the channel MOS transistor is provided.

Further, in order to achieve the above object, a booster circuit device according to the present invention is provided with a booster clock signal, a first signal at a first output terminal, and a first signal at a second output terminal .
A control logic circuit for outputting a second signal having a phase opposite to that of the control logic circuit, a boosting capacitor connected between the first output terminal and the voltage output terminal of the control logic circuit, and a connection between the voltage output terminal and the power supply voltage supply terminal And a first switching depletion-type N channel having a gate connected to the second output terminal of the control logic circuit.
And Le MOS transistor, the second switching N-channel MO which is connected to the voltage output terminal across the load side output terminal
An S transistor, disposed between a voltage output terminal and ground,
Complementary M whose input is connected to the second output terminal of the control logic circuit
And an OS transistor inverter stage.
Third means are provided in which the output of the OS transistor inverter stage is connected to the gate of the second switching N-channel MOS transistor.

[0019]

According to the first means, a boost clock signal is input.
A first step-up capacitor between the input terminal and the first voltage output terminal
Are connected to an inverted boosted clock signal input terminal and a second voltage output terminal.
A second boost capacitor is connected between the power supply voltage supply terminal and the second
1st power supply voltage supply (switch
MOS transistor is connected to the power supply terminal and the
2 for supplying a second power supply voltage between the voltage output terminals
MOS transistor for boosting clock signal input
Terminal and the gate of the first power supply voltage supply MOS transistor.
Between the first power supply voltage supply MO
First gate driving circuit for supplying the gate of the S transistor
Path, inverted boosted clock signal input terminal and second power supply voltage
Inverting boost clock between gates of supply MOS transistors
Clock signal of the second power supply voltage supply MOS transistor.
Connect the second gate drive circuit to be supplied to the gate
And a power supply for the first and second gate drive circuits.
Voltage from the first and second voltage output terminals, respectively.
The boost clock supplied to the first boost capacitive element.
(The first voltage output terminal rises)
Supply of the first power supply voltage
MOS transistor becomes non-conductive and the first voltage output
The power terminal is isolated from the supply voltage supply terminal and a second
Rise of boost clock signal supplied to boost capacitor
Timing (time when the second voltage output terminal is boosted)
The second power supply voltage supply MOS transistor
The transistor becomes non-conductive, and the second voltage output terminal is connected to the power supply voltage.
It is isolated from the supply terminal. In addition, the first and second voltage outputs
First and second p-channels between a power terminal and a load-side output terminal
MOS transistors are connected, and the first and second p-channels are connected.
The gates of the MOS transistors are connected to the second and first
It is driven by the voltage of the voltage output terminal. this
Therefore, an excellent power supply that does not cause a voltage drop unlike a diode
Pressure switch operation, boosting boosting speed and boosting level
And the boosted clock signal (C
K) or the inverted boosted clock signal (CKN)
Also has the function of executing boost operation.
And any p-channel MOS transistor
Since there is no voltage drop, the output voltage boosting efficiency is high.
With the excellent function of increasing the boost speed
I have.

According to the second means, the boosting clock signal
Between the input terminal and the voltage output terminal.
For supplying power supply voltage between the voltage supply terminal and the voltage output terminal (switch
MOS transistor for boosting clock signal
Gate of input terminal and power supply voltage supply MOS transistor
In the meantime, the boosted clock signal is
The gate drive circuits to be supplied to the gates of the
Output the power supply voltage of this gate drive circuit.
Since it is obtained from the terminal, it is
Rising timing of the supplied boost clock signal,
That is, in accordance with the timing when the voltage output terminal is boosted,
The power supply voltage supply MOS transistor becomes non-conductive,
Voltage output terminal is isolated from the power supply terminal.
Between the voltage output terminal and the load side output terminal.
Voltage transfer circuit consisting of S transistor and level shift circuit
Circuit, so that the load side output terminal
Compared to the boosted voltage of the MOS transistor.
Pressure can be supplied. In other words, voltage loss during boost
Voltage level transmission without
It is possible to prevent the charge stored in the capacitor from being sent backward.

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

Next, in the third means, a boosting capacitor is provided between the first output of the control logic circuit to which the boosted clock signal is input and the voltage output terminal, and a boosting capacitor is provided between the voltage output terminal and the power supply voltage supply terminal. , The gate is the second of the control logic circuit
A first depletion-mode MOS transistor for supplying (switching) the power supply voltage connected to the output of the power supply, and a second depletion-mode MOS transistor switch for charge transfer between the voltage output terminal and the load-side output terminal. A complementary MOS transistor inverter stage whose input is connected to the second output of the control logic circuit is connected between the terminal and the ground, and the output of the complementary MOS transistor inverter stage is connected to a second charge transfer depletion type MOS transistor. Connected to the gate of the
The power supply voltage depletion type MOS transistor is turned on, the second charge transfer depletion type MOS transistor is turned off, and the voltage output terminal rises to the power supply voltage. The first depletion-mode MOS transistor for supplying power supply voltage is turned off, the second depletion-mode MOS transistor for charge transfer is turned on, and the voltage of the voltage output terminal is boosted and transmitted to the load-side output terminal by the charge pump operation. Is done.

As described above, according to the third means, in addition to enjoying the action obtained by the first means, the complementary M
The adoption of the OS transistor inverter stage has the advantage that the booster circuit device can be made compact.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a state before a booster circuit device according to the present invention.
FIG. 2 is a circuit diagram showing a basic configuration example to be proposed . FIG. 2 is a voltage waveform diagram showing an operation state of each unit in the basic configuration example shown in FIG.

In FIG. 1, 1 is a boosting capacitor, 2
Is a P-channel MOS for power supply (switching)
Transistor, 3 is a P-channel MOS transistor for charge transfer, 4 is a load capacitor representing equivalent load capacitance, 5 is a 2-input NAND gate, 6 is a CMOS inverter circuit, 7
Is a CMOS inverter circuit, and 8 is a boosted clock signal (C
L) Input terminal, 9 is a voltage output terminal, 10 is a load side output terminal, 11 is a power supply voltage supply terminal, 12 is a power supply voltage clamp circuit composed of three N-channel MOS transistors, 1
Reference numeral 3 denotes a boost clock signal (CL) supply line, and reference numeral 14 denotes an enable signal (ENB) supply line.

The boosting capacitor 1 has one end connected to the voltage output terminal 9, the other end connected to the output of the inverter circuit 7, and the input of the inverter circuit 7 connected to the boosted clock signal input terminal 8. The power supply voltage supply P-channel MOS transistor 2 has a source connected to the power supply voltage supply terminal 11, a drain and a base connected to the voltage output terminal 9, a gate connected to the output of the CMOS inverter circuit 6, and an input of the CMOS inverter circuit 6 connected to the input. Connected to boost clock signal input terminal 8. In the CMOS inverter circuit 6, a voltage generated at the voltage output terminal 9 is used as a power supply. P-channel MOS transistor 3 for charge transfer
Is a diode connection in which the source is connected to the voltage output terminal 9 and the drain, gate and base are connected to the load side output terminal 10, respectively. The load capacitor 4 has one end connected to the load-side output terminal 10 and the other end connected to a ground point. The two-input NAND gate 5 has one input connected to the boost clock signal supply line 13, the other input connected to the enable signal supply line 14, and the output connected to the boost clock signal input terminal 8. The power supply voltage clamp circuit 12 is connected between the power supply voltage supply terminal 11 and the voltage output terminal 9.

The operation of the basic configuration example according to the above configuration is shown in FIG.
Will be described together.

When the enable signal (ENB) is at a low level (L) before time t0, the output of the 2-input NAND gate 5, that is, the boosted clock signal, regardless of the logic state of the boosted clock signal (CL). The supply terminal 8 is fixed at a high level (H), and the CMOS inverter circuit 6
And the output of the inverter circuit 7 is both low level (L)
Is in a precharged state fixed to. In this precharge state, the power supply voltage supply P-channel MOS
Since both transistor 2 and charge transfer P-channel MOS transistor 3 are on, voltage output terminal 9
Is supplied with a power supply voltage (Vcc) via a power supply voltage supply P-channel MOS transistor 2, and a load side output terminal 10 is connected to a charge transfer P-channel MOS transistor 3
(Vcc-Vthp) is supplied via the.
Here, Vthp is the threshold voltage of the P-channel MOS transistor.

Next, at time t0, when the enable signal (ENB) is changed to the high level (H), the boosted clock signal (CL) is supplied to the boosted clock signal input terminal 8 via the 2-input NAND gate 5. It will be transmitted. However, during the period from time t0 to t1, the boosted clock signal (CL) is in the low level (L) state (section A), so that the precharge state is continued, and the voltage of the voltage output terminal 9 is changed to the power supply voltage. The voltage of the load side output terminal 10 is equal to the voltage (Vcc-Vth).
p).

Subsequently, during a period from time t1 to time t2, the boosted clock signal (CL) is in a high level (H) state (section B) and enters a boosted state. In this step-up state, the output of the CMOS inverter circuit 6 is at a high level (H; the step-up level of the voltage output terminal 9), and the power supply voltage supply P-channel MOS transistor 2 is turned off. The output is high level (H;
(High power supply voltage Vcc level).
Is transmitted to the voltage output terminal 9 through the boost capacitor 1, the voltage output terminal 9 is electrically isolated from the power supply voltage (Vcc) and reaches a voltage value (V0) higher than the power supply voltage (Vcc). It is boosted. The boosted voltage obtained at the voltage output terminal 9 is transferred to the load side output terminal 10 via the charge transfer P-channel MOS transistor 3 in the ON state, and the voltage value of the load side output terminal 10 is changed to (V0 -Vthp).

The series of operations performed during the period from time t0 to time t2, that is, the period including the section A and the section B, represents one cycle of the boosting operation in the booster circuit device. When one cycle of the first boosting operation is completed, the process proceeds to one cycle of the next boosting operation.

That is, at time t2, one cycle of the next step-up operation is started. First, during the period from time t2 to t3, the step-up clock signal (CL) goes low (L) and However, at this time, the voltage of the voltage output terminal 9 becomes equal to the power supply voltage (Vcc) since the power supply voltage supply P-channel MOS transistor 2 is turned on.

Thereafter, during the period from time t3 to time t4, the boosted clock signal (CL) goes high (H) and enters the boosted state again. At this time, the power supply voltage supply P-channel MOS transistor 2 is activated. The voltage output terminal 9 is turned off and the voltage output terminal 9 is slightly higher than the voltage value (V0) by the charge transfer by the boosting capacitor 1.
1), and the voltage value of this voltage output terminal 9 (V
1) is transferred to the load-side output terminal 10 via the charge transfer P-channel MOS transistor 3, and the load-side output terminal 1
0 is raised to (V1−Vthp) and the time t
When it reaches 4, one cycle of the next boost operation ends.

Hereinafter, similarly, the cycle of the boosting operation is sequentially repeated, and in each cycle of the boosting operation, the voltage of the load-side output terminal 10 is sequentially boosted by the charge pump operation. In this case, assuming that the voltage generated at the load-side output terminal 10 after the boosting operation cycle is performed n times is Vo (n), Vo (n) becomes

[0041]

(Equation 1)

Is as follows. Here, | Vthp |
This is the forward voltage drop (threshold voltage) of the diode-connected charge transfer P-channel MOS transistor 3, and the forward voltage drop of the P-channel MOS transistor is usually about 0.6V.

In the basic configuration example , the substrate of the charge transfer P-channel MOS transistor 3 is connected to the load-side output terminal 10 commonly to the gate and the source, but the power supply voltage (Vcc) is supplied to the substrate. If the substrate voltage is fixed, the boosted voltage of the load-side output terminal 10 passes through the PN junction of the charge transfer P-channel MOS transistor 3 during the precharge state, and the power supply voltage (V
cc) or to avoid a short circuit with the voltage of the voltage output terminal 9. For example, if the substrate is connected as described above,
Even if the load output terminal 10 becomes higher than the voltage output terminal 9, the voltage of the load output terminal 10 and the substrate voltage (N-well potential) are short-circuited through the PN junction of the charge transfer P-channel MOS transistor 3. It is not done.

Further, in the basic configuration example , a voltage clamp circuit 12 composed of three P-channel MOS transistors connected in series is arranged between the voltage output terminal 9 and the power supply terminal 11. This voltage clamp circuit 12
Means that the voltage at the voltage output terminal 9 is (3 | Vthp | + Vc
c) When rising above these three P-channel MOs
Both the gate-source voltage of the S transistor is (| V
thp |) or more, and the ON state is prevented, thereby preventing the voltage of the voltage output terminal 9 from becoming excessively large. In this case, the P-channel M connected in series
Assuming that the number of OS transistors is n, the voltage of the voltage output terminal 9 is substantially clamped to (Vcc + n | Vthp |) .

FIG. 3 is a circuit diagram showing the configuration of a first embodiment of the booster circuit device according to the present invention, and FIG.
FIG. 4 is a voltage waveform diagram showing an operation state of each unit in the first embodiment shown in FIG.

In FIG. 3, reference numeral 15 denotes a control logic circuit;
Is a voltage transfer circuit, 17 is a P-channel MOS transistor for charge transfer, 18 is a level shift circuit, 19 is an N-channel MOS transistor for reset, 20 is an N-channel depletion type MOS transistor for power supply voltage clamp, and 21 and 22 are 2-input NAND gates. , 23, 24 are inverter circuits, 25 is a NOR gate, 26, 27, 28,
29 is a P-channel MOS transistor, and 30 and 31 are N
Channel MOS transistor, 32 is an inverter circuit,
33 and 34 are two-phase non-superimposed boosted clock signals (VFA, V
CK2) supply line, 35 is an enable signal (VS3) supply line, and other components that are the same as those shown in FIG. 1 are denoted by the same reference numerals.

The control logic circuit 15 includes two two-input NAND gates 21 and 22 and two inverter circuits 2
3 and 24, and one NOR gate 25, and has first to third inputs 15 _{N1 to} 15 _N3 and first to fourth outputs 15 _{O1 to} 15 _O4 . First and second inputs 1
5 _N1 and 15 _N2 are two-phase non-superimposed boost clock signal supply lines 3
3, 34, the third input 15 _N3 is connected to the enable signal supply line 35, respectively. The first output 15 _O1 is connected to one end of the boost capacitor 1, the second output 15 _O2 is connected to the input of the CMOS inverter circuit 6, the third output 15 _O3 is connected to the input of the level shift circuit 18, and the fourth output 15 _{O15 O4} is connected to the gate of the reset N-channel MOS transistor 19, respectively. Voltage transmission circuit 16 includes a P-channel MOS transistor 17 and a level shift circuit 18.
The level shift circuit 18 includes four P-channel MOS transistors 26 to 29, two N-channel MOS transistors 30 to 31, and one inverter circuit 32. The charge transfer P-channel MOS transistor 17 has a drain connected to the voltage output terminal 9, a gate connected to one output of the level shift circuit 18, a source and a base connected to the power supply and the load side output terminal 10 of the level shift circuit 18, respectively. You. The reset N-channel MOS transistor 19 is connected between the load side output terminal 10 and the ground, and is connected to the power supply voltage clamping N-channel depletion type M
The OS transistor 20 has a drain connected to the power supply terminal 11.
The gate is connected to the ground point, and the source is connected to the source of the power supply voltage supply P-channel MOS transistor 2.

The operation of the booster circuit device according to the first embodiment having the above configuration will be described with reference to FIG.

Now, before the time t0, when the two-phase non-superimposed boosted clock signals (VSK2, VFA) and the enable signal (VS3) are both at the low level (L), the control logic circuit 15 outputs the first and second signals. The output 15 _{O1 of} 2,
15 _O2 is low (L), the third and fourth outputs 1
5 _O3 and 15 _O4 are at a high level (H), which is a boost stop period.

During the boost stop period, the low level (L) of the second output 15 _O2 of the control logic circuit 15 is inverted by the CMOS inverter circuit 6 to a high level (H), and this high level (H) ) Is applied to the gate of the power supply voltage supply P-channel MOS transistor 2, and the power supply voltage supply P-channel MOS transistor 2 is turned off. When the high level (H) of the third output ₁₅₀₃ of the control logic circuit 15 is supplied to the input of the level shift circuit 18, the P-channel M
The OS transistor 28 is turned off, the N-channel MOS transistor 30 is turned on, the output of the inverter 32 goes low (L), and the P-channel MOS transistor 29
Is on, and the N-channel MOS transistor 31 is off. Further, the low level (L) generated at the connection point between the P-channel MOS transistor 28 and the N-channel MOS transistor 30 causes the P-channel MOS transistor 17
And the P-channel MOS transistor 27 is turned on,
P channel MOS transistor 29 and N channel MOS
The high level (H) generated at the connection point of the transistor 31 turns off the P-channel MOS transistor 26. At the same time, the high level (H) of the fourth output 15 _O4 of the control logic circuit 15 is applied to the gate of the reset N-channel MOS transistor 19, and the reset N-channel MOS
When the transistor 19 is turned on, the load-side output terminal 10
To ground voltage. At this time, as described above, the power supply voltage supply P-channel MOS transistor 2 is turned off and the charge transfer P-channel MOS transistor 17 is turned on.
The voltage output terminal 9 is also at the ground voltage.

Next, when the time comes close to time t0 and the enable signal (VS3) goes high (H), the two-input NAND gate 21 and the two-input NOR gate 2 of the control logic circuit 15
5 both enter a through state in which the boosted clock signal (VFA) passes, and enter a boosting operation period.

In this boosting operation period, first, during the period from time t0 to t1, the two-phase non-superimposed boosted clock signals (VSK2, VFA) are set to a high level (H) state with a slight phase shift (section A). . At this time, the high level (H) of the second output 15 _O2 of the control logic circuit 15 is set to CM.
The signal is inverted by the OS inverter circuit 6 to a low level (L), and this low level (L) is applied to the power supply voltage supply P channel M
The voltage is applied to the gate of the OS transistor 2, and the power supply voltage supply P-channel MOS transistor 2 is turned on. At the same time, the low level (L) of the first output 15 _O1 of the control logic circuit 15 is applied to the boosting capacitor 1, and this low level (L) is transferred to the voltage output terminal 9 side. 9 is a clamp voltage set by an N-channel depletion type MOS transistor 20 for power supply voltage clamp |
VthD |.

Since the gate electrode of the power supply voltage clamping N-channel depletion type MOS transistor 20 is grounded, the output voltage obtained at the output side of the N-channel depletion type MOS transistor 20 is the N-channel depletion type MOS transistor. 2
When the threshold voltage of 0 is VthD (<0), | V
thD | is generated. That is, the voltage between the gate and source electrodes of the N-channel depletion type MOS transistor 20 is Vgs, and the clamp voltage of the N-channel depletion type MOS transistor 20 is V _CLP.
Then, when the output voltage rises to | VthD | or more, Vgs−VthD = −V _CLP −VthD (<
0) is satisfied and the N-channel depletion type MO
S transistor 20 is turned off, and power supply from voltage source Vcc is blocked by N channel depletion type MOS transistor 20.

Next, the time t1 which is also the boosting operation period
During the period from t2 to t2, the two-phase non-superimposed boosted clock signals (VSK2, VFA) enter a low level (L) state with a slight phase shift (section B). At this time, the low level (L) of the second output 15 _O2 of the control logic circuit 15 is set to CMO.
It is inverted by the S inverter circuit 6 to become a high level (H), and this high level (H) is applied to the power supply voltage supply P channel M
The voltage is applied to the gate of the OS transistor 2, and the power supply voltage supply P-channel MOS transistor 2 is turned off. At the same time, the high level (H) of the first output 15 _O1 of the control logic circuit 15 is applied to the boosting capacitor 1, and this high level (H) is transferred to the voltage output terminal 9 side, and the voltage output terminal 9 becomes high. Level (H), that is, the power supply voltage (Vcc) level. When the power supply voltage supply P-channel MOS transistor 2 is turned off, the voltage output terminal 9 is isolated from the voltage supply terminal 11 so that the power supply voltage (Vcc) is maintained. ) Maintained at the level.

In the first embodiment, the series of operations performed during the period from time t0 to time t2, that is, the period including the section A and the section B is one cycle of the boosting operation in the booster circuit device. When one cycle of the first boosting operation is completed, the process shifts to one cycle of the next boosting operation, and in one cycle of the next boosting operation and one cycle of the subsequent boosting operation, as described above. An operation similar to one cycle of the first boosting operation is performed .

Next, the charge pump operation performed by voltage transmission circuit 16 will be described.

In the boosting operation period, the enable signal (VS3) is at the high level (H), and the low level (L) of the fourth output 15 _O4 of the control logic circuit 15 is at the reset N-channel MOS transistor. Since the voltage is applied to the gate of the transistor 19, the reset N-channel MOS transistor 19 is turned off, and a boosted voltage is obtained at the load-side output terminal 10.

First, in one cycle of a certain boosting operation, two-phase non-superimposed boosted clock signals (VSK2, VF
When A) is at the high level (H) (section A), the voltage output terminal 9 is precharged to the clamp voltage | VthD | as described above. In this state, the control logic circuit 1
5, the low level (L) of the third output 15 _O3 is supplied to the input of the level shift circuit 18.
Becomes an operation state completely opposite to the operation state during the boost stop period described above. That is, in response to the input low level (L), in the level shift circuit 18, the P-channel MOS transistor 28 is turned on, the N-channel MOS transistor 30 is turned off, and the inverter 32
Becomes high level (H), P-channel MOS transistor 29 is turned off, and N-channel MOS transistor 31 is turned on. Further, the low level (L) generated at the connection point between the P-channel MOS transistor 29 and the N-channel MOS transistor 31 turns on the P-channel MOS transistor 26. And a P-channel MOS
Transistor 26 and P-channel MOS transistor 2
8, the boosted voltage of the load side output terminal 10 becomes P
The P-channel MOS transistor 17 is supplied to the gate of the P-channel MOS transistor 17 through a connection point between the channel MOS transistor 28 and the N-channel MOS transistor 30 to turn off the P-channel MOS transistor 17 for charge transfer.

Next, in one cycle of the boosting operation,
When the two-phase non-superimposed boosted clock signal (VSK2, VFA) is at a low level (L) (section B), as described above,
Voltage output terminal 9 is set to the power supply voltage (Vcc) level. In this state, the third output 1 of the control logic circuit 15
When the high level (H) of 5 _O3 is supplied to the input of the level shift circuit 18, the level shift circuit 18 is in the same operation state as the already-described boost stop period.
The charge transfer P-channel MOS transistor 17 is turned on, and the voltage level (charge) of the voltage output terminal 9 is transmitted to the load-side output terminal 10 without a voltage drop.

As described above, in the voltage transmission circuit 16, the charge pump operation is performed by repeating the operation cycle of the section A and the section B, and a required boosted voltage is derived to the load-side output terminal 10. In this case, assuming that the capacity of the boosting capacitor 1 is C1 and the equivalent load capacity of the load capacitor 4 is CL, the boosted voltage Vo (n) of the load-side output terminal 10 in the nth cycle is represented by the following equation.

[0061]

(Equation 2)

As described above, according to the first embodiment, the provision of the voltage transmission circuit 16 makes it possible to smoothly transmit and block the voltage during the precharge and boost operations, and furthermore, , P-channel MOS transistor 17 is turned on, its gate-source voltage (V
gs) above the power supply voltage (Vcc) level, there is no voltage drop in the charge transfer P-channel MOS transistor 17, and both the boosting efficiency and the boosting level in the boosting circuit device are increased. Can be.

Further, according to the first embodiment, an N-channel depletion type MO which is a power clamp circuit is provided.
Since the S transistor 20 is used, the threshold voltage (VthD) for determining the clamp voltage can be controlled and managed relatively easily, and at the same time, there is an advantage that the size can be reduced.

Further, according to the first embodiment, since the booster circuit device is operated with the clamp voltage instead of the power supply voltage (Vcc), the boosted voltage can be naturally limited, and the power consumption can be reduced. Can be reduced.

In the first embodiment, the first embodiment is described between the power supply terminal 11 and the output voltage terminal 9 without using the N-channel depletion type MOS transistor 20 as the power clamp circuit. A clamp circuit 12 may be provided.

In addition, the configurations of the power supply clamp circuit and the level shift circuit 18 used in the first embodiment are as follows.
It is needless to say that the power supply clamp circuit and the level shift circuit are not limited to those shown in the drawings, and other functionally equivalent power supply clamp circuits and level shift circuits can be used.

FIG. 5 is a circuit diagram showing the configuration of a second embodiment of the booster circuit device according to the present invention. FIG. 6 shows the operation state of each part in the second embodiment shown in FIG. It is a voltage waveform diagram shown.

In FIG. 5, 1 'is a second boosting capacitor, and 2' is a second power supply voltage (for switching).
P-channel MOS transistor, 4 'is second equivalent load capacitance, 4 "is third equivalent load capacitance, 6' is second CMO
S inverter circuit, 9 'is a second voltage output terminal, 10'
Is a second load-side output terminal, 10 ″ is a third load-side output terminal, 10m is an output coupling terminal, 17 ′ is a second P-channel MOS transistor for charge transfer, 18 ′ is a second level shift circuit, 18 ″ is a third level shift circuit, 36,
Reference numerals 37, 38, and 39 denote inverter circuits, and other components that are the same as those shown in FIG.

The second boosting capacitor 1 'and the second boosting capacitor 1 are of the same type and have the same capacitance, and have the second CMOS inverter circuit 6' and the CMOS inverter. The circuit 6 has the same circuit configuration. The power supply voltage supply P-channel MOS transistor 2 ′ and the power supply voltage supply P-channel MOS transistor 2, and the second charge transfer P-channel MOS transistor 17 ′ and the charge transfer P-channel MOS transistor 17 are of the same type, respectively. The second level shift circuit 18 'and the third level shift circuit 1
8 "has the same circuit configuration as the level shift circuit 18. The CMOS inverter circuit 6 and the second CMOS inverter circuit 6 'each have a P-channel MOS transistor 6p and an N-channel MOS transistor 6n. In addition, the gates of the P-channel MOS transistor 6'p and the N-channel MOS transistor 6'n are complementarily connected to each other. P-channel MOS transistors 6'p and N
The gate of the channel MOS transistor 6'n is connected to the output of the inverter circuit 37. The drains of the commonly connected P-channel MOS transistor 6p and N-channel MOS transistor 6n are connected to a P-channel MOS
The drains of the P-channel MOS transistor 6'p and the N-channel MOS transistor 6'n, which are connected to the gate of the S transistor 2 and are also commonly connected, are connected to the gate of the second power supply voltage supply P-channel MOS transistor 2 '. You. The charge transfer P-channel MOS transistor 17 and the second charge transfer P-channel MOS transistor 17 ′ have their gates and drains cross-connected to each other. The drain of the charge transfer P-channel MOS transistor 17 is a voltage output terminal 9. The drain of the second charge transfer P-channel MOS transistor 17 'is connected to the second voltage output terminal 9'. Each source and each base of the charge transfer P-channel MOS transistor 17 and the second charge transfer P-channel MOS transistor 17 'are connected to an output coupling terminal 10m.
0m is also connected to each of the level shift circuits 18, 18 ', 18 ". Note that each of the level shift circuits 18, 18', 1"
8 "transmits the voltage of the output coupling terminal 10m to the corresponding load-side output terminal 10, 10 ', 10" when the inputs 18i, 18'i, 18 "i are at a low level (L),
When the inputs 18i, 18'i, 18 "i are at a high level (L), the low level (L), that is, the ground voltage is transmitted to the load side output terminals 10, 10 ', 10", respectively.

[0070] In this case, the second embodiment, the main circuit components of the step-up circuit device of the first embodiment shown in FIG. 3 2
In this configuration, the outputs of the main circuit parts of these two series are coupled at an output coupling terminal 10m.

The operation of the booster circuit device according to the second embodiment having the above configuration will be described with reference to FIG. However, in the description of the operation of the booster circuit device according to the second embodiment, since the operation of the booster circuit device composed of one series of circuit portions has already been described, here, the operation of the booster circuit device composed of two series of circuit portions is described. Only specific operations will be described.

When the boosted clock signal (VCLK) is at the low level (L) in the boosting operation period, that is, during the period A, the output of the inverter circuit 36 is at the high level (H) and the second CMOS inverter circuit 6 ′ And the outputs of the inverter circuits 37 and 39 become low level (L),
Each output of the MOS inverter circuit 6 and the inverter circuit 38 becomes high level (H). In this case, in the inverter circuits 36 to 39, the high level (H) is at the power supply voltage (V
cc) level, but in the CMOS inverter circuit 6 and the second CMOS inverter circuit 6 ', the high level (H) becomes equal to the voltage level of the voltage output terminal 9 and the second voltage output terminal 9', respectively. In this state, the boosting capacitor 1 is in the boosting mode, the boosting capacitor 1 is supplied with a high level (H) from the inverter circuit 38, and the power supply voltage supply P-channel M
The OS transistor 2 is turned off by the high level (H) output from the CMOS inverter circuit 6, the voltage output terminal 9 is isolated from the power supply terminal 11, and a boosted voltage is generated at the voltage output terminal 9. On the other hand, the second boosting capacitor 1 ′ is in the precharge mode, the second boosting capacitor 1 ′ is supplied with a low level (L) from the inverter circuit 39, and is supplied with the second power supply voltage. The P-channel MOS transistor 2 'is turned on by a low level (L) output from the second CMOS inverter circuit 6', and the second boosting capacitor 1 'is connected to the second boosting capacitor 1' by the inverter circuit 38. To low level (L)
And a second power supply voltage supply P-channel M
The OS transistor 2 'is turned on by the low level (L) output from the second CMOS inverter circuit 6', the second voltage output terminal 9 'is connected to the power supply terminal 11, and the second voltage output terminal 9 'is precharged with the power supply voltage (Vcc).

In the initial state of the boosting operation period,
Both the voltage of the voltage output terminal 9 and the voltage of the second voltage output terminal 9 ′ are at a low level (L) (ground potential), and the voltage output terminal 9 during the period A in one cycle of the first boosting operation. Is lower than the power supply voltage (Vcc), while the voltage at the second voltage output terminal 9 'is equal to the power supply voltage (Vcc). At this time, the gate voltage of the charge transfer P-channel MOS transistor 17 becomes the power supply voltage (Vcc) and is turned on. On the other hand, the gate voltage of the second charge transfer P-channel MOS transistor 17 becomes the power supply voltage (Vcc). The voltage becomes lower and the device is turned off, and the voltage of the voltage output terminal 9 is transmitted to the output coupling terminal 10m.

Next, when the boosted clock signal (VCLK) is at the high level (H) in the boosting operation period, that is, in the section B
During the period, the states of the boosting capacitor 1 and the second boosting capacitor 1 'are reversed, the boosting capacitor 1 is in a precharge state, and the second boosting capacitor 1' is in a boosting mode. . That is, on the boosting capacitor 1 side, a low level (L) is supplied from the inverter circuit 38 to the boosting capacitor 1 in accordance with the high level (H) of the boosting clock signal (VCLK).
The low level (L) is supplied from the S inverter circuit 6 to the power supply voltage supply P-channel MOS transistor 2, the power supply voltage supply P-channel MOS transistor 2 is turned on, and the voltage output terminal 9 is connected to the power supply terminal 11. The voltage output terminal 9 is precharged with the power supply voltage (Vcc). On the other hand, on the second boosting capacitor 1 'side,
Similarly, the high level (H) of the boost clock signal (VCLK)
In response to the above, the high level (H) is supplied from the second inverter circuit 38 'to the second boosting capacitor 1', and the high level (H) is supplied from the second CMOS inverter circuit 6 'to the second boosting capacitor 1'. Is supplied to the power supply voltage supply P-channel MOS transistor 2 ′, the second power supply voltage supply P-channel MOS transistor 2 ′ is turned off, and the second voltage output terminal 9 ′ is isolated from the power supply terminal 11. A boosted voltage higher than the power supply voltage (Vcc) is generated at the second voltage output terminal 9 '. At this time, the P-channel MOS transistor 17 has its gate voltage turned to the power supply voltage (Vcc) and is turned off, while the second P-channel MOS transistor 17 has its gate voltage higher than the power supply voltage (Vcc). In the off state, the second terminal is connected to the voltage coupling terminal 10m.
At the voltage output terminal 9 '.

The operation in the section A and the section B is one cycle of the boosting operation.
By repeating the cycle sequentially, the voltage of the voltage coupling terminal 10m becomes a step-up voltage that is charged stepwise as shown in FIG. In addition, the voltage coupling terminal 10m
The boosted voltage generated in, for example, the level shift circuit 18
If an operation signal as shown in FIG. 6 is given to the input 10i of the second level shift circuit 18 'and the input 10i' of the second level shift circuit 18 ', the voltage of the voltage coupling terminal 10m is set when each of the operation signals is low (L). Is transmitted to the load side output terminals 10 and 10 ′ through the level shift circuits 18 and 18 ′, and the same applies when another operation signal is supplied.

As described above, according to the second embodiment,
In addition to the effect obtained in the basic configuration example , a step-up voltage that is stepwise charged can be obtained, so that the step-up efficiency and the step-up level can be improved.

According to the second embodiment, a plurality of level shift circuits 18, 18 ',
18 ", a plurality of load capacitors 4, 4 ', 4" can be selectively boosted and driven,
The overall size can be reduced.

In the second embodiment, the capacity of the boosting capacitor 1 and the capacity of the second boosting capacitor 1 ′ are sufficiently larger than the sum of the equivalent capacities of the plurality of load capacitors 4, 4 ′, 4 ″. If designed to be large, it is possible to select at least two or more load capacitors 4, 4 ', 4 "at the same time.

FIG. 7 is a circuit diagram showing the configuration of a third embodiment of the booster circuit device according to the present invention.

In FIG. 7, reference numeral 40 denotes a depletion-type N-channel MOS transistor for supplying a power supply voltage (for switching), 41 denotes a depletion-type N-channel MOS transistor for charge transfer, and 42 denotes two P-channel MOS transistors.
An inverter circuit including transistors 43 and 44;
Is a two-input NAND gate, 45 and 46 are inverter circuits,
Numeral 47 denotes a two-input NOR gate, and the same components as those shown in FIG. 3 are denoted by the same reference numerals.

The depletion type N-channel MOS transistor 40 for supplying power supply voltage is connected to the voltage output terminal 9
And N-channel depletion type MO for power supply voltage clamp
The charge transfer depletion type N-channel MOS transistor 41 is connected between the S transistor 20 and the charge transfer depletion type N-channel MOS transistor 41 is connected between the voltage output terminal 9 and the load output terminal 10. The inverter circuit 42 has a configuration in which two P-channel MOS transistors 43 and 44 are connected in series.
It is connected between the voltage output terminal 9 and the ground. P channel MO
The connection point between the S transistors 42 and 43 is connected to the gate of the charge transfer depletion type N-channel MOS transistor 41. In this case, the charge transfer depletion type N-channel MOS transistor 41 and the P-channel MO
S transistors 42 and 43 constitute voltage transmission circuit 16.

[0082] The third embodiment uses a power supply voltage supply depletion type N-channel MOS transistor 40 in place of the power voltage supply P-channel MOS transistor 2 of the first embodiment, also, the first Instead of the voltage transfer circuit 16 including the charge transfer P-channel MOS transistor 17 and the level shift circuit 18 of the embodiment, a voltage transfer circuit 16 including a charge transfer depletion type N-channel MOS transistor 41 and an inverter circuit 42 is used. Is what it is.

The operation of the third embodiment is as follows.

First, in the initial state of the boost operation period, the boost enable signal (VS3) is at the low level (L), and the first and second outputs 1 of the control logic circuit 15 are set.
5 _O1 and 15 _O2 are respectively at low level (L), the third output 15 _O3 is at high level (H), the boosting capacitor 1 is at low level (L), and a depletion type N-channel MOS transistor for power supply. Similarly, a low level (L), reset N
A high level (H) is supplied to the gate of the channel MOS transistor 41, the power supply voltage supply depletion type N-channel MOS transistor 40 is turned off, and the resetting N-channel MOS transistor 4 is turned off.
1 turns on, and the load-side output terminal 10 drops to a low level (L), that is, the ground level. On the other hand, the inverter circuit 42
Is supplied to the gate of the charge transfer depletion type N-channel MOS transistor 41, and the charge transfer depletion type N-channel MOS transistor 41 is output.
The S transistor 41 is turned on. Therefore, the voltage output terminal 9 is at the same low level (L) as the load-side output terminal 10, that is, at the ground level.

Next, when a boost operation period is entered and the boost enable signal (VS3) is changed to a high level (H), the boost operation is started. In this case, the boost clock signal (VF
In the first step where A) is at a high level (H),
In the precharge state, the first output 15 _O1 of the control logic circuit 15 is low (L), the second output 15 _O2 is high (H), and the third output 15 _O3 is low (L). , The low level (L) is supplied subsequently to the boosting capacitor 1, the depletion type N-channel MOS transistor 40 for power supply is turned on, the N-channel MOS transistor 19 for reset is turned off, and the charge transfer The depletion type N-channel MOS transistor 41 turns off. For this reason, the threshold voltage of the depletion type N-channel MOS transistor |
A precharge voltage equal to VthD | is generated.

Subsequently, in the second step in which the boosted clock signal (VFA) goes low (L), the boosted state is established, and the first output 15 _O1 of the control logic circuit 15 goes high (H). The second and third outputs 15 _O2 and 15 _O3 are at a low level (L), a high level (H) is supplied to the boosting capacitor 1, and a depletion type N for power supply is provided.
The channel MOS transistor 40 and the reset N-channel MOS transistor 19 are both turned off, and the charge transfer depletion type N-channel MOS transistor 41 is turned on. At this time, the boosted voltage generated at the voltage output terminal 9 is the charge transfer depletion type N-channel M
The data is transferred to the load side output terminal 10 via the OS transistor 41.

Thereafter, the operations of the first and second steps are repeatedly executed, and the voltage of the load-side output terminal 10 becomes a step-up voltage stepwise increased by the charge pump operation.

In the present embodiment, in addition to the effect obtained in the above-described basic configuration example , there is an effect that the whole can be reduced in size because it is configured using the depletion type N-channel MOS transistor.

If the booster circuit according to the present embodiment is arranged in two lines in parallel as shown in FIG. 5 so that the boosting operation continues continuously in both the first and second steps, The boosting efficiency can be further improved.

[0090] followed, FIG. 8, the ones showing a modification of the third embodiment, instead of using the clamping N-channel MOS transistor 20, as in the basic configuration example, the voltage output terminal 9 and the power supply A power supply voltage clamp circuit 12 including three P-channel MOS transistors diode-connected to a terminal 11 is provided.

According to such a configuration, the clamp voltage value of voltage output terminal 9 can be adjusted by appropriately selecting the number of P-channel MOS transistors constituting power supply voltage clamp circuit 12.

In the above description of each embodiment, an example is described in which one or two series of booster circuit devices are used. However, a multi-system booster circuit device is prepared and a plurality of booster circuit devices having different phases are prepared. A plurality of boosted clock signals are formed, and the plurality of boosted clock signals are separately supplied to each of the boosted circuit devices in the multi-sequence boosted circuit device, thereby forming a multi-series boosted circuit device of three or more series. In this case, a boosted voltage corresponding to the number of series can be obtained, and there is an effect that the boosting efficiency and the boosting level can be further improved.

Finally, FIG. 9 is a circuit diagram showing an example of the configuration of an 8-bit analog-digital (A / D) converter using the booster circuit device according to the present invention.

Referring to FIG. 9, the A / D converter of this example is
A booster circuit device 61, a chopper type comparator 62,
Resistive ladder type digital-analog (D / A) conversion circuit 6
3 and, in particular, with low power supply voltage, high accuracy,
In addition, A / D conversion at a high conversion speed is performed. Incidentally, as the booster circuit device 61 used in the A / D converter of this embodiment, any of the booster circuit devices in the first to third embodiments can be used. An example using the booster circuit device of the second embodiment is shown.

In this A / D converter, the chopper type comparator 62 includes a sampling capacitor 62a.
And the five CMOS switch circuits 62b, 62c, 62
d, 62e, 62f and three capacitively coupled CMOS
It comprises inverter circuits 62g, 62h, 62i, two level shift circuits 62j, 62k, and two inverter circuits 62l, 62m. Further, the resistance ladder type D / A conversion circuit 63 includes a 3-8 column address decoder 63.
a, a 5-32 row address decoder 63b, eight resistor columns 63c, a matrix row selection CMOS switch group 63d for outputting tap voltages of the eight resistor columns 63c as decode outputs, and eight taps Column select CMOS switch group 6 for decoding and outputting one of voltage output lines 63e
3f, an inverter circuit 63g for driving the inverting input side of the row selecting CMOS switch group 63d, an inverter circuit 63h for driving the inverting input side of the column selecting CMOS switch group 63f, and a level shift circuit 63i.

The A / D converter according to the above configuration operates roughly as follows.

First, in the resistance ladder type D / A conversion circuit 63, the column address decoder line 63a and the row address decoder line 63b receive the column address signal line 64 and the row address signal line 65, respectively. One of the output lines goes high (H). At this time, one of the 256 tap voltages of the eight resistor strings 63c is selected, and the selected voltage is applied to the D / A conversion output terminal 63.
j.

Next, the chopper type comparator 62 compares the unknown input signal supplied to the terminal 62n with the reference voltage supplied to the D / A conversion output terminal 63j. Signal (VS
When A) becomes a high level (H), in the CMOS switch circuit 62b, a high level (H) is supplied to the gate of the N-channel MOS transistor and a low level (L) is supplied to the gate of the P-channel MOS transistor, and both are turned on. And the unknown input signal is transmitted to one end of the sampling capacitor 62a. At the same time, the three CMOS switch circuits 62d, 62e and 62f are also turned on, and the inputs and outputs of the three CMOS inverter circuits 62g, 62h and 62i are short-circuited.
The other end of a is logically set to the threshold voltage. Subsequently, in the comparison mode, when the reference voltage selection signal (VRE) goes high (H), the reference voltage supplied to the D / A conversion output terminal 63j is transmitted to one end of the sampling capacitor 62a, and the CMOS switch circuit The input of 62d fluctuates by the difference between the unknown input signal and the reference voltage, and the fluctuation is sequentially amplified by three capacitively coupled CMOS switch circuits 62d, 62e and 62f, and is output to the output of the final stage CMOS switch circuit 62f. Generates a logic level output indicating the comparison result.

The comparison result obtained by the chopper type comparator 62 is reflected on a successive approximation register (not shown), and the comparison is sequentially repeated while generating column and row addresses. The comparison operation is A /
The conversion is performed by the number of D conversion bits.

According to the A / D converter of this embodiment, the CMOS
This solves the problem that the on-resistances of the switch circuits 62b to 62f become maximum with respect to an input voltage near an intermediate value of the operation power supply voltage.
A D conversion device is realized.

Further, the A / D converter of this embodiment only has one booster circuit device (power supply) 61, and the boosted voltage is supplied to a plurality of level shift circuits 18 as shown in the third embodiment. , 18 ′, 18 ″, the load is appropriately distributed to each load, so that the entire A / D converter is reduced in size and the circuit configuration of the A / D converter without a known booster circuit is minimized. You just need to make changes.

[0102]

As described above, according to the first aspect of the present invention, the first boosting capacitive element is connected between the boosted clock signal input terminal and the first voltage output terminal, and the inverted boosted clock signal input A second boost capacitor between the terminal and the second voltage output terminal; a first power supply voltage supply P-channel MOS transistor between the power supply voltage supply terminal and the first voltage output terminal; a second power supply voltage P-channel MOS transistor for supplying between the second voltage output terminal, boosting clock signal input terminal and the first power supply voltage supply P channel
A first gate drive circuit for supplying a boosted clock signal to the gate of the first P-channel MOS transistor for supplying a power supply voltage, an inverted boosted clock signal input terminal, and a second P channel for power supply
A second gate drive circuit for supplying an inverted boosted clock signal to the gate of the second power supply voltage supply P-channel MOS transistor is connected between the gates of the first and second MOS transistors. The power supply voltage of the second gate drive circuit is obtained from the first and second voltage output terminals, respectively, and the first voltage is supplied to the first boosting capacitive element in synchronization with the rising timing of the boosting clock signal supplied to the first boosting capacitive element. The power supply voltage supply P-channel MOS transistor is turned off, the first voltage output terminal is isolated from the power supply voltage supply terminal, and the rising timing of the inverted boosted clock signal supplied to the second boosting capacitance element together, the second power supply voltage P-channel MOS transistor for supplying rendered non-conductive, since the second voltage output terminal is isolated from the power voltage supply terminal Also can perform step-up operation at any portions of the booster clock signal or the inverted boosted clock signal, boosting efficiency of the output voltage is high, there is an effect that boosting speed increases.

In this case, the third and fourth switching P-channels M are provided between the voltage output terminal and the load side output terminal.
By connecting the voltage transmission circuit of the one-way transmission function switch including the OS transistor without voltage drop, there is an effect that a high boosted voltage with little voltage loss can be supplied to the load side output terminal.

According to the fourth aspect of the present invention, the boosting capacitor is provided between the boosted clock signal input terminal and the voltage output terminal, and the power supply voltage supply P-channel MOS transistor is provided between the power supply voltage supply terminal and the voltage output terminal. , boosting clock signal input terminal and the power supply voltage supplying P channel MOS transistor of the gate - to intercluster, a boosting clock signal supply voltage supply P
Since the gate drive circuits to be supplied to the gates of the channel MOS transistors are connected to each other and the power supply voltage of this gate drive circuit is obtained from the voltage output terminal, a boost clock signal supplied to the boost capacitance element Power supply voltage supply P-channel MOS in accordance with the rising timing of
The transistor becomes non-conductive, and the voltage output terminal is isolated from the power supply terminal. In this way, the voltage output terminal is not clamped by the power supply voltage due to the isolation from the power supply voltage supply terminal, so that the voltage of the voltage output terminal can be increased to the power supply voltage or more,
Despite its small size, it has the effect of being able to boost the voltage with high efficiency, which is particularly effective when boosting a power supply voltage of about 1.8 V, and has a voltage output terminal and a load side output terminal. P-channel MOS transistor between
And a voltage transfer circuit composed of a level shifter, the loss of the threshold voltage of the MOS transistor does not occur at the load side output terminal as compared with the case where a diode-connected charge transfer MOS transistor is connected. There is an effect that a boosted voltage can be supplied.

According to the sixth aspect of the present invention, the boosting capacitance element is provided between the first output of the control logic circuit to which the boosted clock signal is input and the voltage output terminal, and the boosted capacitive element is provided between the voltage output terminal and the power supply voltage supply terminal. A depletion type N for supplying a first power supply voltage, the gate of which is connected to a second output of the control logic circuit.
A channel charge MOS depletion type N channel is connected between a voltage output terminal and a load side output terminal.
Le MOS transistor switch, between ground and voltage output terminal, the input is a second connected complementary MOS transistors inverter stage to the output of the control logic circuit is connected,
Since the output of the complementary MOS transistor inverter stage is connected to the gate of the second charge transfer depletion type N-channel MOS transistor,
First depletion type N-channel MOS for supplying power supply voltage
Transistor ON, second charge transfer depletion type
When the N-channel MOS transistor is turned off, the voltage output terminal rises to the power supply voltage.
The source voltage supply depletion type N-channel MOS transistor is turned off, a second charge transfer depletion type N Ji
The channel MOS transistor is turned on, and the voltage of the voltage output terminal is boosted and transmitted to the load side output terminal by the charge pump operation. Therefore, in addition to enjoying the effects of the invention described in claim 4 , there is also an effect that the booster circuit device can be configured to be smaller by employing the complementary MOS transistor inverter stage.

[0106]

[0107]

[0108]

[Brief description of the drawings]

FIG. 1 is a basic premise of a booster circuit device according to the present invention.
FIG. 2 is a circuit configuration diagram showing a configuration example .

FIG. 2 is a voltage waveform diagram of each part showing the operation of the basic configuration example shown in FIG.

FIG. 3 is a circuit configuration diagram showing a configuration of a first embodiment of the booster circuit device according to the present invention.

FIG. 4 is a voltage waveform diagram of each part showing the operation of the first embodiment shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a booster circuit device according to a second embodiment of the present invention.

FIG. 6 is a voltage waveform diagram of each part showing the operation of the second embodiment shown in FIG.

FIG. 7 is a circuit configuration diagram showing a configuration of a third embodiment of the booster circuit device according to the present invention.

FIG. 8 is a circuit diagram showing a modification of the third embodiment shown in FIG. 7;

FIG. 9 is a circuit diagram showing an example of a configuration of an analog / digital conversion circuit using the booster circuit device according to the present invention.

FIG. 10 is a circuit configuration diagram showing an example of a configuration of a known booster circuit device.

FIG. 11 is a voltage waveform diagram showing an operation state of each part of a known booster circuit device. .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Boost capacitor 1 '2nd boost capacitor 2 P-channel MO for power supply (for switching)
S transistor 2 'P-channel MOS transistor for supplying second power supply voltage (for switching) 3 P-channel MOS transistor for charge transfer 3' P-channel MOS transistor for second charge transfer 4, 4 ', 4 "Load capacitor 5 , 21, 22 2-input NAND gate 6 CMOS inverter circuit 6 'Second CMOS inverter circuit 7, 23, 24, 32, 36, 37, 38, 39, 42
Inverter circuit 8 Clock signal (CL) input terminal 9 Voltage output terminal 9 'Second voltage output terminal 10, 10', 10 "Load side output terminal 10m Output coupling terminal 11 Power supply voltage supply terminal 12 Power supply voltage clamp circuit 13 Step-up clock signal (CL) supply line 14 Enable signal (ENB) supply line 15 Control logic circuit 16 Voltage transfer circuit 17 Charge transfer P-channel MOS transistor 17 'Second charge transfer P-channel MOS transistor 18 Level shift circuit 18' Second level shift circuit 18 "Third level shift circuit 19 N channel MOS transistor for reset 20 N channel depletion type MOS transistor for power supply voltage clamp 25 NOR gate 26, 27, 28, 29, 43, 44 P channel MO
S-transistors 30, 31 N-channel MOS transistors 33, 34 Two-phase non-superimposed boosted clock signals (VCK2,
VFA) supply line 35 enable signal (VS3) supply line control logic circuit 40 depletion type N-channel MO for supply of power supply voltage
S transistor 41 Depletion type N-channel MOS transistor for charge transfer

──────────────────────────────────────────────────続 き Continuing on the front page (72) Mitsuhiko Okitsu, 3-2-1 Samachi, Hitachi-shi, Ibaraki Inside Hitachi Engineering Co., Ltd. (72) Masahiro Shiina 3-2-1 Samachi, Hitachi-shi, Ibaraki Hitachi Engineering Co., Ltd. (72) Inventor Takehiro Ota 3-1-1, Sakaimachi, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Plant (56) References JP-A-63-316510 (JP, A) JP-A-5-137320 (JP, A) JP-A-5-49238 (JP, A) JP-A-62-85669 (JP, A) JP-A-59-63755 (JP, A) JP-A-5-127619 (JP, A) A) Japanese Utility Model Hei 6-74087 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 3/07 H01L 27/04

Claims (7)

(57) [Claims] 1. A first boosting capacitor connected between a boosted clock signal input terminal and a first voltage output terminal, and a first boosted capacitive element connected between an inverted boosted clock signal input terminal and a second voltage output terminal. 2 step-up capacitance elements, a first switching P-channel MOS transistor connected between a power supply voltage supply terminal and the first voltage output terminal, and between the power supply voltage supply terminal and the second voltage output terminal. The second connected to
A switching P-channel MOS transistor of the booster clock signal input terminal and the first gate of the switching P-channel MOS transistor - is connected between gate electrode, wherein in response to the boost clock signal first P switching A first gate drive circuit for turning on / off a channel MOS transistor, the inverted boosted clock signal input terminal, and the second switching P-channel MOS
A second switching P channel connected between the gate electrodes of the transistors and in response to the inverted boosted clock signal;
A second gate drive circuit for turning on / off the channel MOS transistor switch in a state opposite to the on / off state of the first switching P-channel MOS transistor ;
The first voltage output terminal and the second voltage output terminal are
A voltage transmission circuit connected between the load-side output terminals , wherein a power supply voltage of the first gate drive circuit is supplied from the first voltage output terminal, and a power supply voltage of the second gate drive circuit is provided.
Voltage from said second voltage output terminal and said voltage transmission
The circuit includes third and fourth switching P-channel MOs.
A third switching P-channel including an S transistor;
The gate of the channel MOS transistor is connected to the first voltage output.
A fourth switching P-channel MOS
The gate of the transistor is connected to the second voltage output terminal.
And the third and fourth switching P-chs.
The source of the channel MOS transistor is the load side output terminal.
A booster circuit device connected to the first terminal. 2. The third and fourth switching P switches.
The substrate of the channel MOS transistor is the output terminal on the load side.
2. The booster circuit device according to claim 1, wherein the booster circuit device is connected to the booster circuit. 3. The power supply voltage supply terminal and the first switch.
P-channel MOS transistor for etching and the second
Between the P-channel MOS transistors for switching of
A voltage clamp circuit is connected to the
3. The booster circuit device according to any one of 1 and 2 . 4. A boosted clock signal input terminal and a voltage output terminal.
Voltage boosting capacitor connected between the terminals and power supply voltage supply terminal
And a first switching connected between the voltage output terminals
P-channel MOS transistor and boost clock
A signal input terminal and the first switching P-channel M
Connected between the gate electrodes of the OS transistors,
The first switching P-channel corresponding to the clock signal;
Gate drive to turn on / off channel MOS transistor
Circuit, and between the voltage output terminal and the load side output terminal.
And a voltage transmission circuit connected to the gate drive circuit.
Supplying a power supply voltage from the voltage output terminal;
Connect a voltage transfer circuit between the terminal and the load side output terminal, and
The voltage transmission circuit supplies the power supply voltage from the load side output terminal.
Supplied level shift circuit and the drain is the voltage output
The terminal and the source and the substrate are gated to the load side output terminal.
Are connected to one output terminal of the level shift circuit, respectively.
Connected second switching P-channel MOS transistor
High level during the precharge period.
And outputs a low level during the boosting period.
Supply to the switching P-channel MOS transistor.
And a booster circuit device. 5. The power supply voltage supply terminal and the first switch.
Voltage between switching P-channel MOS transistor
5. The method according to claim 4, wherein a clamp circuit is connected.
On-board booster circuit device. 6. A first output receiving a boosted clock signal.
Terminal is the first signal, and second output terminal is the opposite of the first signal
A control logic circuit for outputting a second signal of the phase;
Booster connected between the first output terminal and the voltage output terminal of the circuit
Between the voltage output terminal and the power supply terminal
Connected to the second output terminal of the control logic circuit
Switching depletion type N switch connected to
Channel MOS transistor, the voltage output terminal and a load
Second switching N-channel connected between the side output terminals
A channel MOS transistor, between the voltage output terminal and ground
And the input is connected to the second output terminal of the control logic circuit.
And a connected complementary MOS transistor inverter stage.
Eteori, of the complementary MOS transistor inverter stage
The output is the second switching N-channel MOS transistor.
Lift connected to the gate of the transistor
Pressure circuit device. 7. The power supply voltage supply terminal and the first switch.
Depletion type N-channel MOS transistor for pitching
A voltage clamp circuit connected between the
The booster circuit device according to claim 6.