JP6792436B2 - Incremental Delta-Sigma AD Modulator and Incremental Delta-Sigma AD Converter - Google Patents

Description

The present invention relates to an incremental delta-sigma AD modulator and an incremental delta-sigma AD converter.

Conventionally, in an AD converter having a plurality of integrating circuits and converting an analog signal into a digital signal, an incremental delta sigma modulator and an incremental delta that reset the electric charge accumulated in the integrating circuit at predetermined time intervals. Sigma AD converters have been known (see, for example, Patent Documents 1 and 2).
Patent Document 1 International Publication No. 2013/136676 Patent Document 2 Japanese Patent Application Laid-Open No. 2016-131366

It is known that such an incremental delta-sigma modulator and an incremental delta-sigma AD converter are provided with a sample hold circuit in the front stage to widen the bandwidth. However, the switched capacitor or the like used in the sample hold circuit operates at a higher frequency than the frequency at which the incremental delta-sigma modulator or the incremental delta-sigma AD converter outputs a digital signal, so that the power consumption increases. Was. Therefore, a wideband and low power consumption incremental delta-sigma modulator and an incremental delta-sigma AD converter have been desired.

In the first aspect of the present invention, a sample hold unit having a plurality of switched capacitors and sampling an input signal and an analog integrator are provided, and the sample hold unit integrates an analog signal based on the sampled input signal. An analog integrating unit, a quantization unit that quantizes the output signal of the analog integrating unit, and a plurality of switched capacitors are charged with input signals in a predetermined tracking cycle, and a plurality of switched capacitors are charged in a predetermined conversion cycle. The control unit includes a control unit that sequentially transfers the charged charge to the analog integration unit, and the control unit receives an input signal for the next tracking cycle for at least one switched capacitor among the plurality of switched capacitors in the conversion cycle. Provided are an incremental delta sigma AD modulator and an incremental delta sigma AD converter, which start a charging operation after the transfer operation from at least one switched capacitor to the analog integrating unit is completed.

The outline of the above invention does not list all the features of the present invention. Sub-combinations of these feature groups can also be inventions.

An example of a block diagram of the incremental delta-sigma AD converter 100 according to the present embodiment is shown. A configuration example of the sample hold unit 110 and the DA conversion unit 160 according to the present embodiment is shown. A configuration example of the analog integrator 130 according to the present embodiment is shown. A configuration example of the feedforward unit 140 according to the present embodiment is shown. An example of the signal waveform in each part of the incremental delta-sigma AD converter 100 according to the present embodiment is shown. A first example of a signal waveform when the control unit 180 according to the present embodiment performs control to reduce the power consumption of the incremental delta-sigma AD converter 100 is shown. A second example of a signal waveform when the control unit 180 according to the present embodiment performs control to reduce the power consumption of the incremental delta-sigma AD converter 100 is shown. A third example of a signal waveform when the control unit 180 according to the present embodiment performs control to reduce the power consumption of the incremental delta-sigma AD converter 100 is shown. A fourth example of a signal waveform when the control unit 180 according to the present embodiment performs control to reduce the power consumption of the incremental delta-sigma AD converter 100 is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions claimed in the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 shows an example of a block diagram of the incremental delta-sigma AD converter 100 according to the present embodiment. The incremental type delta-sigma AD converter 100 converts the input analog signal into a digital signal while resetting the internal circuit at a substantially constant cycle. The incremental type delta sigma AD converter 100 includes an input terminal 10, an incremental type delta sigma AD modulator 20, a digital arithmetic unit 30, and an output terminal 40.

The input terminal 10 inputs an input signal A _in . The input signal A _in may be an analog signal. The input terminal 10 may be a single-ended input, and may be a differential input instead. When the input terminal 10 is a differential input, the positive side signal AINP is input from the positive side input and the negative side signal AINN is input from the negative side input to the input terminal 10. The input terminal 10 supplies the input input signal A _in to the incremental delta-sigma AD modulator 20.

The incremental type delta-sigma AD modulator 20 converts an analog input signal into a digital value in a substantially constant conversion cycle, and outputs a serial digital code corresponding to the analog input signal in each conversion cycle. The incremental type delta-sigma AD modulator 20 samples a plurality of analog input signals in synchronization with a clock signal or the like, converts each of the plurality of samples into a digital value, and outputs the sample. Here, the number of samplings for one conversion cycle is defined as the oversampling ratio N. That is, the number of digital codes included in the serial digital code is equal to the oversampling ratio N.

The digital arithmetic unit 30 digitally processes the output of the incremental delta-sigma AD modulator 20. The digital arithmetic unit 30 integrates the outputs of the incremental delta-sigma AD modulator 20 and outputs a digital value, for example, as a part of digital processing. As an example, the digital calculation unit 30 may have a digital integration unit, and the digital integration unit may integrate digital codes to calculate a corresponding digital value. The digital calculation unit 30 may calculate a digital value in synchronization with the clock signal.

Further, the digital arithmetic unit 30 filters the output of the incremental delta-sigma AD modulator 20 as, for example, as a part of digital processing. As an example, the digital arithmetic unit 30 has a low-pass filter and reduces quantization noise and the like generated by the incremental delta-sigma AD modulator 20. Further, the digital calculation unit 30 may have a decimation filter to reduce the sampling frequency. The digital calculation unit 30 outputs the digital value of the calculation result from the output terminal 40 as the conversion result of the incremental type delta-sigma AD converter 100.

The incremental delta-sigma AD modulator 20 includes a sample hold unit 110, an addition unit 120, an analog integration unit 130, a feedforward unit 140, a quantization unit 150, a DA conversion unit 160, a reset unit 170, and the like. It includes a control unit 180.

The sample hold unit 110 samples the amplitude value of the input analog signal and holds (holds) the sampled value. The sample hold unit 110 repeats sampling and holding in synchronization with a clock signal or the like. Here, it is desirable that the frequency of the clock signal is several times to several tens of times higher than the frequency of the input signal. In this case, the sample hold unit 110 oversamples the input analog signal. It will be. It should be noted that such a clock signal is generated in a clock signal generator provided inside or outside the incremental delta-sigma AD converter 100, and is supplied to each part inside the incremental delta-sigma AD converter 100. To.

FIG. 1 shows an example _in which the analog signal A _in input by the sample hold unit 110 is sampled and the held value is output. The sample hold unit 110 outputs the held value to the addition unit 120. The sample hold unit 110 will be described later.

The addition unit 120 adds the feedback signal of the incremental delta-sigma AD modulator 20 to the output of the sample hold unit 110. For example, the addition unit 120 receives a differential signal from the sample hold unit 110, and adds feedback signals having different symbols to the positive side signal and the negative side signal of the differential signal. The addition unit 120 supplies the addition result to the analog integration unit 130 as an analog signal based on the input signal sampled by the sample hold unit.

The analog integrator 130 has an analog integrator and integrates the analog signal received from the adder 120. The analog integrator 130 may have a plurality of analog integrators. The analog integrating unit 130 supplies the integrated result to the feedforward unit 140. The analog integrator 130 will be described later.

The feedforward unit 140 transmits the input signal to the quantization unit 150. Further, the feedforward unit 140 transmits the signal output by the analog integrator of the analog integrator unit 130 to the quantization unit 150. The feedforward unit 140 will be described later.

The quantization unit 150 quantizes the output signal of the analog integration unit 130. The quantization unit 150 quantizes, for example, the output signal _Airr of the analog integration unit 130 on which the signal transmitted by the feedforward unit 140 is superimposed. The quantization unit 150 quantizes the integration result of the analog integration unit 130 according to a clock signal or the like supplied from the inside or the outside, and outputs a bit stream according to the integration result. The quantizer 150 may function as a 1-bit quantizer or a multi-bit quantizer.

For example, when a 1-bit quantizer is used as the quantization unit 150, the bit stream becomes a sequence (serial digital code) of a predetermined number of 1-bit data (digital code). Here, the value obtained by integrating the digital codes is a digital value that is proportional to or substantially matches the amplitude value of the input signal A _in . The quantization unit 150 compares the output signal _{Airr with a} predetermined threshold value for each clock signal, and converts the output signal _Airr into a digital code of 1 or 0 depending on whether or not the threshold value is exceeded. You can do it.

Further, for example, when an M-bit quantizer is used as the quantization unit 150, the bit stream becomes a sequence (serial digital code) of a predetermined number of M-bit data (digital codes). Here, the value obtained by integrating the digital codes becomes a digital value that is proportional to or substantially matches the amplitude value of the input signal A _in . The quantization unit 150 compares the output signal _Airr and the predetermined M-bit thresholds with a comparator for M bits for each clock signal, and determines whether or not each comparator exceeds the threshold. The output signal A _err may be converted into an M-bit digital code.

That is, the incremental type delta-sigma AD modulator 20 converts the input signal A _in into a digital value at a constant conversion cycle, but the quantization unit 150 inputs the input signal A _in according to a clock signal or the like faster than one conversion cycle. The serial digital code corresponding to the signal A _in is output. In this way, the input signal A _in is converted into a digital value for each of the plurality of samples synchronized with the clock signal. Assuming that the number of samplings for one conversion cycle is the oversampling ratio N, the number of digital codes included in the serial digital code is equal to the oversampling ratio N.

For example, when the oversampling ratio N of the incremental delta-sigma AD modulator 20 is 60, the quantization unit 150 outputs a serial digital code including 60 digital codes in each conversion cycle. The quantization unit 150 supplies the quantized digital signal Y to the DA conversion unit 160. Further, the quantization unit 150 supplies the quantized digital signal Y as the output of the incremental type delta-sigma AD modulator 20 to the digital calculation unit 30.

The DA conversion unit 160 DA-converts the output of the quantization unit 150 and outputs a feedback signal to be fed back to the analog integration unit 130. The DA conversion unit 160 DA-converts the digital signal Y output by the quantization unit 150 into a corresponding analog signal, and supplies the converted analog signal to the addition unit 120 as a feedback signal. The DA conversion unit 160 may convert the digital signal Y into an analog signal in synchronization with the clock signal.

The reset unit 170 resets the integrated value held by the analog integrating unit 130 in a predetermined first cycle. The reset unit 170 may further reset the digital filter or the like of the digital calculation unit 30. The reset unit 170 may reset the analog integrator 130 and the digital arithmetic unit 30 each time the incremental delta-sigma AD modulator 20 converts the input signal A _in into a digital value. As an example, the reset unit 170 supplies a reset signal to the analog integrator unit 130 and the digital arithmetic unit 30 to reset each of the conversion cycles (first cycle) to the digital value.

The control unit 180 controls the operation of the sample hold unit 110. Further, the control unit 180 may control the operation of the analog integration unit 130 and the feedforward unit 140. The control unit 180 may execute the control operation of the incremental delta-sigma AD modulator 20 according to a clock signal or the like supplied from the inside or the outside. The control operation of the control unit 180 will be described later.

As described above, the incremental type delta-sigma AD converter 100 according to the present embodiment resets the analog integrating unit 130 and the digital arithmetic unit 30 by the reset unit 170, and converts the input signal A _{in to} the digital output. Repeat in synchronization with the clock signal. The incremental delta-sigma AD converter 100 may operate as a delta-sigma AD converter if there is no reset operation by the reset unit 170.

FIG. 2 shows a configuration example of the sample hold unit 110 and the DA conversion unit 160 according to the present embodiment. The sample hold unit 110 and the DA conversion unit 160 shown in FIG. 2 show a more detailed configuration example of the sample hold unit 110 shown in FIG. Note that FIG. 2 shows an example in which a differential signal is input to the sample hold unit 110.

The sample hold unit 110 includes a plurality of switched capacitors and samples the input signals AINP and AINN to be input to the incremental delta-sigma AD converter 100. The sample hold unit 110 may include substantially the same number of switched capacitors as the oversampling ratio N. The plurality of switched capacitors have a capacitor C _s1pj , a capacitor C _s1nj, and a changeover switch in the front stage and the rear stage of each capacitor, respectively. In addition, j is a natural number from 1 to m, and m is a value substantially the same as the oversampling ratio N.

The switch in the _previous stage of the capacitor C _s1pj switches one terminal of the capacitor C _s1pj to either an input terminal input by the analog signal AINP or a reference potential. _Further , the switch in the _subsequent stage of the capacitor C _s1pj switches the other terminal of the capacitor C _s1pj to either the reference potential or the addition unit 120. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

Similarly, the switch in the _previous stage of the capacitor C _s1nj switches one terminal of the capacitor C _s1nj to either an input terminal input by the analog signal AINN or a reference potential. _Further , the switch in the _subsequent stage of the capacitor C _s1nj switches the other terminal of the capacitor C _s1nj to either the reference potential or the addition unit 120.

The control unit 180 supplies and controls the signal φt to each of the plurality of switched capacitors of the sample hold unit 110. For example, at the first timing (for example, the signal φt has a high potential), the control unit 180 connects one terminal of the capacitor C _s1pj to the input terminal AINP and connects the other terminal to the reference potential on the positive side. Charges the analog input signal of. In this case, at the first timing, the control unit 180 _connects one terminal of the capacitor C _s1nj to the input terminal AINN and connects the other terminal to the reference potential to charge the analog input signal on the negative side.

In the present embodiment, such a first timing is defined as a tracking cycle. That is, the control unit 180 charges the plurality of switched capacitors with input signals in a predetermined tracking cycle.

Further, the control unit 180 connects the j-th capacitor _Cs1nj to the reference potential at the timing deviated from the tracking cycle by the j-th (the signal φij is a high potential), and connects the other terminal to the addition unit 120. The charged positive analog input signal is sequentially discharged to the analog integrating unit 130. Similarly, the control unit 180 connects the j-th capacitor C _s1pj to the reference potential at the timing deviated from the first timing by the j-th timing, and connects the other terminal to the addition unit 120 to charge the capacitor. The negative analog input signal is sequentially discharged to the analog integrating unit 130.

In the present embodiment, the timing at which the control unit 180 discharges the plurality of switched capacitors is defined as the conversion cycle. That is, the control unit 180 sequentially transfers the charges charged in the plurality of switched capacitors to the analog integration unit 130 in a predetermined conversion cycle. Here, one conversion cycle (first cycle) is the sum of the tracking cycle and the conversion cycle. Further, the plurality of switched capacitors may execute sampling N times in the first cycle and output the sampling result N times. Further, the sample hold unit 110 may have the same number of switched capacitors as the oversampling ratio N, which is the ratio of the number of samples to the first period. In this case, the N switched capacitors may sequentially execute the charge transfer operation to the analog integrator 130 so as to complete the charge transfer operation within the conversion cycle.

As an example, the control unit 180 charges a plurality of switched capacitors with analog input signals in the first clock, and transfers the charged analog input signals to the analog integrating unit 130 according to the corresponding clock signals after the first clock. And discharge sequentially. As a result, the sample hold unit 110 can sequentially supply substantially the same analog values sampled by the plurality of switched capacitors in the first clock to the analog integrator unit 130 in the first clock and thereafter. That is, even if the analog signal changes at high speed, the sample hold unit 110 can hold the value at one timing and convert it into a digital value.

The DA conversion unit 160 includes a first reference voltage REFP, a second reference voltage REFN, a capacitor C _fbp , a capacitor C _fbn , a first switch unit 162, a second switch unit 164, and a third switch unit 166. Has. The first reference voltage REFP and the second reference voltage REFN output voltages having substantially the same absolute value and opposite polarities. As an example, the first reference voltage REFP outputs a positive voltage, and the second reference voltage REFN outputs a negative voltage.

The first switch unit 162 switches one terminal of the capacitor C _fbp to either the first reference voltage REFP or the reference potential. Further, the first switch unit 162 switches one terminal of the capacitor C _fbn to either the second reference voltage REFN or the reference potential. For example, the signal φs supplies control unit 180 is in the timing of the high-potential, one terminal of the capacitor _{C fbp} connected to a first reference voltage REFP, one terminal of the capacitor _{C fbn} connected to the second reference voltage REFN .. In this case, the timing of the control unit 180 is signal φi is high potential supplied, one terminal of one terminal and the capacitor C _fbn capacitor C _fbp, connected to a reference potential.

The second switch unit 164 switches whether or not to connect the other terminals of the capacitor C _fbp and the capacitor C _fbn to the reference potential. In the second switch unit 164, for example, when the signal φs has a high potential, the other terminals of the capacitor C _fbp and the capacitor C _fbn are connected to the reference potential, and when the signal φi has a high potential, the other terminal and the other terminal Disconnect the electrical connection at the reference potential. The control unit 180 controls the first switch unit 162 and the second switch unit 164 to _connect the capacitor C _fbp and the capacitor C _fbn to the corresponding reference voltage at the timing when the signal φs is at a high potential, respectively, and the reference voltage. And charge the charge according to the capacity of the capacitor.

The third switch unit 166 switches whether or not to connect the other terminals of the capacitor C _fbp and the capacitor C _fbn to the addition unit 120. The third switch unit 166 connects, for example, the other terminals of the capacitor C _fbp and the capacitor C _fbn to the addition unit 120 at the timing when the signal φi has a high potential, and the other terminal at the timing when the signal φs has a high potential. And disconnect the electrical connection of the adder 120. The control unit 180 controls the third switch unit 166 to supply the charges charged to the capacitor C _fbp and the capacitor C _fbn to the addition unit 120 according to the first reference voltage REFP and the second reference voltage REFN, respectively. ..

Further, the third switch unit 166 switches the connection destination of the other terminal of the capacitor C _fbp and the capacitor C _fbn according to the digital signal Y supplied from the quantization unit 150. Here, the addition unit 120, which is the connection destination of the capacitor C _fbp and the capacitor C _fbn , corresponds to the differential signal received from the sample hold unit 110, and feeds back signals to the positive side signal and the negative side signal of the differential signal, respectively. Has a path to transmit.

For example, when the digital code of the digital signal Y is "0", the third switch unit 166 adds a charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the positive side signal of the differential signal. Switch the connection as follows. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the negative side signal of the differential signal. As an example, when the signal φip becomes a high potential according to the digital code of “0”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the positive signal at that timing. , The other terminal of the capacitor C _fbn is connected to the transmission line of the negative signal.

Further, for example, when the digital code of the digital signal Y is "1", the third switch unit 166 uses the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp as the negative side signal of the differential signal. Switch the connection to add. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the positive side signal of the differential signal. As an example, when the signal φin becomes a high potential according to the digital code of “1”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the negative signal at that timing. , The other terminal of the capacitor C _fbn is connected to the transmission line of the positive signal.

In this way, the DA conversion unit 160 outputs an analog signal corresponding to the positive reference voltage as a feedback signal to the addition unit 120 in response to the digital signal “0” output by the quantization unit 150, and outputs the feedback signal to the addition unit 120. Add to the differential signal. Further, the DA conversion unit 160 outputs an analog signal corresponding to the negative reference voltage to the addition unit 120 as a feedback signal according to the digital signal “1” output by the quantization unit 150, and differentially outputs the feedback signal to the addition unit 120. Add to the signal.

As described above, the control unit 180 controls the sample hold unit 110 and the DA conversion unit 160 to superimpose the feedback signal for adding or subtracting the reference voltage on the input analog signal and supply it to the analog integration unit 130. To do. In FIG. 2, the positive side signal supplied from the addition unit 120 to the analog integration unit 130 is SP, and the negative side signal is SN. The operation of the analog integrator 130 of the incremental delta-sigma AD modulator 20 will be described below.

FIG. 3 shows a configuration example of the analog integrator 130 according to the present embodiment. FIG. 3 shows an example in which a differential signal from the addition unit 120 by the positive signal SP and the negative signal SN is input to the analog integration unit 130. The analog integrator 130 has a plurality of analog integrators and a plurality of switched capacitors. The analog integrator 130 shown in FIG. 3 shows an example having three analog integrators of a first analog integrator 210, a second analog integrator 220, and a third analog integrator 230. Further, the analog integrator 130 shows an example having two switched capacitors, a first switched capacitor 240 and a second switched capacitor 245.

Further, FIG. 3 shows an example in which three analog integrators have two input terminals and two output terminals, respectively, input a differential signal, and output a differential signal. One of the two input terminals of the analog integrator is the first input terminal, and the other is the second input terminal. Further, one of the two output terminals of the analog integrator is used as the first output terminal, and the other is used as the second output terminal.

The analog integrator includes an analog amplifier, a feedback capacitor, and a reset switch, respectively. FIG. 3 shows an example in which the first analog integrator 210 includes a first analog amplifier 212, a positive feedback capacitor C _i1p , a negative feedback capacitor C _i1n , a positive reset switch 214, and a negative reset switch 216. Further, the second analog integrator 220 includes a second analog amplifier 222, a positive feedback capacitor C _i2p , a negative feedback capacitor C _i2n , a positive reset switch 224, and a negative reset switch 226, and also includes a third analog. An example is shown in which the integrator 230 includes a third analog amplifier 232, a positive feedback capacitor C _i3p , a negative feedback capacitor C _i3n , a positive reset switch 234, and a negative reset switch 236.

The analog amplifier amplifies and outputs the signals input to the positive input terminal and the negative input terminal, respectively. The analog amplifier is, for example, a differential input type amplifier circuit. Further, the analog amplifier may have a single-ended output, and instead, a differential output may be used. The analog amplifier is, for example, an OP amplifier. FIG. 3 shows an example in which three analog integrators, a first analog amplifier 212, a second analog amplifier 222, and a third analog amplifier 232, include differential input and differential output analog amplifiers, respectively. In FIG. 3, the positive input terminal of the analog amplifier is connected to the first input terminal of the analog integrator, and the negative input terminal is connected to the second input terminal.

Each of the feedback capacitors sequentially accumulates charges according to the input signal. The feedback capacitor sequentially accumulates electric charges from the front stage to the rear stage for each sampling, for example. As an example, the electric charge accumulated in the positive feedback capacitor C _i1p in the first clock according to the positive signal SP is accumulated in the positive feedback capacitor C _i2p in the next second clock, and is accumulated in the positive feedback capacitor C _i2p in the next third clock. It is stored in the positive feedback capacitor _Ci3p . Similarly, according to the negative signal SN, the electric charge accumulated in the negative feedback capacitor C _i1n in the first clock is accumulated in the negative feedback capacitor C _i2n in the next second clock, and is accumulated in the negative feedback capacitor C _i2n in the next third clock. It is stored in the negative feedback capacitor _Ci3n .

The reset switch discharges the electric charge accumulated in the feedback capacitor and resets each of the analog integrators in response to an instruction from the reset unit 170. The reset switch connects between the terminals of the feedback capacitor in response to the reset signal supplied from the reset unit 170, for example, and discharges the accumulated charge. In the example of FIG. 3, according to the instruction from the reset unit 170, the positive side reset switch 214, the negative side reset switch 216, the positive side reset switch 224, the negative side reset switch 226, the positive side reset switch 234, and the negative side reset The switches 236 are each switched on to reset the first analog amplifier 212, the second analog amplifier 222, and the third analog amplifier 232.

The switched capacitors are provided between the analog integrators and transfer the charges accumulated in the analog integrators connected to the previous stage to the analog integrators connected to the subsequent stages. The switched capacitor includes a capacitor for charging and discharging and switches provided in the front and rear stages of the capacitor. The switch in the previous stage switches the connection destination of one terminal of the capacitor to either the circuit in the previous stage of the switched capacitor or the reference potential. The subsequent switch switches the connection destination of the other terminal of the capacitor to either the subsequent circuit of the switched capacitor or the reference potential. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

In a switched capacitor, for example, in one clock, one terminal of the capacitor is connected to the analog integrator of the previous stage, and the other terminal of the capacitor is connected to the reference potential, so that the analog integrator connected to the previous stage The capacitor charges the output charge. In this case, in the next clock, the switched capacitor charges the charge charged by the capacitor by connecting one terminal of the capacitor to the reference potential and connecting the other terminal of the capacitor to the analog integrator in the subsequent stage. Discharge to the analog integrator of.

FIG. 3 shows an example in which the first switched capacitor 240 is connected between the first analog integrator 210 and the second analog integrator 220. The first switched capacitor 240, using the primary switch 242 and secondary switch 244, the charge accumulated in front of the positive-side feedback capacitor _{C i1p,} capacitor _{C s2p} is charged, to the subsequent positive feedback capacitor _{C i2p} Is discharged and transmitted. In this case, similarly, the first switched capacitor 240, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _I1n, capacitor C _s2n is charged, and discharged to the subsequent negative feedback capacitor C _i2n To do.

Further, FIG. 3 shows an example in which the second switched capacitor 245 is connected between the second analog integrator 220 and the third analog integrator 230. Second switched capacitor 245, using the primary switch 246 and secondary switch 248, the charge accumulated in front of the positive-side feedback capacitor _{C i2p,} capacitor _{C S3P} is charged, to the subsequent positive feedback capacitor _{C I3P} Is discharged and transmitted. In this case, likewise, the second switched capacitor 245, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _i2n, capacitor C _S3N are charged, and discharged to the subsequent negative feedback capacitor C _I3n To do.

As described above, in the analog integrator 130, a plurality of analog integrators are connected in series, and the positive side signal SP and the negative side signal SN are charged from the analog integrator in the previous stage to the analog integrator in the rear stage for each clock. Are sequentially accumulated and transmitted. The analog integrator 130 outputs the electric charge accumulated in the feedback capacitor of the analog integrator in the latter stage to the quantization unit 150. When the analog integrator 130 has a feedforward unit 140, the analog integrator in the latter stage outputs to the quantization unit 150 via the feedforward unit 140.

For example, since the analog integrator 130 shown in FIG. 3 has a three-stage analog integrator, the electric charge accumulated in the first analog integrator 210 in the first clock is stored in the third analog integrator 230 in the third clock. It is transmitted and output to the feed forward unit 140. As shown in FIG. 1, when the analog integrator 130 has a feedforward unit 140, the output signals INT10P and INT10N of the first analog integrator 210 and the output signals INT20P and INT20N of the second analog integrator 220 are also the third. Similar to the output signals INT30P and INT30N of the analog integrator 230, the output signals are output to the feed forward unit 140.

Although FIG. 3 has described an example in which the analog integrator 130 has three analog integrators, instead of this, the analog integrator 130 may have two or four or more analog integrators. Good. In this case, one or three or more switched capacitors may be provided in the analog integrator 130 depending on the number of analog integrators. Further, although the analog integrating unit 130 shown in FIG. 1 shows an example having the feedforward unit 140, the feedforward unit 140 may not be provided instead. In this case, the output signals INT30P and INT30N of the third analog integrator 230 in the final stage are supplied to the quantization unit 150.

FIG. 4 shows a configuration example of the feedforward unit 140 according to the present embodiment. The feedforward unit 140 includes a first feedforward unit 250, a second feedforward unit 260, a third feedforward unit 270, and a fourth feedforward unit 280. The feedforward unit 140 may be controlled by the control unit 180.

The first feedforward unit 250 includes one or a plurality of switched capacitors, and transmits the analog signals AINP and AINN input to the incremental delta-sigma AD modulator 20 to the quantization unit 150. FIG. 4 shows an example in which the first feedforward unit 250 includes a plurality of switched capacitors. The first feedforward unit 250 may include the same number of switched capacitors as the oversampling ratio N. One switched capacitor included in the first feedforward unit 250 includes, for example, a first FF switch 252, a capacitor C _0ffpj , and a capacitor C _0ffnj . In addition, j was a natural number from 1 to an oversampling ratio N (60 as an example).

The first FF switch 252 switches, for example, one terminal of the capacitor C _0ffpj to either an input terminal or a reference potential input by the analog signal AINP according to the control signal of the control unit 180. _Further, the other terminal of the capacitor C _0ffpj is connected to the quantization unit 150. As an example, the capacitor C _0ffpj has one terminal connected to the input terminal at the first timing to charge the analog input signal. Then, one terminal of the capacitor C _0ffpj is connected to the reference potential at the timing deviated from the first timing by the jth timing, and the charged analog input signal is discharged to the quantization unit 150.

Similarly, the first FF switch 252 switches one terminal of the capacitor C _0ffnj to either an input terminal input by the analog signal AINN or a reference potential according to the control signal of the control unit 180. At the first timing, one terminal of the capacitor C _0ffnj is connected to the input terminal to charge the analog input signal. Then, one terminal of the capacitor C _0ffnj is connected to the reference potential at the timing deviated from the first timing by the jth timing, and the charged analog input signal is discharged to the quantization unit 150. That is, each of the plurality of switched capacitors charges the analog input signal in the first clock, and sequentially discharges the charged analog input signal to the quantization unit 150 according to the corresponding clock signals after the first clock.

The second feedforward unit 260 includes a switched capacitor, and transmits signals (for example, INT10P and INT10N) output by the first analog integrator 210 to the quantization unit 150. The second feedforward unit 260 may include a switched capacitor. The second feedforward unit 260 includes, for example, a second FF switch 262, a capacitor C 1 _fpp , and a capacitor C 1 _fpn .

The second FF switch 262 has one terminal of the capacitor C _{1ffp on} the positive side according to the control signal of the control unit 180, and one of the first output terminal and the reference potential at which the first analog integrator 210 outputs the signal INT10P. Switch to. _Further, the other terminal of the capacitor C _1ffp is connected to the quantization unit 150. For example, in the first clock of the capacitor C _1ffp , one terminal is connected to the output terminal to charge the signal INT10P. Then, in the second clock, one terminal of the capacitor C _1fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the second FF switch 262 has one terminal of the negative capacitor C _1ffn according to the control signal of the control unit 180, the second output terminal where the first analog integrator 210 outputs the signal INT10N, and the reference potential. Switch to one of. _Further, the other terminal of the capacitor C _1ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _1ffn is connected to the output terminal to charge the signal INT10N. Then, in the second clock, one terminal of the capacitor C _1ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

The third feedforward unit 270 includes a switched capacitor, and transmits signals output by the second analog integrator 220 (for example, INT20P and INT20N) to the quantization unit 150. The third feedforward unit 270 may include a switched capacitor. The third feedforward unit 270 includes, for example, a third _FF switch 272, a capacitor C _2ffp , and a capacitor C _2ffn .

The third FF switch 272 is one of the first output terminal and the reference potential at which the second analog integrator 220 outputs the signal INT20P to one terminal of the capacitor C _{2ffp on} the positive side according to the control signal of the control unit 180. Switch to. _Further, the other terminal of the capacitor C _2fp is connected to the quantization unit 150. For example, in the first clock of the capacitor C _2fp , one terminal is connected to the output terminal to charge the signal INT 20P. Then, in the second clock, one terminal of the capacitor C _2fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the third FF switch 272 has one terminal of the negative capacitor C _2ffn according to the control signal of the control unit 180, the second output terminal where the second analog integrator 220 outputs the signal INT20N, and the reference potential. Switch to one of. _Further, the other terminal of the capacitor C _2ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _2ffn is connected to the output terminal to charge the signal INT20N. Then, in the second clock, one terminal of the capacitor C _2ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

The fourth feedforward unit 280 includes a switched capacitor, and transmits signals output by the third analog integrator 230 (for example, INT30P and INT30N) to the quantization unit 150. The fourth feedforward unit 280 may include a switched capacitor. The fourth feedforward unit 280 includes, for example, a fourth _FF switch 282, a capacitor C _3ffp , and a capacitor C _3ffn .

The fourth FF switch 282 has one terminal of the capacitor C _{3ffp on} the positive side according to the control signal of the control unit 180, and one of the first output terminal and the reference potential at which the third analog integrator 230 outputs the signal INT30P. Switch to. _Further, the other terminal of the capacitor C _3fp is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _3fp is connected to the output terminal to charge the signal INT30P. Then, in the second clock, one terminal of the capacitor C _3fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the fourth FF switch 282 has one terminal of the negative capacitor C _3ffn according to the control signal of the control unit 180, and the second output terminal and the reference potential at which the third analog integrator 230 outputs the signal INT30N. Switch to one of. _Further, the other terminal of the capacitor C _3ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _3ffn is connected to the output terminal to charge the signal INT30N. Then, in the second clock, one terminal of the capacitor C _3ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

As an example, the control unit 180 charges the second feedforward unit 260, the third feedforward unit 270, and the fourth feedforward unit 280 at the timing when the signal φi has a high potential, and the signal φs. The discharge operation is executed at the timing of high potential. As described above, the feedforward unit 140 uses the signal input to the incremental delta-sigma AD modulator 20 and the signal output by the analog integrator of the analog integrator 130 as feedforward signals in the quantization unit. Communicate to 150. With such a feedforward signal, the digital code output by the quantization unit 150 for each clock can be made to reflect the analog input signal at a higher speed.

The incremental delta-sigma AD modulator 20 according to the present embodiment is not limited to such a feedforward operation. For example, the feedforward section 140 may have a structure having at least one of a first feedforward section 250, a second feedforward section 260, a third feedforward section 270, and a fourth feedforward section 280. ..

The incremental type delta-sigma AD modulator 20 according to the above embodiment integrates an input analog signal, and feedback control that adds or subtracts a reference voltage to the input analog signal according to the quantization result of the integration result. To execute. As a result, the incremental type delta-sigma AD modulator 20 can accurately output the serial digital code corresponding to the input analog signal. Further, the incremental type delta-sigma AD converter 100 can digitally process such a serial digital code and output a digital signal corresponding to the analog signal with high accuracy. The operation of each part according to the clock signal of such an incremental type delta-sigma AD converter 100 will be described below.

FIG. 5 shows an example of a signal waveform in each part of the incremental delta-sigma AD converter 100 according to the present embodiment. The horizontal direction (horizontal axis) of FIG. 5 indicates time, and the vertical direction (vertical axis) indicates peak value (as an example, voltage value). In FIG. 5, the time domain in which the input analog signal is sampled and held is referred to as “tracking” as the tracking cycle (or tracking phase). Further, the time domain for converting the held analog signal into a digital signal is referred to as "conversion" as the conversion period (or conversion phase). An example of the analog signal to be input is shown as a signal AIN (= AINP-AINN).

The reset unit 170 resets the analog integration unit 130 and the digital calculation unit 30 in the tracking cycle Tt. An example of the reset signal output by the reset unit 170 is shown in the signal φr of FIG. The signal φr has a high potential in the tracking cycle Tt. The reset unit 170 may supply a reset signal to the control unit 180. In this case, the control unit 180 controls each unit based on the reception timing of the reset signal. Instead, the control unit 180 may control the output timing of the reset signal of the reset unit 170.

The sample hold unit 110 samples the analog signals AINP and AINN in the tracking cycle Tt. For example, the plurality of switched capacitors of the sample hold unit 110 charge the analog input signal according to the high potential of the signal φt supplied from the control unit 180 in the tracking cycle Tt. The plurality of switched capacitors included in the first feedforward unit 250 may also charge the analog input signal according to the signal φt.

Further, the sample hold unit 110 is charged according to the signal φij (j is a natural number from 1 to m and m is the same number as the oversampling ratio N) supplied from the control unit 180 in the conversion cycle Tc. The input signal is sequentially discharged to the analog integrating unit 130. For example, the capacitor C _s1pj and the capacitor C _s1nj included in the sample hold unit 110 sequentially discharge the charged analog input signal according to the high potential signal φij at different timings. The plurality of switched capacitors included in the first feedforward unit 250 may also sequentially discharge the analog input signal according to the signal φt.

As a result, the analog integration unit 130 integrates the analog input signals sequentially discharged from the sample hold unit 110, and the quantization unit 150 quantizes the integration result and outputs it as a digital signal Y. Note that FIG. 5 shows an example of the digital signal Y output by the quantization unit 150 as the signal Y.

Further, FIG. 5 shows an example of the signal φs and the signal φi that control the first switch unit 162 and the second switch unit 164. When the signal φs and the signal φi are supplied from the control unit 180 to the DA conversion unit 160, the first switch unit 162 and the second switch unit 164 are switched to the reference voltage corresponding to the capacitor C _fbp and the capacitor C _fbn. The corresponding charge is charged. Note that FIG. 5 shows an example of the first reference voltage REFP and the second reference voltage REFN. The first reference voltage REFP may have a substantially constant high potential, and in this case the second reference voltage REFN may have a substantially constant low potential.

Further, FIG. 5 shows an example of a signal φip and a signal φin that control the third switch unit 166 of the DA conversion unit 160 according to the signal Y. The signal φip is a signal having a high potential depending on the bit value of the signal Y being 0, and the signal φin is a signal having a low potential depending on the bit value of the signal Y being 1. is there. By controlling the third switch unit 166 by the signal φip and the signal φin, the addition unit 120 can add the feedback signal to the differential signal.

In the conversion cycle Tc, when all (that is, m) switched capacitors of the sample hold unit 110 complete the discharge and the quantization unit 150 sequentially outputs m digital codes, the incremental delta-sigma AD converter. 100 may terminate one conversion cycle. That is, the incremental type delta-sigma AD converter 100 shifts from the conversion cycle to the tracking cycle, and the reset unit 170 resets the analog integration unit 130 and the digital calculation unit 30. The incremental delta-sigma AD converter 100 may further have a digital calculation cycle for executing the calculation by the digital calculation unit 30 between the conversion cycle and the next tracking cycle. In this embodiment, the digital calculation cycle is omitted.

In this way, the incremental delta-sigma AD converter 100 repeats a conversion cycle including a tracking cycle and a conversion cycle to convert an analog input signal into a digital signal. Unlike the delta-sigma AD converter, the incremental type delta-sigma AD converter 100 discharges and resets the electric charge accumulated in the analog integrator 130 in the tracking cycle. As a result, the digital value converted in one conversion cycle is made into a more accurately converted value of the analog input signal value without being affected by the electric charge accumulated in a cycle different from that of one conversion cycle. Can be done.

In such an incremental type delta-sigma AD converter 100, since the sample hold unit 110 samples the input signal at a frequency higher than one conversion cycle, it can correspond to a wider band signal. However, in the sample hold unit 110, since a plurality of switched capacitors sample according to the high frequency clock, the amount of electric charge to be transferred per unit time may increase, and the power consumption may increase.

Therefore, in the incremental type delta-sigma AD converter 100 according to the present embodiment, the control unit 180 controls the charge / discharge operation of the sample hold unit 110 to reduce the power consumption. The operation of each part according to the clock signal of such an incremental type delta-sigma AD converter 100 will be described below.

FIG. 6 shows a first example of a signal waveform when the control unit 180 according to the present embodiment controls to reduce the power consumption of the incremental delta-sigma AD converter 100. FIG. 6 shows the time in the horizontal direction and the peak value in the vertical direction, similar to the signal waveform shown in FIG. Further, FIG. 6 shows the tracking cycle as “tracking” and the conversion cycle as “conversion”, as in FIG.

FIG. 6 shows an example in which the control unit 180 executes an operation similar to the operation described with reference to FIG. 5 except for the operation of the sample hold unit 110. That is, the analog signal AIN, the reset signal φr, the signal φs for controlling the first switch unit 162 and the second switch unit 164, the signal φi, the first reference voltage REFP, and the second reference voltage REFN shown in FIG. 6 are shown in FIG. An example is shown in which the signal waveform is substantially the same as each of the signal waveforms shown in. Further, since the input analog signal AIN shown in FIG. 6 is substantially the same as the signal waveform shown in FIG. 5, the digital signal Y output by the incremental delta sigma AD modulator 20 and the signal for controlling the third switch unit 166 are controlled. The φip and the signal φin also have substantially the same signal waveform as each of the signal waveforms shown in FIG.

Here, the control unit 180 starts the charging operation for at least one switched capacitor among the plurality of switched capacitors in the conversion cycle after the transfer operation from at least one switched capacitor to the analog integrating unit 130 is completed. The charging operation is an input signal charging operation for the next tracking cycle. That is, the control unit 180 starts the operation of the tracking cycle of some switched capacitors in the conversion cycle.

FIG. 6 shows an example in which the control unit 180 sequentially starts the charging operation for the next tracking cycle for each of the plurality of switched capacitors in the conversion cycle after the transfer operation is completed. Here, the control unit 180 generates different control signals φt1, φt2, ..., Φtm for m switched capacitors and supplies them to each of them. The control unit 180 charges all the capacitors of the sample hold unit 110 with analog input signals, for example, in the tracking cycle. That is, the control unit 180 supplies all the capacitors with a control signal that keeps the high potential during the tracking cycle.

Next, the control unit 180 discharges the electric charges charged in the first capacitors C _s1p1 and C _s1n1 to the analog integrator 130 at the first timing of the conversion cycle (timing changed to the conversion cycle). Let me. Then, the control unit 180 starts the charging operation of the next analog input signal of the first capacitors C _s1p1 and C _{s1n1 at} the second timing of the conversion cycle.

That is, the control unit 180 supplies the control signal φt1 having a low potential at the first timing and a high potential at the second timing to the first capacitors C _s1p1 and C _s1n1 . Further, the control unit 180 supplies the control signals φi1 having a high potential at the first timing and a low potential at the second timing to the first capacitors C _s1p1 and C _s1n1 .

Further, the control unit 180 discharges the charges charged in the second capacitors C _s1p2 and C _s1n2 to the analog integrator 130 at the second timing of the conversion cycle (the signal φi2 has a high potential). Then, the control unit 180 starts the charging operation of the next analog input signal of the second capacitors C _s1p2 and C _{s1n2 at} the third timing of the conversion cycle.

That is, the control unit 180 _{supplies the} second capacitors C _s1p2 and C _s1n2 with a control signal φt2 having a low potential at the first timing and a high potential at the third timing. Further, the control unit 180 supplies the control signals φi2 having a high potential at the second timing and a low potential at the third timing to the first capacitors C _s1p1 and C _s1n1 .

As described above, the control unit 180 starts charging in the next tracking cycle from the switched capacitors that have finished discharging while sequentially discharging the charges charged in the tracking cycle by the plurality of switched capacitors in the conversion cycle. This allows most of the plurality of switched capacitors to substantially extend the tracking period. For example, the tracking cycle Tt1 of the first capacitors C _s1p1 and C _s1n1 can be started from the second timing of the conversion cycle.

Here, for example, it is assumed that the tracking cycle Tt described with reference to FIG. 5 and the time interval Td for discharging the electric charge of each capacitor are substantially the same (Tt = Td). The time interval for discharging the electric charge of each capacitor is the time interval at which each of the signals φij in FIGS. 5 and 6 has a high potential. Then, it is assumed that the conversion cycle Tc is substantially the same as the time interval (Tc = m · Td) at which the discharge of m switched capacitors ends. In this case, the tracking cycle Tt1 of the first capacitors C _s1p1 and C _s1n1 shown in FIG. 6 is calculated as Td + (m-1) · Td = m · Td = m · Tt, and the tracking cycle Tt shown in FIG. It can be seen that it can be increased m times as compared with.

Similarly, it can be seen that the tracking cycle Tt2 of the second capacitors C _s1p2 and C _s1n2 can be Td + (m-2) · Td, and the tracking cycle can be increased (m-1) times. As described above, the incremental delta-sigma AD converter 100 according to the present embodiment can _multiply the tracking period of the capacitors C _s1pj and C _s1nj by (m−j + 1) times. As a result, the sample hold unit 110 can lengthen the drive time for capturing the analog input signal into the switched capacitor and reduce the amount of charge (that is, current) to be transferred per unit time.

FIG. 7 shows a second example of a signal waveform when the control unit 180 according to the present embodiment controls to reduce the power consumption of the incremental delta-sigma AD converter 100. Similar to the signal waveform shown in FIG. 5, FIG. 7 shows the time in the horizontal direction and the peak value in the vertical direction. Further, in FIG. 7, the tracking cycle is indicated by “tracking” and the conversion cycle is indicated by “conversion”, as in FIG.

FIG. 7 shows an example in which the control unit 180 executes the same operation as that described with reference to FIG. 5 except for the operation of the sample hold unit 110, as in FIG. Therefore, except for the signal waveforms of the control signals φt1, φt2, ..., Φtm supplied by the control unit 180 to each of the m switched capacitors, the signal waveforms are substantially the same as those of FIGS. 5 and 6. The explanation is omitted.

FIG. 7 shows an example in which the control unit 180 starts the charging operation of two or more switched capacitors among the plurality of switched capacitors whose transfer operation has been completed at the same timing in the conversion cycle. For example, the control unit 180 sets the control signals φtj + 1, φtj + 2, ..., Φtm supplied to the j + 1st to mth capacitors of the sample hold unit 110 to be substantially the same control signal φt. Here, the control signal φt may be substantially the same signal as the control signal φt described with reference to FIG.

Further, FIG. 7 shows an example in which the control unit 180 starts the charging operation of the remaining part of the plurality of switched capacitors whose transfer operation has been completed at different timings in the conversion cycle. For example, the control unit 180 converts the control signals φt1, φt2, ..., Φtj to be supplied to the first to jth capacitors of the sample hold unit 110 to the control signals φt1, φt2, ... The signal is substantially the same as φtj.

In this way, the incremental delta-sigma AD converter 100 of the second example increases the tracking cycle of the first to jth switched capacitors, for example, and makes the control signals of the j + 1th and subsequent switches substantially the same signal φt. To. As a result, the incremental delta-sigma AD converter 100 can simplify the circuit configuration while reducing the power consumption by increasing the tracking cycle.

Here, the switched capacitor that terminates the transfer of electric charges to the analog integrator 130 at a relatively early stage of the conversion cycle has a great effect of increasing the tracking cycle by controlling after the transfer. Therefore, it is desirable that the control unit 180 controls the switched capacitor that terminates the charge transfer at the initial stage so as to start the tracking cycle earlier. On the other hand, the switched capacitor that ends the transfer of electric charge to the analog integrator 130 in the latter half of the conversion cycle reduces the effect of increasing the tracking cycle. Therefore, the control unit 180 may simplify the control operation by starting the tracking cycle Tt after the conversion cycle Tc ends for the switched capacitor that finishes the charge transfer in the latter half of the conversion cycle.

FIG. 8 shows a third example of a signal waveform when the control unit 180 according to the present embodiment controls to reduce the power consumption of the incremental delta-sigma AD converter 100. FIG. 8 shows the time in the horizontal direction and the peak value in the vertical direction, similar to the signal waveform shown in FIG. Further, in FIG. 8, similarly to FIG. 5, the tracking cycle is indicated by “tracking” and the conversion cycle is indicated by “conversion”.

FIG. 8 shows an example in which the control unit 180 executes an operation similar to the operation described with reference to FIG. 5 except for the operation of the sample hold unit 110, similarly to FIGS. 6 and 7. Therefore, the signal waveforms of FIGS. 5, 6, and 7 are substantially the same except for the signal waveforms of the control signals φt1, φt2, ..., Φtm supplied by the control unit 180 to each of the m switched capacitors. Therefore, the description is omitted here.

FIG. 8 shows an example in which the control unit 180 starts the charging operation for each part of the plurality of switched capacitors whose transfer operation has been completed at different timings in the conversion cycle. For example, the control unit 180 sets the control signals supplied to the first to jth capacitors of the sample hold unit 110 to substantially the same control signal φt1 (j <m). As a result, the incremental delta-sigma AD converter 100 of the third example can increase the tracking period of the first to jth capacitors to (m−j + 1) · Td.

Further, the control unit 180 sets the control signal supplied to the j + 1st to mth capacitors of the sample hold unit 110 to be substantially the same control signal φt2. Here, the control signal φt2 may be substantially the same signal as the control signal φt described with reference to FIG. As described above, the incremental type delta-sigma AD converter 100 of the third example can simplify the circuit configuration while reducing the power consumption by using the two control signals.

The signal waveform shown in FIG. 8 shows an example in which the control unit 180 divides a plurality of switched capacitors into two groups and controls the timing of starting charging for each group. The incremental delta-sigma AD converter 100 according to the present embodiment is not limited to this, and may be divided into more groups. That is, the control unit 180 may divide a plurality of switched capacitors into three or more groups and control the timing at which charging is started for each group.

In the incremental delta-sigma AD converter 100 according to the present embodiment, the example in which the sample hold unit 110 has the same number of switched capacitors as the oversampling ratio N has been described. Instead, the sample hold unit 110 may have a smaller number of switched capacitors as compared to the oversampling ratio N. Even in this case, the power consumption can be reduced by causing the control unit 180 to start the operation of the tracking cycle of at least a part of the switched capacitors in the conversion cycle. An example of the signal waveform in this case is shown below.

FIG. 9 shows a fourth example of a signal waveform when the control unit 180 according to the present embodiment controls to reduce the power consumption of the incremental delta-sigma AD converter 100. FIG. 9 shows the time in the horizontal direction and the peak value in the vertical direction, similar to the signal waveform shown in FIG. Further, FIG. 9 shows the tracking cycle as “tracking” and the conversion cycle as “conversion”, as in FIG.

FIG. 9 shows an example in which the control unit 180 executes an operation similar to the operation described with reference to FIG. 5 except for the operation of the sample hold unit 110, similarly to FIGS. 6 to 8. Therefore, except for the control signals φt1, φt2, ..., Φtl supplied by the control unit 180 to each of the l switched capacitors, the signal waveforms are substantially the same as those of FIGS. 5 to 8, and the description thereof is omitted here. (M> l).

Also in the fourth example, the control unit 180 performs the transfer operation with respect to the switched capacitors among the plurality of switched capacitors regardless of the number of the switched capacitors at the clock timing next to the clock timing at which the transfer operation is executed. The charging operation may be started. That is, the control unit 180 generates and supplies different control signals φt1, φt2, ..., Φtl for each of the switched capacitors.

The control unit 180 discharges the electric charges charged in the first capacitors C _s1p1 and C _s1n1 to the analog integrator 130 at the first timing of the conversion cycle, for example. Then, the control unit 180 starts the charging operation of the next analog input signal of the first capacitors C _s1p1 and C _{s1n1 at} the second timing of the conversion cycle. That is, the control unit 180 supplies the control signal φt1 having a low potential at the first timing and a high potential at the second timing to the first capacitors C _s1p1 and C _s1n1 .

Further, the control unit 180 discharges the electric charges charged in the second capacitors C _s1p2 and C _s1n2 to the analog integrator 130 at the second timing of the conversion cycle. Then, the control unit 180 starts the charging operation of the next analog input signal of the second capacitors C _s1p2 and C _{s1n2 at} the third timing of the conversion cycle. That is, the control unit 180 _{supplies the} second capacitors C _s1p2 and C _s1n2 with a control signal φt2 having a low potential at the first timing and a high potential at the third timing.

As described above, the control unit 180 may execute the same operation as the control signal for up to l switched capacitors among the controls for m switched capacitors described with reference to FIG. As a result, the power consumption in the sample hold unit 110 can be reduced. Further, the control operation of the control unit 180 for l switched capacitors is not limited to the operation described with reference to FIG. As described with reference to FIGS. 7 and 8, the control unit 180 may share a control signal for some switched capacitors.

When the discharge operation of the l switched capacitors is completed, the tracking cycle for all the switched capacitors is started. Therefore, the control unit 180 may advance the start time of the next conversion cycle. That is, the control unit 180 may make one conversion cycle shorter. At least a part of the control unit 180 and / or the digital calculation unit 30 may be composed of a computer or the like.

The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. Blocks in flowcharts and block diagrams may be represented as (1) the stage of the process in which the operation is performed or (2) the "part" of the device responsible for performing the operation. Specific stages and "parts" are supplied with dedicated circuits, programmable circuits supplied with computer-readable instructions stored on computer-readable storage media, and / or with computer-readable instructions stored on computer-readable storage media. It may be implemented by the processor.

The dedicated circuit may include digital and / or analog hardware circuits, and may also include integrated circuits (ICs) and / or discrete circuits. Programmable circuits include, for example, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc., such as logical sums, exclusive logical sums, negative logical products, negative logical sums, and other logical operations, flip-flops. , Registers, and reconfigurable hardware circuits, including memory elements.

The computer-readable storage medium may include any tangible device capable of storing instructions executed by the appropriate device. Thereby, the computer-readable storage medium having the instructions stored in the tangible device comprises a product containing instructions that can be executed to create means for performing the operation specified in the flowchart or block diagram. become. Examples of computer-readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like.

More specific examples of computer-readable storage media include floppy (registered trademark) disks, diskettes, hard disks, random access memory (RAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM or flash memory). , Electrically Erasable Programmable Read Only Memory (EEPROM), Static Random Access Memory (SRAM), Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD), Blu-ray® Disc, Memory Stick , Integrated circuit card, etc. may be included.

Computer-readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, and the like. Computer-readable instructions also include object-oriented programming languages such as Smalltalk, JAVA®, C ++, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages. It may include source code or object code written in any combination of multiple programming languages.

Computer-readable instructions are used locally or via a local area network (LAN), wide area network (WAN) such as the Internet, etc., for general purpose computers, special purpose computers, or processors of other programmable data processing devices. Alternatively, it may be provided in a programmable circuit. This allows a general purpose computer, a special purpose computer, or the processor of another programmable data processing unit, or a programmable circuit, to create a means for performing an operation specified in a flowchart or block diagram. Can execute computer-readable instructions. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, and the like.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

The order of execution of operations, procedures, steps, steps, etc. in the devices, systems, programs, and methods shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first," "next," etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 input terminal, 20 incremental delta sigma AD modulator, 30 digital arithmetic unit, 40 output terminal, 100 incremental delta sigma AD converter, 110 sample hold unit, 120 adder unit, 130 analog integrator unit, 140 feed forward unit, 150 Quantization unit, 160 DA conversion unit, 162 1st switch unit, 164 2nd switch unit, 166 3rd switch unit, 170 reset unit, 180 control unit, 210 1st analog integrator, 212 1st analog amplifier, 214 Positive side reset switch, 216 Negative side reset switch, 220 2nd analog integrator, 222 2nd analog amplifier, 224 Positive side reset switch, 226 Negative side reset switch, 230 3rd analog integrator, 232 3rd analog amplifier, 234 Positive side reset switch, 236 negative side reset switch, 240 1st switched capacitor, 242 front switch, 244 rear switch, 245 2nd switched capacitor, 246 front switch, 248 back switch, 250 1st feed forward part, 252 1st FF switch , 260 2nd feed forward section, 262 2nd FF switch, 270 3rd feed forward section, 272 3rd FF switch, 280 4th feed forward section, 282 4th FF switch

Claims (13)

A sample hold unit that has multiple switched capacitors and samples the input signal,
An analog integrator that has an analog integrator and integrates an analog signal based on the input signal sampled by the sample hold unit, and an analog integrator.
A quantization unit that quantizes the output signal of the analog integration unit,
A control unit that charges the plurality of switched capacitors with the input signals in a predetermined tracking cycle and sequentially transfers the charges charged in the plurality of switched capacitors to the analog integrating unit in a predetermined conversion cycle.
With
In the conversion cycle, the control unit performs the charging operation of the input signal for the next tracking cycle for at least one switched capacitor among the plurality of switched capacitors from the at least one switched capacitor to the analog integrating unit. An incremental delta-sigma AD modulator that is started after the transfer operation to is completed. The incremental type according to claim 1, wherein the control unit sequentially starts the charging operation for the next tracking cycle for each of the plurality of switched capacitors in the conversion cycle after the transfer operation is completed. Delta sigma AD modulator. In the conversion cycle, the control unit starts the charging operation of two or more switched capacitors among the plurality of switched capacitors whose transfer operation has been completed at the same timing, and performs the remaining charging operation of a part of the switched capacitors. The incremental delta-sigma AD modulator according to claim 1, which is started at different timings. The incremental delta-sigma AD modulation according to claim 1, wherein the control unit starts the charging operation for each part of the plurality of switched capacitors whose transfer operation has been completed in the conversion cycle. vessel. The control unit starts the charging operation of the switched capacitor that starts the charging operation among the plurality of switched capacitors at the clock timing next to the clock timing at which the transfer operation is executed. 3. The incremental delta-sigma AD modulator according to 3. The incremental delta-sigma AD modulator according to any one of claims 1 to 5, further comprising a reset unit that resets the integrated value held by the analog integrating unit in a predetermined first cycle. The plurality of switched capacitors output the sampling result of N times in the first cycle.
The incremental delta-sigma AD modulator according to claim 6, wherein the first cycle is the sum of the tracking cycle and the conversion cycle. The incremental delta-sigma AD modulator according to claim 7, wherein the sample hold unit has an oversampling ratio N, which is the ratio of the number of samples to the first period, and the same number of switched capacitors. The incremental delta-sigma AD modulator according to claim 7, wherein the sample holding unit has a small number of switched capacitors as compared with an oversampling ratio N which is a ratio of the number of samples to the first period. A DA conversion unit that DA-converts the output of the quantization unit and outputs a feedback signal that feeds back to the analog integration unit.
An addition unit that adds the feedback signal to the output of the sample hold unit and supplies it as the analog signal to the analog integration unit.
The incremental delta-sigma AD modulator according to any one of claims 1 to 9. The incremental delta-sigma AD modulator according to any one of claims 1 to 10, wherein the analog integrator has a plurality of the analog integrators. The incremental delta-sigma AD modulator according to any one of claims 1 to 11, further comprising a feedforward unit that transmits the input signal to the quantization unit. The incremental delta-sigma AD modulator according to any one of claims 1 to 12.
A digital arithmetic unit that filters the output of the quantization unit, and
Incremental type delta-sigma AD converter equipped with.

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