JP6823478B2 - Incremental delta-sigma AD converter and adjustment method - Google Patents

Description

The present invention relates to an incremental delta-sigma AD converter and an adjustment method.

Conventionally, in an AD converter having a plurality of integrating circuits and converting an analog signal into a digital signal, an incremental delta-sigma AD converter that resets the electric charge accumulated in the integrating circuit at a predetermined time interval is known. (See, for example, Patent Document 1).
Patent Document 1 International Publication No. 2013/136676

Since such an incremental type delta-sigma AD converter outputs digitally converted digital data in a cycle of resetting the electric charge accumulated in the integrating circuit, the cycle is one conversion cycle. If the performance and cost are the same, it is desirable that the conversion speed of the AD converter is high, and it is hoped that the conversion speed of the incremental delta-sigma AD converter will be improved while maintaining the cost, resolution, accuracy, etc. It was rare.

In the first aspect of the present invention, a delta-sigma converter that outputs a delta-sigma-modulated modulated digital signal of an input analog signal and a digital that outputs a digital signal obtained by filtering the modulated digital signal as an AD conversion result of the analog signal. A filter unit is provided, and the digital filter unit provides an incremental delta-sigma AD converter and an adjustment method for switching from a first operation for integrating a modulated digital signal to a second operation for calculating a weighted sum of modulated digital signals. To do.

The outline of the above invention does not list all the necessary features of the present invention. Sub-combinations of these feature groups can also be inventions.

An example of a block diagram of the incremental delta-sigma AD converter 10 according to the present embodiment is shown. A configuration example of the analog integrator 130 according to the present embodiment is shown. A first example of the timing chart of the incremental delta-sigma AD converter 10 according to the present embodiment is shown. A second example of the timing chart of the incremental delta-sigma AD converter 10 according to the present embodiment is shown. A modification of the incremental delta-sigma AD converter 10 according to the present embodiment is shown. A configuration example of the sample hold unit 110 and the DA conversion unit 160 according to the present embodiment is shown. A configuration example of the feedforward unit 140 according to the present embodiment is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions claimed in the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 shows an example of a block diagram of the incremental delta-sigma AD converter 10 according to the present embodiment. The incremental type delta-sigma AD converter 10 converts the analog signal A _in input from the input terminal 12 into a digital signal D _out and outputs it from the output terminal 14 while resetting the internal circuit. The incremental type delta-sigma AD converter 10 improves the speed of conversion into a digital signal D _out by switching the calculation operation of the digital filter. The incremental type delta-sigma AD converter 10 includes an input terminal 12, an output terminal 14, a delta-sigma conversion unit 100, and a digital filter unit 190.

The input terminal 12 inputs an input analog signal A _in . The input terminal 12 may be a single-ended input, and may be a differential input instead. When the input terminal 12 is a differential input, the input terminal 12 receives a positive signal A _inp from the positive input and a negative signal A _inn from the negative input. The input terminal 12 supplies the input input signal A _in to the delta-sigma conversion unit 100.

The output terminal 14 outputs the digital signal D _OUT converted by the incremental delta-sigma AD converter 10 _in response to the input analog signal A _in . The output terminal 14 may be a single-ended output, and may be a differential output instead.

The delta-sigma conversion unit 100 outputs a modulated digital signal Y obtained by delta-sigma-modulating the input analog signal A _in . The delta-sigma conversion unit 100 includes an addition unit 120, an analog integration unit 130, a quantization unit 150, a DA conversion unit 160, a reset unit 170, and a control unit 180.

The addition unit 120 adds a feedback signal from the DA conversion unit to the input signal A _in input from the input terminal 12. When the input terminal 12 is a differential input, the addition unit 120 may add feedback signals having different symbols to the positive side signal A _imp and the negative side signal A _imp of the differential signal. The addition unit 120 supplies the addition result to the analog integration unit 130.

The analog integrator 130 includes an analog integrator and integrates the output of the adder 120. The analog integrator 130 may include a plurality of vertically connected analog integrators. The analog integrating unit 130 supplies the integrated result as an output signal V _out (i) to the quantization unit 150.

The quantization unit 150 quantizes the output signal V _out (i) of the analog integration unit 130. The quantization unit 150 quantizes the integration result of the analog integration unit 130 according to a clock signal or the like supplied from the outside, and outputs a bit stream according to the integration result. The quantizer 150 may function as a 1-bit quantizer or a multi-bit quantizer. That is, the quantization unit 150 may quantize the output signal V _out (i) of the analog integration unit 130 into a binary or multi-valued digital signal.

For example, when a 1-bit quantizer is used as the quantization unit 150, the bit stream is a sequence (serial digital code) of a predetermined number of 1-bit data (digital codes), and the digital codes are integrated. The value becomes a digital value that is proportional to or substantially matches the amplitude value of the input signal A _in . The quantization unit 150 compares the output signal V _out (i) and a predetermined threshold value for each clock signal, and sets the output signal V _out (i) to 1 or 1 or not depending on whether or not the threshold value is exceeded. It may be converted to a digital code of 0.

Further, for example, when an M-bit quantizer is used as the quantization unit 150, the bit stream is a sequence (serial digital code) of a predetermined number of M-bit data (digital codes), and the digital code is used. The integrated value becomes a digital value that is proportional to or substantially matches the amplitude value of the input signal A _in . The quantization unit 150 compares the output signal V _out (i) and a predetermined M-bit threshold with a comparator for M bits for each clock signal, and determines whether or not each comparator exceeds the threshold. Correspondingly, the output signal V _out (i) may be converted into an M-bit digital code.

That is, the incremental type delta sigma AD converter 10 converts the input signal A _in into a digital value at a constant conversion cycle, but the quantization unit 150 is a clock signal supplied from the outside, which is faster than one conversion cycle. Etc., the serial digital code corresponding to the input signal A _in is output. In this way, the input signal A _in is converted into a digital value for each of the plurality of samples synchronized with the clock signal, and the number of samples per conversion cycle is used as the oversampling ratio. That is, the number of digital codes included in the serial digital code is equal to the oversampling ratio.

For example, when the oversampling ratio of the incremental delta-sigma AD converter 10 is 60, the quantization unit 150 outputs a serial digital code including 60 digital codes in each conversion cycle. The quantization unit 150 supplies the quantized digital signal Y as a modulated digital signal to the DA conversion unit 160 and the digital filter unit 190.

The DA conversion unit 160 outputs a feedback signal based on the output of the quantization unit 150. The DA conversion unit 160 DA-converts the digital signal Y output by the quantization unit 150 into a corresponding analog signal, and supplies the converted analog signal as a feedback signal to the addition unit 120. The feedback signal may be a predetermined reference voltage. The feedback signal will be described later. The DA conversion unit 160 may convert the digital signal Y into an analog signal in synchronization with the clock signal.

The reset unit 170 resets the integrated value held by the analog integrating unit 130 at predetermined intervals. Further, the reset unit 170 may also reset the digital filter unit 190 at the timing of resetting the analog integration unit 130. The reset unit 170 may reset the analog integrator unit 130 and the digital filter unit 190 each time the incremental type delta-sigma AD converter 10 converts the input signal A _in into a digital value. As an example, the reset unit 170 supplies a reset signal to the analog integrator unit 130 and the digital filter unit 190 for each conversion cycle to a digital value to reset each.

The control unit 180 controls the operation of the incremental delta-sigma AD converter 10. The control unit 180 controls, for example, the operations of the analog integration unit 130 and the digital filter unit 190. The control unit 180 may execute a control operation of each unit according to a clock signal or the like supplied from the inside or the outside. Further, the control unit 180 may have a clock oscillator and execute control operations of each unit.

The digital filter unit 190 outputs a digital signal obtained by filtering the modulated digital signal output by the quantization unit 150 as an AD conversion result of the input analog signal. The digital filter unit 190 may output a filtered digital signal at predetermined intervals. The digital filter unit 190 filters and outputs the digital signal Y received from the quantization unit 150. The digital filter unit 190 may function as an integration filter for digital integration by the first calculation for integrating the bit stream of the digital signal Y. In this case, the digital filter unit 190 may calculate the digital value by multiplying the integrated value by a predetermined coefficient.

Further, the digital filter unit 190 may function as an arithmetic filter for digital integration by the second arithmetic for calculating the weighted sum of the bitstream of the digital signal Y. The digital filter unit 190 may switch from the first calculation of integrating the modulated digital signals to the second calculation of calculating the weighted sum of the modulated digital signals. The digital filter unit 190 may calculate a digital value in synchronization with the clock signal. Further, the digital filter unit 190 may reset the integrated amount in response to receiving the reset signal from the reset unit 170.

Further, the digital filter unit 190 may have a low-pass filter to reduce the quantization noise generated in the quantization unit 150. Further, the digital filter unit 190 may have a decimation filter to reduce the sampling frequency. The digital filter unit 190 supplies the digital value of the calculation result to the output terminal 14. The output terminal 14 outputs the received digital value as the digital output D _OUT of the incremental delta-sigma AD converter 10.

As described above, the incremental type delta-sigma AD converter 10 according to the present embodiment resets the analog integrating unit 130 and the digital filter unit 190 by the reset unit 170, and converts the input signal A _{in to} the digital output. Repeat in synchronization with the clock signal. The incremental delta-sigma AD converter 10 may operate as a delta-sigma AD converter if there is no reset operation by the reset unit 170.

FIG. 2 shows a configuration example of the analog integrator 130 according to the present embodiment. FIG. 2 shows an example in which a differential signal from the addition unit 120 by the positive signal SP and the negative signal SN is input to the analog integration unit 130. The analog integrator 130 has a plurality of analog integrators and a plurality of switched capacitors. The analog integrator 130 shown in FIG. 2 shows an example having three analog integrators of a first analog integrator 210, a second analog integrator 220, and a third analog integrator 230. Further, the analog integrator 130 shows an example having two switched capacitors, a first switched capacitor 240 and a second switched capacitor 245.

Further, FIG. 2 shows an example in which each of the three analog integrators has two input terminals and two output terminals, respectively, and inputs a differential signal to output the differential signal. One of the two input terminals of the analog integrator is the first input terminal, and the other is the second input terminal. Further, one of the two output terminals of the analog integrator is used as the first output terminal, and the other is used as the second output terminal.

The analog integrator includes an analog amplifier, a feedback capacitor, and a reset switch, respectively. FIG. 2 shows an example in which the first analog integrator 210 includes a first analog amplifier 212, a positive feedback capacitor C _i1p , a negative feedback capacitor C _i1n , a positive reset switch 214, and a negative reset switch 216. Further, the second analog integrator 220 includes a second analog amplifier 222, a positive feedback capacitor C _i2p , a negative feedback capacitor C _i2n , a positive reset switch 224, and a negative reset switch 226, and also includes a third analog. An example is shown in which the integrator 230 includes a third analog amplifier 232, a positive feedback capacitor C _i3p , a negative feedback capacitor C _i3n , a positive reset switch 234, and a negative reset switch 236.

The analog amplifier amplifies and outputs the signals input to the positive input terminal and the negative input terminal, respectively. The analog amplifier is, for example, a differential input type amplifier circuit. Further, the analog amplifier may have a single-ended output, and instead, a differential output may be used. The analog amplifier is, for example, an OP amplifier. FIG. 2 shows an example in which three analog integrators, a first analog amplifier 212, a second analog amplifier 222, and a third analog amplifier 232, include differential input and differential output analog amplifiers, respectively. In FIG. 2, the positive input terminal of the analog amplifier is connected to the first input terminal of the analog integrator, and the negative input terminal is connected to the second input terminal.

Each of the feedback capacitors sequentially accumulates charges according to the input signal. The feedback capacitor sequentially accumulates electric charges from the front stage to the rear stage for each sampling, for example. As an example, the electric charge accumulated in the positive feedback capacitor C _i1p in the first clock according to the positive signal SP is accumulated in the positive feedback capacitor C _i2p in the next second clock, and is accumulated in the positive feedback capacitor C _i2p in the next third clock. It is stored in the positive feedback capacitor _Ci3p . Similarly, according to the negative signal SN, the electric charge accumulated in the negative feedback capacitor C _i1n in the first clock is accumulated in the negative feedback capacitor C _i2n in the next second clock, and is accumulated in the negative feedback capacitor C _i2n in the next third clock. It is stored in the negative feedback capacitor _Ci3n .

The reset switch discharges the electric charge accumulated in the feedback capacitor and resets each of the analog integrators in response to an instruction from the reset unit 170. The reset switch connects between the terminals of the feedback capacitor in response to the reset signal supplied from the reset unit 170, and discharges the accumulated electric charge, for example. In the example of FIG. 2, in response to an instruction from the reset unit 170, the positive reset switch 214, the negative reset switch 216, the positive reset switch 224, the negative reset switch 226, the positive reset switch 234, and the negative reset The switches 236 are each switched on to reset the first analog amplifier 212, the second analog amplifier 222, and the third analog amplifier 232.

The switched capacitors are provided between the analog integrators and transfer the charges accumulated in the analog integrators connected to the previous stage to the analog integrators connected to the subsequent stages. The switched capacitor includes a capacitor for charging and discharging and switches provided in the front and rear stages of the capacitor. The front-stage switch switches the connection destination of one terminal of the capacitor to either the pre-stage circuit of the switched capacitor or the reference potential. The subsequent switch switches the connection destination of the other terminal of the capacitor to either the subsequent circuit of the switched capacitor or the reference potential. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

In a switched capacitor, for example, in one clock, one terminal of the capacitor is connected to the analog integrator of the previous stage, and the other terminal of the capacitor is connected to the reference potential, so that the analog integrator connected to the previous stage The capacitor charges the output charge. In this case, in the next clock, the switched capacitor charges the charge charged by the capacitor by connecting one terminal of the capacitor to the reference potential and connecting the other terminal of the capacitor to the analog integrator in the subsequent stage. Discharge to the analog integrator of.

FIG. 2 shows an example in which the first switched capacitor 240 is connected between the first analog integrator 210 and the second analog integrator 220. The first switched capacitor 240 uses the front switch 242 and the rear switch 244 to charge the charge accumulated in the front feedback capacitor C _i1p in the front stage by the capacitor C _s2p to the positive feedback capacitor C _{i2p in the} rear stage. Is discharged and transmitted. In this case, similarly, the first switched capacitor 240, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _I1n, capacitor C _s2n is charged, and discharged to the subsequent negative feedback capacitor C _i2n To do.

Further, FIG. 2 shows an example in which the second switched capacitor 245 is connected between the second analog integrator 220 and the third analog integrator 230. Second switched capacitor 245, using the primary switch 246 and secondary switch 248, the charge accumulated in front of the positive-side feedback capacitor _{C i2p,} capacitor _{C S3P} is charged, to the subsequent positive feedback capacitor _{C I3P} Is discharged and transmitted. In this case, likewise, the second switched capacitor 245, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _i2n, capacitor C _S3N are charged, and discharged to the subsequent negative feedback capacitor C _I3n To do.

As described above, in the analog integrator 130, a plurality of analog integrators are connected in series, and the positive signal SP and the negative signal SN are charged from the analog integrator in the previous stage to the analog integrator in the rear stage for each clock. Are sequentially accumulated and transmitted. The analog integrator 130 outputs the charge accumulated in the feedback capacitor of the analog integrator at the latest stage to the quantization unit 150.

For example, since the analog integrator 130 shown in FIG. 2 has a three-stage analog integrator, the charge accumulated in the first analog integrator 210 in the first clock is transferred to the third analog integrator 230 in the third clock. It is transmitted and output to the quantization unit 150. Further, as will be described later, when the analog integrator 130 has a feedforward unit, the analog integrator in the latter stage outputs to the quantization unit 150 via the feedforward unit.

Further, the control unit 180 supplies a control signal to the analog integration unit 130 to execute such an operation of the analog integration unit 130. As an example, the control unit 180 has a clock oscillator that generates a clock signal having a predetermined frequency, and supplies the clock signal to the analog integration unit 130. Further, the control unit 180 may stop the supply of the clock signal to the analog integration unit 130 to stop the integration operation of the analog integration unit 130.

Note that FIG. 2 has described an example in which the analog integrator 130 has three analog integrators, but instead, the analog integrator 130 may have two or four or more analog integrators. Good. In this case, one or three or more switched capacitors may be provided in the analog integrator 130 depending on the number of analog integrators.

The incremental delta-sigma AD converter 10 according to the above embodiment integrates an input analog signal, and feedback control adds or subtracts a reference voltage to the input analog signal according to the quantization result of the integration result. To execute. As a result, the incremental type delta-sigma AD converter 10 can accurately output the serial digital code corresponding to the input analog signal. Further, the incremental type delta-sigma AD converter 10 can digitally process such a serial digital code and output a digital signal corresponding to the analog signal with high accuracy.

Unlike the delta-sigma AD converter, the incremental type delta-sigma AD converter 10 discharges and resets the electric charge accumulated in the analog integrator 130 at regular intervals. As a result, the digital value converted in one conversion cycle is made into a more accurately converted value of the analog input signal value without being affected by the electric charge accumulated in a cycle different from that of one conversion cycle. Can be done.

The incremental delta-sigma AD converter 10 of the present embodiment switches from the first calculation in which the digital filter unit 190 integrates the modulated digital signals to the second calculation in which the weighted sum of the modulated digital signals is calculated, whereby the AD conversion result is obtained. Adjust the output timing of. Before explaining such an adjustment operation, first, an operation when the incremental type delta-sigma AD converter 10 executes only the first calculation will be described.

FIG. 3 shows a first example of a timing chart of the incremental delta-sigma AD converter 10 according to the present embodiment. FIG. 3 shows the data processed by each part or the timing signal of each part in the time axis direction.

For example, the signal waveform shown as "CONV CLK" indicates the conversion period of the incremental delta-sigma AD converter 10. As an example, when "CONV CLK" has a high potential, a reset signal is supplied from the reset unit 170 to each unit. Further, when "CONV CLK" has a low potential, the delta-sigma conversion unit 100 and the digital filter unit 190 operate in response to the clock signal, and the AD conversion operation is executed. In the present embodiment, the period during which "CONV CLK" becomes a low potential is defined as the conversion cycle.

The signal waveform indicated by “CLK” in FIG. 3 indicates a clock signal. For example, the analog integration unit 130 starts the integration operation in response to the first clock signal after receiving the reset signal from the reset unit 170, and outputs the integration result V _out (1) after the second clock signal. Begin to.

The data string indicated by “Y” in FIG. 3 indicates a digital signal in which the quantization unit 150 quantizes the integration result V _out (i) of the analog integration unit 130 according to the clock signal. The quantization unit 150 sequentially outputs digital signals to D (1), D (2), ..., From the second clock signal. That is, Y (i) = D (i). Here, FIG. 3 shows an example in which the quantization unit 150 outputs j digital signals in one conversion cycle.

The digital filter unit 190 executes the first operation of integrating (digitally integrating) j digital signals sequentially received from the quantization unit 150. “DIGINT1”, “DIGINT2”, and “DIGINT3” in FIG. 3 show an example of the clock-by-clock integration process of the first calculation executed by the digital filter unit 190. Note that FIG. 3 shows that the analog integrator 130 has three integrators, and three data strings of "DIGINT1", "DIGINT2", and "DIGINT3" are used to perform three digital integrations. An example of doing so is shown.

For example, the data string represented by "DIGINT1" integrates the digital signal output by the quantization unit 150 according to the clock signal. That is, assuming that the data string of "DIGINT1" is I1 (k), I1 (k) can be expressed by the following equation that integrates the digital signal D (k) output by the quantization unit 150. As an example, the initial value I1 (1) = D (1).
(Number 1)
I1 (k) = I1 (k-1) + D (k)

Similarly, the data string indicated by "DIGINT2" integrates the data string indicated by "DIGINT1", and the data string indicated by "DIGINT3" integrates the data string indicated by "DIGINT2". That is, assuming that the data string of "DIGINT2" is I2 (k) and the data string of "DIGINT3" is I3 (k), In (k) can be expressed by the following equation.
(Number 2)
In (k) = In (k-1) + In-1 (k)

Here, n = 2, 3, but the value of n in the equation (Equation 2) may be substantially the same as the number L of integrals possessed by the analog integrating unit 130. That is, the digital filter unit 190 may execute digital integration using L data sequences. Further, the value of k in the equations (Equation 1) and (Equation 2) indicates the number of integrations performed by one digital integration of the digital filter unit 190. FIG. 3 shows an example in which the digital filter unit 190 executes j times of integration in one digital integration in response to the quantization unit 150 outputting j digital signals in one conversion cycle.

In this way, after receiving the reset signal from the reset unit 170, the digital filter unit 190 starts the first calculation at the second clock signal and executes the digital integration L times. Therefore, the digital filter unit 190 calculates the integration result IL (j) at the j + L + 1th clock signal. FIG. 5 shows an example in which the digital filter unit 190 calculates the integration result I3 (j) in the j + 4th clock signal.

The incremental type delta-sigma AD converter 10 outputs the integration result I3 (j) as a digital signal D _OUT from the output terminal 14 as a conversion result of one conversion cycle. The data string indicated by “D _OUT ” in FIG. 3 shows an example of the timing at which the digital signal D _OUT is output. That is, FIG. 3 shows an example in which the incremental delta-sigma AD converter 10 outputs the integration result I3 (j) as the digital signal D _{OUT in} the j + 5th clock signal by the digital filter unit 190 using the first calculation. Shown.

On the other hand, when the digital filter unit 190 uses the first calculation and the second calculation, the incremental type delta-sigma AD converter 10 can adjust the output timing of the integration result I3 (j). For example, the digital filter unit 190 executes a predetermined second calculation instead of the first calculation in the j + 1th and subsequent clock signals to advance the output timing of the integration result.

As an example, the digital filter unit 190 switches from the first timing for finally supplying the modulated digital signal to the digital filter unit 190 as the signal to be filtered by the delta sigma conversion unit 100 to the second calculation, and sets the output timing of the AD conversion result. adjust. Here, the first timing in the example of FIG. 3 corresponds to the timing of the j + second clock signal. That is, the digital filter unit 190 switches to the digital weighted sum at the j + second clock signal. The quantization unit 150 outputs j pieces of data to be integrated in one conversion cycle from D (1) to D (j) in the j + 1th clock signal.

That is, since the digital filter unit 190 can acquire all the data to be integrated in the j + 1th clock signal, the integration result can be calculated in the next j + 2nd clock signal by using an appropriate calculation. As an example, the digital filter unit 190 can calculate the integration result I3 (j) by executing the digital weighted sum shown in the following equation. The following equation shows an example when the number L of the analog integrators of the analog integrator 130 is 3.
(Number 3)
I3 (j) = I3 (j-1) + I2 (j)
= {I3 (j-2) + I2 (j-1)} + {I2 (j-1) + I1 (j)}
= {I3 (j-3) + I2 (j-2)} + 2 {I2 (j-2) + I1 (j-1)}
+ {I1 (j-1) + D (j)}
= I3 (j-3) +3 ・ I2 (j-2) +3 ・ I1 (j-1) + D (j)

As shown in FIG. 3, I3 (j-3), I2 (j-2), I1 (j-1), and D (j) are all acquired by the digital filter unit 190 at the j + 1th clock signal. Since it is a digital value, the equation (Equation 3) can be calculated with the j + second clock signal. FIG. 4 shows an example in which the digital filter unit 190 executes the above calculation.

FIG. 4 shows a second example of the timing chart of the incremental delta-sigma AD converter 10 according to the present embodiment. In the second example of the timing chart shown in FIG. 4, substantially the same operation as that of the first example of the timing chart shown in FIG. 3 is designated by the same reference numerals, and the description thereof will be omitted. The digital filter unit 190 acquires the digital values I3 (j-3), I2 (j-2), I1 (j-1), and D (j) in the j + 1th clock signal. Therefore, the digital filter unit 190 can calculate the result of digital integration of j pieces of data by using the digital weighted sum of the equation (Equation 3). FIG. 4 shows an example in which the digital filter unit 190 outputs the integration result I3 (j) in the j + second clock signal.

The formula (Equation 3) is an example of a weighted sum that can be used when L = 3, and the formula of the weighted sum is different from the formula (Equation 3) depending on the value of L. That is, the digital filter unit 190 sets the weight of the digital weighting unit to the weight corresponding to the number L of the plurality of analog integrators, and accelerates the output timing of the AD conversion result.

The digital filter unit 190 according to the present embodiment described above describes an example in which the first calculation is switched to the second calculation in the j + second clock signal, but the present invention is not limited to this. For example, the digital filter unit 190 may switch to the second operation represented by the following equation at the j + 3rd clock signal.
(Number 4)
I3 (j) = I3 (j-1) + I2 (j)
= {I3 (j-2) + I2 (j-1)} + {I2 (j-1) + I1 (j)}
= I3 (j-2) +2 · I2 (j-1) + I1 (j)

In this way, the digital filter unit 190 can accelerate the output timing of the calculation result of the digital integral by using the digital weighted sum. Therefore, the incremental delta-sigma AD converter 10 according to the present embodiment can output a digital conversion result having substantially the same accuracy as the incremental delta-sigma AD converter 10 shown in FIG. 1 more quickly.

Equations (Equation 3) and (Equation 4) are examples in which the analog integrator 130 has three analog integrators, and the range in which the incremental delta-sigma AD converter 10 can adjust the output timing is 2 clocks. There is no limitation. That is, when the analog integrator 130 has L analog integrators, the incremental delta-sigma AD converter 10 according to the present embodiment can adjust the output timing within the range of the clock number of L-1.

That is, the digital filter unit 190 outputs the AD conversion result at any of the timings from one timing after the first timing to one timing before the output timing when filtering is performed only by the first calculation. Can be output. In this case, as the weight of the weighted sum, a weight corresponding to the number of analog integrators possessed by the analog integrator 130 and the number of clocks to be adjusted is used.

Since such an operation has almost no effect on the cost of the product, the incremental delta-sigma AD converter 10 adjusts the output timing of the conversion result and shortens one conversion cycle without increasing the cost. be able to. That is, according to the incremental delta-sigma AD converter 10 of the present embodiment, high-speed AD conversion can be realized while maintaining cost, resolution, accuracy, and the like.

The above incremental delta-sigma AD converter 10 has described an example of converting an input signal into a digital signal as it is, but the present invention is not limited to this. The incremental delta-sigma AD converter 10 may further include a sample hold unit for sampling the input signal. Further, the incremental type delta-sigma AD converter 10 may be provided with a feedforward circuit so that the digital output of the quantization unit 150 reflects the analog input signal at a higher speed. Such an incremental delta-sigma AD converter 10 will be described below.

FIG. 5 shows a modified example of the incremental delta-sigma AD converter 10 according to the present embodiment. In the incremental delta-sigma AD converter 10 of this modification, substantially the same operation as that of the incremental delta-sigma AD converter 10 shown in FIG. 1 is designated by the same reference numerals, and the description thereof will be omitted. The incremental delta-sigma AD converter 10 further includes a sample hold unit 110 and a feedforward unit 140.

The sample hold unit 110 samples the amplitude value of the input analog signal and holds (holds) the sampled value. The sample hold unit 110 may execute one sampling and hold, one sampling and a plurality of holds, or a plurality of samplings and holds in one conversion cycle. The sample hold unit 110 may repeat sampling and holding in synchronization with a clock signal or the like. Here, it is desirable that the frequency of the clock signal is several to several tens of times higher than the frequency of the input signal. In this case, the sample hold unit 110 oversamples the input analog signal. It will be.

It should be noted that such a clock signal is generated in a clock signal generator provided inside or outside the incremental delta-sigma AD converter 10 and supplied to each part inside the incremental delta-sigma AD converter 10. To. As an example, the control unit 180 supplies such a clock signal. FIG. 5 shows an example _in which the analog signal A _in input by the sample hold unit 110 is sampled and the held value is output. The sample hold unit 110 outputs the held value to the addition unit 120. The sample hold unit 110 will be described later.

The feedforward unit 140 transmits a part of the integration results of each of the plurality of analog integrators to the quantization unit 150. Further, the feedforward unit 140 transmits the input analog signal to the quantization unit 150. The feedforward unit 140 may transmit a part of the output of the plurality of analog integrators and the input analog signal by including the analog output of the analog integrator 130.

For example, consider a case where the delta-sigma conversion unit 100 having the analog integrator 130 shown in FIG. 2 has such a feedforward unit 140. In this case, the output signals INT10P and INT10N of the first analog integrator 210 and the output signals INT20P and INT20N of the second analog integrator 220 are transmitted to the quantization unit 150 by the feedforward unit 140. Such a feedforward unit 140 will be described later.

FIG. 6 shows a configuration example of the sample hold unit 110 and the DA conversion unit 160 according to the present embodiment. The sample hold unit 110 and the DA conversion unit 160 shown in FIG. 6 show a more detailed configuration example of the sample hold unit 110 shown in FIG. Note that FIG. 6 shows an example in which a differential signal is input to the sample hold unit 110.

The sample hold unit 110 includes one or more switched capacitors and samples the input signals AINP and AINN to be input to the incremental delta-sigma AD converter 10. The sample hold unit 110 may include substantially the same number of switched capacitors as the oversampling ratio N. The plurality of switched capacitors have a capacitor C _s1pj , a capacitor C _s1nj, and a changeover switch in the front stage and the rear stage of each capacitor, respectively. In addition, j is a natural number from 1 to m, and m is a value substantially the same as the oversampling ratio N.

The switch in the _previous stage of the capacitor C _s1pj switches one terminal of the capacitor C _s1pj to either an input terminal input by the analog signal AINP or a reference potential. _Further , the switch in the _subsequent stage of the capacitor C _s1pj switches the other terminal of the capacitor C _s1pj to either the reference potential or the addition unit 120. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

Similarly, the switch in the _previous stage of the capacitor C _s1nj switches one terminal of the capacitor C _s1nj to either an input terminal input by the analog signal AINN or a reference potential. _Further , the switch in the _subsequent stage of the capacitor C _s1nj switches the other terminal of the capacitor C _s1nj to either the reference potential or the addition unit 120.

The control unit 180 supplies and controls the signal φt to each of the plurality of switched capacitors of the sample hold unit 110. The control unit 180 connects one terminal of the capacitor C _s1pj to the input terminal AINP and connects the other terminal to the reference potential at the second timing (for example, the signal φt has a high potential) on the positive side. Charges the analog input signal of. In this case, at the second timing, the control unit 180 _connects one terminal of the capacitor C _s1nj to the input terminal AINN and connects the other terminal to the reference potential to charge the analog input signal on the negative side.

In the present embodiment, such a second timing is defined as a tracking cycle. That is, the control unit 180 charges the plurality of switched capacitors with input signals in a predetermined tracking cycle.

Further, the control unit 180 connects the j-th capacitor _Cs1nj to the reference potential at the timing deviated from the tracking cycle by the j-th (the signal φij is a high potential), and connects the other terminal to the addition unit 120. The charged positive analog input signal is sequentially discharged to the analog integrating unit 130. Similarly, the control unit 180 connects the j-th capacitor C _s1pj to the reference potential at the timing deviated from the second timing by the j-th timing, and connects the other terminal to the addition unit 120 to charge the capacitor. The negative analog input signal is sequentially discharged to the analog integrating unit 130.

In the present embodiment, the timing at which the control unit 180 discharges the plurality of switched capacitors is defined as the conversion cycle. That is, the control unit 180 sequentially transfers the charges charged in the plurality of switched capacitors to the analog integration unit 130 in a predetermined conversion cycle. Here, one conversion cycle (first cycle) is the sum of the tracking cycle and the conversion cycle.

Further, the plurality of switched capacitors may execute sampling N times in the first cycle and output the sampling result N times. Further, the sample hold unit 110 may have the same number of switched capacitors as the oversampling ratio N, which is the ratio of the number of samples to the first period. In this case, the N switched capacitors may sequentially execute the charge transfer operation to the analog integrator 130 so as to complete the charge transfer operation within the conversion cycle. The number N of switched capacitors may be the same as the number j of digital signals output by the quantization unit 150 in one conversion cycle.

As an example, the control unit 180 charges a plurality of switched capacitors with analog input signals in the first clock, and transfers the charged analog input signals to the analog integrating unit 130 according to the corresponding clock signals after the first clock. And discharge sequentially. As a result, the sample hold unit 110 can sequentially supply substantially the same analog values sampled by the plurality of switched capacitors in the first clock to the delta-sigma conversion unit 100 as input analog signals after the first clock. it can. That is, even if the analog signal changes at high speed, the sample hold unit 110 can hold the value at one timing and convert it into a digital value.

The DA conversion unit 160 includes a first reference voltage REFP, a second reference voltage REFN, a capacitor C _fbp , a capacitor C _fbn , a first switch unit 162, a second switch unit 164, and a third switch unit 166. Have. The first reference voltage REFP and the second reference voltage REFN output voltages having substantially the same absolute value and opposite polarities. As an example, the first reference voltage REFP outputs a positive voltage, and the second reference voltage REFN outputs a negative voltage.

The first switch unit 162 switches one terminal of the capacitor C _fbp to either the first reference voltage REFP or the reference potential. Further, the first switch unit 162 switches one terminal of the capacitor C _fbn to either the second reference voltage REFN or the reference potential. For example, the signal φs supplies control unit 180 is in the timing of the high-potential, one terminal of the capacitor _{C fbp} connected to a first reference voltage REFP, one terminal of the capacitor _{C fbn} connected to the second reference voltage REFN .. In this case, the timing of the control unit 180 is signal φi is high potential supplied, one terminal of one terminal and the capacitor C _fbn capacitor C _fbp, connected to a reference potential.

The second switch unit 164 switches whether or not to connect the other terminals of the capacitor C _fbp and the capacitor C _fbn to the reference potential. In the second switch unit 164, for example, when the signal φs has a high potential, the other terminals of the capacitor C _fbp and the capacitor C _fbn are connected to the reference potential, and when the signal φi has a high potential, the other terminal and the other terminal Disconnect the electrical connection at the reference potential. The control unit 180 controls the first switch unit 162 and the second switch unit 164 to _connect the capacitor C _fbp and the capacitor C _fbn to the corresponding reference voltage at the timing when the signal φs is at a high potential, respectively, and the reference voltage. And charge the charge according to the capacity of the capacitor.

The third switch unit 166 switches whether or not to connect the other terminals of the capacitor C _fbp and the capacitor C _fbn to the addition unit 120. The third switch unit 166 connects, for example, the other terminals of the capacitor C _fbp and the capacitor C _fbn to the addition unit 120 at the timing when the signal φi has a high potential, and the other terminal at the timing when the signal φs has a high potential. And disconnect the electrical connection of the adder 120. The control unit 180 controls the third switch unit 166 to supply the charges charged to the capacitor C _fbp and the capacitor C _fbn to the addition unit 120 according to the first reference voltage REFP and the second reference voltage REFN, respectively. ..

Further, the third switch unit 166 switches the connection destination of the other terminal of the capacitor C _fbp and the capacitor C _fbn according to the digital signal Y supplied from the quantization unit 150. Here, the addition unit 120, which is the connection destination of the capacitor C _fbp and the capacitor C _fbn , corresponds to the differential signal received from the sample hold unit 110, and feeds back signals to the positive and negative signals of the differential signal, respectively. Has a path to transmit.

For example, when the digital code of the digital signal Y is "0", the third switch unit 166 adds a charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the positive side signal of the differential signal. Switch the connection as follows. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the negative side signal of the differential signal. As an example, when the signal φip becomes a high potential according to the digital code of “0”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the positive signal at that timing. , The other terminal of the capacitor C _fbn is connected to the transmission line of the negative signal.

Further, for example, when the digital code of the digital signal Y is "1", the third switch unit 166 uses the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp as the negative side signal of the differential signal. Switch the connection to add. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the positive side signal of the differential signal. As an example, when the signal φin becomes a high potential according to the digital code of “1”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the negative signal at that timing. , The other terminal of the capacitor C _fbn is connected to the transmission line of the positive signal.

In this way, the DA conversion unit 160 outputs an analog signal corresponding to the positive reference voltage as a feedback signal to the addition unit 120 in response to the digital signal “0” output by the quantization unit 150, and outputs the feedback signal to the addition unit 120. Add to the differential signal. Further, the DA conversion unit 160 outputs an analog signal corresponding to the negative reference voltage to the addition unit 120 as a feedback signal according to the digital signal “1” output by the quantization unit 150, and differentially outputs the feedback signal to the addition unit 120. Add to the signal.

As described above, the control unit 180 controls the sample hold unit 110 and the DA conversion unit 160 to superimpose the feedback signal for adding or subtracting the reference voltage on the input analog signal and supply it to the analog integration unit 130. .. In FIG. 6, the positive side signal supplied from the addition unit 120 to the analog integration unit 130 is SP, and the negative side signal is SN. As described above, the incremental type delta-sigma AD converter 10 is provided with the sample hold unit 110, so that a high-speed analog signal or the like can be sampled and converted into a digital signal.

FIG. 7 shows a configuration example of the feedforward unit 140 according to the present embodiment. The feedforward unit 140 includes a first feedforward unit 250, a second feedforward unit 260, a third feedforward unit 270, and a fourth feedforward unit 280. The feedforward unit 140 may be controlled by the control unit 180.

The first feedforward unit 250 includes one or a plurality of switched capacitors, and transmits the analog signals AINP and AINN input to the incremental delta-sigma AD converter 10 to the quantization unit 150. FIG. 7 shows an example in which the first feedforward unit 250 includes a plurality of switched capacitors. The first feedforward unit 250 may include the same number of switched capacitors as the oversampling ratio N. One switched capacitor included in the first feedforward unit 250 includes, for example, a first FF switch 252, a capacitor C _0ffpj , and a capacitor C _0ffnj . In addition, j was a natural number from 1 to an oversampling ratio N (60 as an example).

The first FF switch 252 switches, for example, one terminal of the capacitor C _0ffpj to either an input terminal or a reference potential input by the analog signal AINP according to the control signal of the control unit 180. _Further, the other terminal of the capacitor C _0ffpj is connected to the quantization unit 150. As an example, the capacitor C _0ffpj has one terminal connected to the input terminal at the second timing to charge the analog input signal. Then, one terminal of the capacitor C _0ffpj is connected to the reference potential at the timing deviated from the second timing by the jth timing, and the charged analog input signal is discharged to the quantization unit 150.

Similarly, the first FF switch 252 switches one terminal of the capacitor C _0ffnj to either an input terminal input by the analog signal AINN or a reference potential according to the control signal of the control unit 180. At the second timing, one terminal of the capacitor C _0ffnj is connected to the input terminal to charge the analog input signal. Then, one terminal of the capacitor C _0ffnj is connected to the reference potential at the timing deviated from the second timing by the jth timing, and the charged analog input signal is discharged to the quantization unit 150. That is, each of the plurality of switched capacitors charges the analog input signal in the first clock, and sequentially discharges the charged analog input signal to the quantization unit 150 according to the corresponding clock signals after the first clock.

The second feedforward unit 260 includes a switched capacitor, and transmits signals output by the first analog integrator 210 (for example, INT10P and INT10N) to the quantization unit 150. The second feedforward unit 260 includes, for example, a second FF switch 262, a capacitor C 1 _fpp , and a capacitor C 1 _fpn .

The second FF switch 262 has one terminal of the capacitor C _{1ffp on} the positive side according to the control signal of the control unit 180, and one of the first output terminal and the reference potential at which the first analog integrator 210 outputs the signal INT10P. Switch to. _Further, the other terminal of the capacitor C _1ffp is connected to the quantization unit 150. For example, in the first clock of the capacitor C _1ffp , one terminal is connected to the output terminal to charge the signal INT10P. Then, in the second clock, one terminal of the capacitor C _1fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the second FF switch 262 has one terminal of the negative capacitor C _1ffn according to the control signal of the control unit 180, the second output terminal where the first analog integrator 210 outputs the signal INT10N, and the reference potential. Switch to one of. _Further, the other terminal of the capacitor C _1ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _1ffn is connected to the output terminal to charge the signal INT10N. Then, in the second clock, one terminal of the capacitor C _1ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

The third feedforward unit 270 includes a switched capacitor, and transmits signals output by the second analog integrator 220 (for example, INT20P and INT20N) to the quantization unit 150. The third feedforward unit 270 includes, for example, a third _FF switch 272, a capacitor C _2ffp , and a capacitor C _2ffn .

The third FF switch 272 is one of the first output terminal and the reference potential at which the second analog integrator 220 outputs the signal INT20P to one terminal of the capacitor C _{2fp on} the positive side according to the control signal of the control unit 180. Switch to. _Further, the other terminal of the capacitor C _2fp is connected to the quantization unit 150. For example, in the first clock of the capacitor C _2fp , one terminal is connected to the output terminal to charge the signal INT 20P. Then, in the second clock, one terminal of the capacitor C _2fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the third FF switch 272 has one terminal of the negative capacitor C _2ffn according to the control signal of the control unit 180, and the second output terminal and the reference potential at which the second analog integrator 220 outputs the signal INT20N. Switch to one of. _Further, the other terminal of the capacitor C _2ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _2ffn is connected to the output terminal to charge the signal INT20N. Then, in the second clock, one terminal of the capacitor C _2ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

The fourth feedforward unit 280 includes a switched capacitor, and transmits signals output by the third analog integrator 230 (for example, INT30P and INT30N) to the quantization unit 150. The fourth feedforward unit 280 includes, for example, a fourth _FF switch 282, a capacitor C _3ffp , and a capacitor C _3ffn .

The fourth FF switch 282 has one terminal of the capacitor C _{3ffp on} the positive side according to the control signal of the control unit 180, and one of the first output terminal and the reference potential at which the third analog integrator 230 outputs the signal INT30P. Switch to. _Further, the other terminal of the capacitor C _3fp is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _3fp is connected to the output terminal to charge the signal INT30P. Then, in the second clock, one terminal of the capacitor C _3fp is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

Similarly, the fourth FF switch 282 has one terminal of the negative capacitor C _3ffn according to the control signal of the control unit 180, the second output terminal where the third analog integrator 230 outputs the signal INT30N, and the reference potential. Switch to one of. _Further, the other terminal of the capacitor C _3ffn is connected to the quantization unit 150. For example, in the first clock, one terminal of the capacitor C _3ffn is connected to the output terminal to charge the signal INT30N. Then, in the second clock, one terminal of the capacitor C _3ffn is connected to the reference potential, and the charged signal is discharged to the quantization unit 150.

As an example, the control unit 180 charges the second feedforward unit 260, the third feedforward unit 270, and the fourth feedforward unit 280 at the timing when the signal φi has a high potential, and the signal φs. The discharge operation is executed at the timing of high potential. As described above, the feedforward unit 140 uses the signal input to the incremental delta-sigma AD converter 10 and the signal output by the analog integrator of the analog integrator 130 as feedforward signals in the quantization unit. Communicate to 150. With such a feedforward signal, the digital code output by the quantization unit 150 for each clock can be made to reflect the analog input signal at a higher speed.

The feedforward unit 140 according to the present embodiment is not limited to such a feedforward operation. For example, the feedforward section 140 has a structure having at least one of a first feedforward section 250, a second feedforward section 260, a third feedforward section 270, and a fourth feedforward section 280.

The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. Blocks in flowcharts and block diagrams may be represented as (1) the stage of the process in which the operation is performed or (2) the "part" of the device responsible for performing the operation. Specific stages and "parts" are supplied with dedicated circuits, programmable circuits supplied with computer-readable instructions stored on computer-readable storage media, and / or with computer-readable instructions stored on computer-readable storage media. It may be implemented by the processor.

Specific stages and "parts" are supplied with dedicated circuits, programmable circuits supplied with computer-readable instructions stored on computer-readable storage media, and / or with computer-readable instructions stored on computer-readable storage media. It may be implemented by the processor. The dedicated circuit may include a digital and / or analog hardware circuit, and may include an integrated circuit (IC) and / or a discrete circuit. Programmable circuits include logical products, logical sums, exclusive ORs, negative logical products, logical sums, and other logical operations, such as, for example, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like. , Flip-flops, registers, and reconfigurable hardware circuits, including memory elements.

The computer-readable storage medium may include any tangible device capable of storing instructions executed by the appropriate device. Thereby, the computer-readable storage medium having the instructions stored in the tangible device comprises a product containing instructions that can be executed to create means for performing the operation specified in the flowchart or block diagram. become.

Examples of computer-readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of computer-readable storage media include floppy (registered trademark) disks, diskettes, hard disks, random access memory (RAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM or flash memory). , Electrically Erasable Programmable Read Only Memory (EEPROM), Static Random Access Memory (SRAM), Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD), Blu-ray® Disc, Memory Stick , Integrated circuit card, etc. may be included.

Computer-readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, and the like. Computer-readable instructions also include object-oriented programming languages such as Smalltalk, JAVA®, C ++, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages. It may include source code or object code written in any combination of multiple programming languages.

Computer-readable instructions are the processors of general purpose computers, special purpose computers, or other programmable data processing devices, either locally or via a local area network (LAN), wide area network (WAN) such as the Internet, etc. Alternatively, it may be provided in a programmable circuit. Thereby, a general purpose computer, a special purpose computer, or a processor of another programmable data processing unit, or a programmable circuit, is said to generate means for performing an operation specified in a flowchart or block diagram. Can execute computer-readable instructions. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, and the like.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

The order of execution of operations, procedures, steps, steps, etc. in the devices, systems, programs, and methods shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 Incremental type delta sigma AD converter, 12 input terminal, 14 output terminal, 100 delta sigma converter, 110 sample hold, 120 adder, 130 analog integrator, 140 feed forward, 150 quantization, 160 DA conversion Unit, 162 1st switch unit, 164 2nd switch unit, 166 3rd switch unit, 170 reset unit, 180 control unit, 190 digital filter unit, 210 1st analog integrator, 212 1st analog amplifier, 214 positive side reset Switch, 216 Negative side reset switch, 220 2nd analog integrator, 222 2nd analog amplifier, 224 Positive side reset switch, 226 Negative side reset switch, 230 3rd analog integrator, 232 3rd analog amplifier, 234 Positive side reset Switch, 236 Negative side reset switch, 240 1st switched capacitor, 242 1st switch, 244 2nd switch, 245 2nd switched capacitor, 246 1st switch, 248 2nd switch, 250 1st feed forward, 252nd 1FF switch, 260th 2 feed forward section, 262 2nd FF switch, 270 3rd feed forward section, 272 3rd FF switch, 280 4th feed forward section, 282 4th FF switch

Claims (13)

A delta-sigma converter that outputs a modulated digital signal obtained by delta-sigma-modulating an input analog signal,
A digital filter unit that outputs a digital signal obtained by filtering the modulated digital signal as an AD conversion result of the input analog signal, and a digital filter unit.
With
The digital filter unit is an incremental delta-sigma AD converter that switches from a first calculation for integrating the modulated digital signals to a second calculation for calculating the weighted sum of the modulated digital signals. The digital filter unit switches from the first timing for finally supplying the modulated digital signal to the digital filter unit as a signal to be filtered by the delta-sigma conversion unit to the second calculation, and sets the output timing of the AD conversion result. The incremental delta-sigma AD converter according to claim 1, which is adjusted. The delta-sigma converter has an analog integrator including a plurality of vertically connected analog integrators.
The second aspect of the present invention, wherein the digital filter unit sets the weight of the digital weighted sum of the second operation to a weight corresponding to the number of the plurality of analog integrators to accelerate the output timing of the AD conversion result. Incremental type delta-sigma AD converter. The digital filter unit performs the AD conversion result at any of the timings from one timing after the first timing to one timing before the output timing when filtering is performed only by the first calculation. The incremental delta-sigma AD converter according to claim 3, which outputs. The delta-sigma conversion unit
A quantization unit that quantizes the output signal of the analog integrating unit and supplies it as the modulated digital signal to the digital filter unit.
A DA conversion unit that outputs a feedback signal based on the output of the quantization unit, and
An adder that adds a feedback signal from the DA converter to the input analog signal,
Have,
The incremental delta-sigma AD converter according to claim 3 or 4, wherein the analog integrating unit integrates the output of the adding unit. The incremental delta-sigma AD converter according to claim 5, wherein the delta-sigma conversion unit includes a feedforward unit that transmits the input analog signal to the quantization unit. The incremental delta-sigma AD converter according to claim 6, wherein the feedforward unit transmits a part of the integration results of each of the plurality of analog integrators to the quantization unit. The incremental delta-sigma AD converter according to any one of claims 5 to 7, wherein the quantization unit quantizes the output signal of the analog integration unit into a binary or multi-valued digital signal. The delta-sigma conversion unit has a reset unit that resets the integrated value held by the plurality of analog integrators at predetermined intervals.
The incremental delta-sigma AD converter according to any one of claims 3 to 8, wherein the digital filter unit outputs a filtered digital signal at each predetermined cycle. The incremental delta-sigma AD converter according to claim 9, wherein the reset unit resets the digital filter unit at the timing of resetting the analog integrator unit. It has multiple switched capacitors and is further equipped with a sample hold unit that samples the input signal.
The incremental delta-sigma AD converter according to claim 9 or 10, wherein the sample hold unit sequentially supplies values sampled by a plurality of switched capacitors as input analog signals to the delta-sigma conversion unit. At each predetermined cycle
The plurality of switched capacitors are charged with the input signals in a predetermined tracking cycle.
It includes a control unit that sequentially transfers the charges charged in the plurality of switched capacitors to the delta-sigma conversion unit in a predetermined conversion cycle.
The incremental delta-sigma AD converter according to claim 11. It is an adjustment method that adjusts the output timing of the AD conversion result of the incremental delta-sigma AD converter.
To output a modulated digital signal obtained by delta-sigma modulation of the input analog signal,
To output a digital signal obtained by filtering the modulated digital signal as an AD conversion result of the input analog signal.
With
Filtering the modulated digital signal comprises switching from a first calculation for integrating the modulated digital signal to a second calculation for calculating the weighted sum of the modulated digital signal.

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