JP5129298B2 - DWA (Data-Weighted-Averaging) circuit and delta-sigma modulator using the same - Google Patents

Description

  The present invention relates to a DWA circuit and a multi-bit delta-sigma modulator using the same.

An AD converter using a delta-sigma modulator is generally known as a converter having excellent linearity and a wide dynamic range. In the delta-sigma modulator, the signal is modulated by oversampling processing in which signal processing is performed at a frequency higher than the signal band. For this reason, it is not suitable for high-speed signal processing as compared with a Nyquist type converter such as a flash AD converter or a pipeline AD converter.
However, in recent years, high-speed, wide dynamic range AD converters are required for applications such as communication systems, and there is an increasing demand for delta-sigma modulators with a low oversampling ratio that enable high-speed signal processing. Yes.

  A multi-bit delta sigma modulator having a plurality of quantizers is known as a delta sigma modulator capable of obtaining a wide dynamic range with a low oversampling ratio. The multi-bit type delta-sigma modulator feeds back a plurality of analog values to a 1-bit feedback DA converter that feeds back only two values to a loop filter (hereinafter also simply referred to as feedback DA), and has a wide dynamic range. Is obtained, and at the same time, the problem of stability of the loop filter is reduced. The feedback value of the 1-bit feedback DA is completely linear. For this reason, a delta sigma modulator having 1-bit feedback DA has very good linearity.

However, multi-bit delta-sigma modulators have a feedback DA that is used to feed back multiple analog values. For this reason, an analog value to be fed back has non-linearity due to a mismatch of elements constituting the feedback DA (a defect caused by variations in element characteristics), and harmonic distortion is generated in the AD conversion result in the AD converter. There was a problem.
As means for improving the nonlinearity of the feedback DA, a plurality of DA elements (elements constituting the feedback DA) are sequentially selected to average the number of times each element is used. DWA (Data Weighted Averageing) Is known.

  FIG. 9 is a diagram for explaining a DWA circuit 600 in which a DWA algorithm according to the related art is used. Such a DWA circuit 600 is described in Non-Patent Document 1, for example. The DWA circuit 600 illustrated in FIG. 9 includes an element selection signal generation circuit and a DA control circuit 602. FIG. 9 also shows a decoder 605 that inputs a digital signal to the DWA circuit 600 and a DA 604 that receives the digital signal output from the DWA circuit 600.

Based on the value (digital value) of the digital signal input from the decoder 605, the DWA circuit 600 generates an element selection signal that sequentially uses a plurality of DA elements included in the DA 604, and outputs the element selection signal to the DA 604. . Specifically, the element selection signal generation circuit / DA control circuit 602 is configured by an accumulator that integrates input digital values, a barrel shifter that shifts digital values, and the like.
However, in the DWA algorithm that uses a plurality of DA elements in order, due to the time delay in the logic circuit used to generate the element selection signal, the input signal changes until the output signal of the DA 604 changes. There was a problem of taking time.

  Therefore, when the DA that averages the number of times of use of the DA element is used as the feedback DA of the delta-sigma AD conversion as described in Non-Patent Document 1, a plurality of analogs are added to the loop filter from the timing of data sampling by the quantizer. There has been a problem that it takes more time to process the signal until the value is fed back, and the operation of the loop filter provided in the delta-sigma converter becomes unstable. In other words, in the prior art, the DA that averages the number of times the DA element is used can be applied only to a low-speed circuit that does not deteriorate the stability of the delta-sigma loop.

As means for solving the above-described problem of time delay of the DWA circuit, a method using a switch matrix is known. Such a method is described in Non-Patent Document 2, for example.
FIG. 10 is a diagram for explaining a conventional DWA circuit 700 using a switch matrix. A DWA circuit 700 illustrated in FIG. 10 includes a switch matrix 701 and an element selection signal generation circuit 702. The quantizer 703 and the feedback DA 704 are all connected in advance by a switch matrix 701 inserted between them. Here, “all connections” means that the internal wiring of the quantizer 703 connected by the switch matrix 701 and the internal wiring of the feedback DA 704 are all connected one-to-one. Say. Further, in this specification, such a state may be referred to as “directly coupled as a whole”.

  The digital signal output from the quantizer 703 is a plurality of thermo metacodes, and the plurality of digital signals are input to the feedback DA 704 after passing through one-stage switches in the switch matrix 701. Therefore, the time delay from the change of the output value of the quantizer 703 to the change of the output signal of the feedback DA 704 is shortened by the element selection signal generation circuit 702 that controls this switch appropriately generating the element selection signal. can do.

Rex T. Baird, “Linearity Enhancement of Multibit ΔΣ A / D and D / A Converters Using Data Weighted Averageing”, IEEE Trans. Circuits Syst. II, Analog and Digital Signal Processing Vol. 42, vol. 42 No. 12, DEC 1995. Sheng-Jui Huang, “A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR Using Low-latency DEM”, inIEEEInt. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp 172-173.

However, in the prior art, the element selection signal generation circuit that controls the switch matrix needs to complete the arithmetic processing necessary to perform element selection until the next sampling timing. For this reason, the conventional DWA circuit using a switch matrix has a problem that it is difficult to use it in a signal processing system that operates at high speed.
The present invention has been made in view of these points, and provides a DWA circuit using a switch matrix that can be used in a signal processing system that operates at a higher speed, and a delta-sigma modulator using the DWA circuit. For the purpose.

To solve the above problems, DWA circuit of the present invention (e.g. DWA circuit 100 shown in FIG. 1) receives a digital signal represented in thermo metacode, prior to shuffling the bits of Kide digital signal an output signal, a digital / analog converter switch matrix output as input signal (e.g., feedback DA104 shown in FIG. 1) (e.g., switch matrix 101 shown in FIG. 1), device selection signal for controlling the switch matrix element selection signal generating circuit for generating a (element selection signal generating circuit 102 shown in example FIG. 1, element select signal generating circuit 702 shown in FIG. 7), wherein the switch matrix before Kide digital signal each bit, and each bit of the input signal of the digital / analog converter, all combinations that can be connected one-to-one Directly connected by mating, it includes a plurality of switching elements capable of outputting a digital signal of a plurality of bits (for example, a switch element 200 shown in FIG. 2), the element selection signal, each of the digital signal inputted to the switch matrix This is a signal for selecting any one of the bits as an output signal from the switch matrix, and the output signal from the switch matrix is included in the digital / analog converter and selected by the element selection signal generation circuit. The element selection signal generation circuit is used in the current cycle among the elements included in the digital / analog converter based on an output signal output from the switch matrix. The boundary between the active element and the unused element can be directly To detect, and generating said element selection signal based on the result of the detection.

Further, DWA circuit of the present invention, in the invention described above, the device selection signal generating circuit includes a logic device 301) shown from the first N-th, the total of N of the logic device 3 for example, the logic element includes a non-inverting input terminal, and an inverting input terminal, to each of the inverting input terminal, each bit of the previous SL output signal that will be output from the switch matrix is input, k-th (k ≦ N) The non-inverting input terminal of each of the logic elements is connected to the inverting input terminal of the (k−1) th logic element, and the non-inverting input terminal of the first logic element is the inverting input terminal of the Nth logic element. It is desirable to be connected to a terminal.

Further, DWA circuit of the present invention, in the invention described above, the device selection signal generating circuit, as the logic element, an AND element or NAND element, a pair of the inverter device, at least, each of the front Kide digital signal It is desirable to have as many digital values as the bits indicate.
In the DWA circuit of the present invention, it is preferable that the element selection signal generation circuit does not update the element selection signal when the output signals of the switch matrix are all L or all H.

The delta-sigma modulator according to the present invention is the digital filter expressed in the thermo metacode by quantizing the output from the loop filter (for example, the loop filter 105 shown in FIG. 8) and the loop filter in the above-described invention. quantizer for outputting a signal (e.g., quantizer 103 illustrated in FIG. 8), claim to be output before enter the Kide digital signal (feedback DA104 shown in example FIG. 8) a digital / analog converter DWA circuit according to any one of 1 to 4 (e.g., DWA circuit 100 shown in FIG. 1) and, a digital signal inputted from the DWA circuit into an analog signal, an equivalent 該A analog value And the digital / analog converter for feeding back to the loop filter.
In the delta-sigma modulator according to the present invention, the loop filter is preferably a continuous time loop filter.

  Thus, according to the present invention, it is possible to provide a DWA circuit capable of correcting an element mismatch of a digital / analog converter that outputs a plurality of analog values and capable of operating at high speed. Also, by using this, it is possible to provide a multi-bit delta sigma modulator capable of high-speed operation.

1 is a circuit diagram for explaining a DWA circuit 100 according to a first embodiment of the present invention. It is a figure for demonstrating the switch matrix of Embodiment 1 shown in FIG. FIG. 2 is a diagram for explaining an element selection signal generation circuit according to the first embodiment shown in FIG. FIG. 2 is a diagram for explaining a specific operation of the DWA circuit shown in FIG. 1. FIG. 6 is another diagram for explaining a specific operation of the DWA circuit shown in FIG. 1. 1 is a diagram for illustrating a signal processing system to which a DWA circuit according to a first embodiment is applicable. FIG. 6 is a diagram for explaining an element selection signal generation circuit according to a second embodiment. It is a figure for demonstrating the delta-sigma modulator of Embodiment 3 of this invention. It is a figure for demonstrating the prior art of this invention. It is another figure for demonstrating the prior art of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
DWA Circuit FIG. 1 is a circuit diagram for explaining the DWA circuit 100 according to the first embodiment of the present invention. In addition to the DWA circuit 100, a quantizer 103, a feedback DA (DA converter, hereinafter simply referred to as DA) 104).
As shown in FIG. 1, a DWA circuit 100 according to the first embodiment includes a switch matrix 101 for shuffling a plurality of digital signals, and an element selection signal generation circuit that generates a control signal for the switch matrix 101 based on the output signal. 102.

A plurality of digital signals input from the quantizer 103 to the DWA circuit 100 are thermometacodes. The thermo metacode is directly input to the switch matrix 101 and fed back again via the element selection signal generation circuit 102. In the DWA circuit 100 shown in FIG. 1, the switch matrix 101 directly connects the quantizer 103 and the feedback DA 104. In the switch matrix 101, all connections between the quantizer 103 and the feedback DA 104 are made in advance. Such a switch matrix 101 directly couples a plurality of digital signals input from the quantizer 103 and a plurality of input signals of the feedback DA 104 as switches that can be connected or disconnected.
The element selection signal generation circuit 102 generates an element selection signal that is a control signal for the switch matrix 101. The element selection signal is a signal for selecting any one of the digital signals input to the switch matrix 101 as an output signal of the switch matrix 101.

Switch Matrix FIG. 2 is a diagram for explaining the switch matrix 101 of the first embodiment shown in FIG. The switch matrix 101 according to the first embodiment includes 4 × 4 switch elements 200 as illustrated. The switch matrix 101 receives a digital signal (Q [3: 0]) from the quantizer 103 and receives an element selection signal (Pt [3: 0]) from the element selection signal generation circuit 102. A digital signal (Mx [3: 0]) is output from the switch matrix 101 to the feedback DA 104 and the element selection signal generation circuit 102.

-Element selection signal generation circuit Next, the element selection signal generation circuit 102 of the circuit of Embodiment 1 shown in FIG. 1 is demonstrated.
FIG. 3 is a diagram for explaining the element selection signal generation circuit 102 according to the first embodiment shown in FIG. The illustrated element selection signal generation circuit 102 includes four logic elements 301 that input digital signals from the switch matrix 101 and a latch circuit 106 that latches the digital signals output from the logic elements 301. The logic element 301 is configured by combining an AND element and an inverter element.

The element selection signal generation circuit 102 includes a total of four logic elements 301 from the first to the fourth . The logic element 301 includes a normal input terminal and an inverting input terminal, and a plurality of output signals output from the switch matrix 101 are input to each of the inverting input terminals. The normal input terminal of the logic element 301 is connected to the inverting input terminal of the preceding logic element 301, and the normal input terminal of the first logic element 301 is connected to the inverting input terminal of the fourth logic element 301. Yes. The element selection signal (Pt [3: 0]) output from the latch circuit 106 is input to the switch matrix 101 as shown in FIG.

Operation FIGS. 4 and 5 are diagrams for explaining a specific operation of the DWA circuit 100 shown in FIG. 4 shows an input cycle N of a digital signal input to the DWA circuit 100, a digital signal input to the input cycle N (denoted as a quantizer output in FIG. 4), and elements used in the feedback DA 104. (Referred to as DAC element number in FIG. 4) and an element selection signal.
FIG. 5 shows the relationship between the input cycle N and the feedback DA element used corresponding to the input cycle N.
In the first embodiment, it is assumed that the feedback DA 104 is composed of four elements (0 to 3). At this time, as shown in FIG. 4, a digital signal having a value of “2” is input from the quantizer 103 to the DWA circuit 100 in the input cycle N = 1 (hereinafter referred to as the input cycle N1). To do. At this time, H, H, L, and L are input from the quantizer 103 to the switch matrix 101 as digital signals.

  Four switch elements 200 are turned on in accordance with the combination of the input digital signal and the element selection signal. Then, the output “H” or “L” signal is output from the switched switch element 200 to the feedback DA 104 and the element selection signal generation circuit 102 as an output signal that is a digital signal. In the feedback DA 104, an element used for arithmetic processing is selected according to the value (digital value) of the digital signal input from the switch matrix 101. The element used is represented as “ON” in FIG.

  Here, assuming that the element selection signal Pt [0: 3] = L, L, L, H (initial values), the switch matrix 101 outputs the digital signal Mx1 [0: 3] = H, H, L, L. Is done. The element selection signal generation circuit 102 receives the digital signal Mx1 [0: 3], and detects the boundary between the signals “H” and “L” by the logic element 301 and the latch circuit 106 that hold the number of bits of the digital signal. . The detection result is output as an element selection signal. In the first embodiment, the element selection signal Pt1 [0: 3] = L, H, L, L indicating that the feedback DA 104 is used from the element “2” in the next input cycle is output.

  Next, in the first embodiment, it is assumed that the digital value “1” is input in the next input cycle N2. As described above, since the element selection signal Pt1 [0: 3] = L, H, L, L is input to the switch matrix 101, the switch is switched according to the combination of the input digital value and the element selection signal. From the matrix 101, an element selection signal that causes the element 2 to be used in the feedback DA 104 is output to the feedback DA 104.

Further, when a digital value of “3” is input in the next cycle N3, the circle shown in FIG. 5 is made one round, and the elements 3, 0, 1 are selected in the feedback DA104. As described above, in the first embodiment, all the elements included in the feedback DA 104 are used in order, and the number of times of use of the elements included in the feedback DA 104 can be averaged.
According to the first embodiment, the element selection signal is generated using the digital signal output from the switch matrix 101. For this reason, the digital signal after the switch matrix 101 is a signal that already selects the elements included in the feedback DA 101 in order. Such a signal after the switch matrix 101 includes integration information of the digital input signals up to the present time.

By generating an element selection signal using such a thing, in the first embodiment, a circuit such as an accumulator for accumulating input signals that has been necessary in the past becomes unnecessary, and the next element selection is performed. The computation processing necessary for this can be speeded up. As a result, a higher-speed DWA circuit can be provided, and a simple configuration with a small circuit scale can be realized.
Further, according to the first embodiment, the distortion of the DA output signal due to the mismatch of the elements included in the feedback DA 104 becomes mismatch noise that is uncorrelated with the signal component. Further, since this noise is shaped into a first-order high-pass type, the SN ratio in the low frequency region near the signal component is improved.

  In the first embodiment, all connections are made in advance between the quantizer 103 and the feedback DA 104 by the switch matrix 101. In addition, there is no latch circuit or arithmetic logic between the quantizer 103 and the feedback DA 104. For this reason, immediately after the output of the quantizer 103 is updated, the digital value input to the feedback DA 104 is updated. In other words, in the first embodiment, the time from when the output of the quantizer 103 changes until the digital value input to the feedback DA 104 is updated is only the ON resistance of the switch and the capacitance parasitic to the matrix output unit. decide.

According to the first embodiment, the time from when the output of the quantizer 103 changes until the digital value input to the feedback DA 104 is updated can be relatively easily reduced. Specifically, for example, there is only a half cycle of the sampling frequency from the determination of the digital value output from the quantizer 103 to the change timing of the digital value output from the feedback DA 104 as in the timing chart shown in FIG. The DWA circuit 100 of the first embodiment can be applied to such a signal processing system.
The signal passing through the switch matrix 101 is an L or H digital signal. For this reason, the driving force of the buffer that outputs the digital signal before the switch matrix 101 has a problem with respect to the time from the determination of the digital value output from the quantizer 103 to the change timing of the digital value output from the feedback DA 104. Not.

  Further, in the circuit shown in FIG. 1, it is possible to provide a switch matrix for shuffling the threshold voltage in the quantizer 103 instead of the switch matrix 101. However, in such a configuration, in order to shuffle a plurality of analog values at high speed, it is necessary to increase the bandwidth of the amplifier that buffers the analog values and to perform high-speed settling. In particular, when the number of bits of a digital signal to be processed increases, the problem is that the circuit area and current consumption increase. However, in the first embodiment, since the thermo metacode is input from the quantizer 103, the analog value shuffling by the switch matrix is unnecessary, and there is an effect that such a problem does not occur.

  The first embodiment is not limited to the configuration described above. For example, in the element selection signal generation circuit 102 shown in FIG. 3, the logic element in which the AND element and the inverter element are combined may be a combination of the NAND element and the inverter. Further, even when a NAND element and an inverter are combined, a latch circuit can be provided between the output of these logic elements and the switch matrix.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described. The second embodiment is for preventing all the outputs of the switch matrix 101 shown in FIG. Therefore, in the second embodiment, the element selection signal generation circuit 102 shown in FIG. 2 in the first embodiment is replaced with the element selection signal generation circuit 702 shown in FIG.
The element selection signal generation circuit 702 illustrated in FIG. 7 includes a full code monitor circuit 109, and the latch circuit 106 includes latch elements 107a to 107d and multiplexers 108a to 108d. The full code monitor circuit 109 detects that the outputs of the switch matrix 101 are all L or all H. Then, the flag L or H is output based on the detection result.

  When the flag is L, the latch circuit 106 updates the value of Ptn [0: 3] at the rising timing of the timing φ bar (“bar” indicates an inverted signal of the signal φ). On the other hand, when the flag is H, the previous value Ptn−1 [0: 3] is output again. According to the second embodiment, it is possible to prevent all the outputs of the element selection signal generation circuit 702 from becoming L. For this reason, it is possible to avoid a state in which none of the switches of the switch matrix 101 shown in FIG.

According to the second embodiment, there is no need to provide a limiting circuit or provide redundant bits so that the outputs of the switch matrix 101 do not all become L or all H. The second embodiment can realize a function of preventing all the outputs of the switch matrix 101 from becoming L or H by adding a relatively small number of circuits.
The full code monitor circuit 109 can be composed of an AND element having input ports for the number of digital bits.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described. In the third embodiment, a delta-sigma modulator using the DWA circuit described in the first or second embodiment will be described.
FIG. 8 is a diagram for explaining the delta-sigma modulator according to the third embodiment. As shown in FIG. 8, the delta-sigma modulator of Embodiment 3 includes a loop filter 105, a quantizer 103 that quantizes an analog signal output from the loop filter 105 and outputs a plurality of digital signals, and a loop filter. A feedback DA 104 that outputs a plurality of analog signals to 105 and the DWA circuit 100 described in the first or second embodiment are configured.

As shown in FIG. 8, the delta-sigma modulator according to the third embodiment includes a feedback loop to which negative feedback is applied. For this reason, when the time delay amount of the path of the loop filter 105 is large, there is a problem that the phase margin is lost and the operation of the loop filter 105 becomes unstable.
According to the first and second embodiments described above, it is possible to provide a DWA circuit that operates at high speed. By using such a DWA circuit, the delta-sigma modulator of Embodiment 3 can constitute a feedback loop with a small time delay. Therefore, according to the third embodiment, the stability of the delta-sigma modulator is improved, and since high-speed signal processing is possible, it is possible to provide a delta-sigma modulator that can operate at high speed.

Note that the loop filter 105 of the third embodiment may have any configuration of an SC (Switched-Capacitor) filter and a continuous time filter. In the case of a continuous-time delta-sigma modulator composed of a continuous-time filter, since there is no requirement for the settling speed of the SC filter, the digital signal is output from the quantizer until the analog signal is output from the feedback DA. Time delay (excess loop delay) is the rate limiting factor.
In the case of a multi-bit continuous time delta-sigma modulator that feeds back a plurality of analog outputs, the presence of a DWA circuit often hinders the speeding up. Therefore, it can be said that applying the DWA circuit of the first and second embodiments to the continuous time delta-sigma modulator of the third embodiment is a preferable application example.

  The present invention described above can be applied to any circuit as long as it is a DWA circuit and a multi-bit delta-sigma modulator using the DWA circuit.

DESCRIPTION OF SYMBOLS 100 DWA circuit 101 Switch matrix 102,702 Element selection signal generation circuit 103 Quantizer 105 Loop filter 106 Latch circuit 107a-107d Latch element 108a-108d Multiplexer 109 Full code monitor circuit 200 Switch element 301 Logic element

Claims (6)

Receives the digital signal represented by thermo metacode, an output signal shuffling the bits of the previous SL digital signal, and a switch matrix outputs as an input signal of the digital / analog converter,
An element selection signal generation circuit for generating an element selection signal for controlling the switch matrix,
Said switch matrix, and each bit of the pre Kide digital signal, with each bit of the input signal of the digital / analog converter, connected directly by all combinations that can be connected in a one-to-one, multiple-bit digital Including a plurality of switch elements capable of outputting signals,
The element selection signal is a signal for selecting any one of the bits of the digital signal input to the switch matrix as an output signal from the switch matrix,
The output signal from the switch matrix is a signal for sequentially selecting elements included in the digital / analog converter and selected by the element selection signal generation circuit,
The element selection signal generation circuit includes a boundary between an element used in the current cycle and an element not used among the elements included in the digital / analog converter based on an output signal output from the switch matrix. Is directly detected using a logic element, and the element selection signal is generated based on the detection result . The device selection signal generating circuit includes a first N-th, the total of N of the logic elements,
The logic element is
Includes a non-inverting input terminal, an inverting input terminal, to each of the inverting input terminal, each bit of the previous SL output signal from the switch matrix Ru is outputted is inputted, k-th (k ≦ N) from the logic element Are connected to the inverting input terminal of the (k−1) th logic element, and the normal input terminal of the first logic element is connected to the inverting input terminal of the Nth logic element. The DWA circuit according to claim 1, wherein: The device selection signal generating circuit, as the logic element is an AND element or NAND element, a pair of the inverter device, at least, characterized in that it comprises as many digital value indicated by each bit of the previous Kide digital signal The DWA circuit according to claim 1 or 2 . The device selection signal generating circuit when said output signal of the switch matrix are all L or all H, according to any one of claims 1 to 3 characterized in that it does not update the device selection signal DWA circuit. A loop filter,
A quantizer that quantizes the output from the loop filter and outputs a digital signal expressed in a thermo metacode ;
And DWA circuit according to any one of claims 1 to 4 and outputs the digital / analog converter to front input the Kide digital signal,
The digital signal inputted from the DWA circuit into an analog signal, and the digital / analog converter the person 該A analog value is fed back to the loop filter,
A delta-sigma modulator comprising: The delta-sigma modulator according to claim 5 , wherein the loop filter is a continuous-time loop filter.

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