CN116488657A - Integrator circuit, sigma-delta modulator and analog-to-digital converter - Google Patents
Integrator circuit, sigma-delta modulator and analog-to-digital converter Download PDFInfo
- Publication number
- CN116488657A CN116488657A CN202310732195.8A CN202310732195A CN116488657A CN 116488657 A CN116488657 A CN 116488657A CN 202310732195 A CN202310732195 A CN 202310732195A CN 116488657 A CN116488657 A CN 116488657A
- Authority
- CN
- China
- Prior art keywords
- signal
- chopping
- module
- chopper
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 28
- 238000005070 sampling Methods 0.000 claims description 20
- 230000003321 amplification Effects 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 238000001914 filtration Methods 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 34
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 31
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 31
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 30
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 101150040681 cho1 gene Proteins 0.000 description 10
- 230000000630 rising effect Effects 0.000 description 9
- 102100031765 3-beta-hydroxysteroid-Delta(8),Delta(7)-isomerase Human genes 0.000 description 6
- 101000866618 Homo sapiens 3-beta-hydroxysteroid-Delta(8),Delta(7)-isomerase Proteins 0.000 description 6
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000010363 phase shift Effects 0.000 description 6
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The application relates to an integrator circuit, a sigma-delta modulator and an analog-to-digital converter. The integrator circuit includes: the first chopper module, the second chopper module, the amplifier, the third chopper module and the feedback module are connected between the output end of the third chopper module and the input end of the first chopper module. The average offset value is 0 by making the frequencies of the third chopping signal and the second chopping signal equal to the same value as the frequency of the first chopping signal and the same time and the opposite time of the third chopping signal and the second chopping signal are the same, so that the total number of offset peaks in the circuit that are positive and the offset peaks that are negative are equal. Therefore, the total offset of the output signal of the integrator is reduced, and further, the total offset of the output signal of the integrator can be obviously reduced through subsequent low-pass filtering processing, so that the accuracy of the conversion result of the sigma-delta analog-to-digital converter is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to an integrator circuit, a sigma-delta modulator, and an analog-to-digital converter.
Background
Analog-to-digital Converter (ADC) is used to convert Analog signals to digital signals. Sigma-Delta (Sigma-Delta) analog-to-digital converters are widely used in the field of integrated circuits because of their advantages of high resolution, high integration, low cost, etc., among various analog-to-digital converters.
However, the sigma-delta analog-to-digital converter is susceptible to dc bias and flicker noise when processing low-frequency and low-level signals, and thus a sigma-delta Modulator (SDM), which is an important component in the sigma-delta analog-to-digital converter, needs to have a function of reducing dc bias and low-frequency noise.
Chopper stabilization is often used in the integrator of sigma-delta modulators as a method to improve the low frequency performance of operational amplifiers. In the related art, an integrator mostly adopts a mirror image integration structure, and direct current offset and flicker noise generated by an operational amplifier in the integrator are eliminated by using a chopper. However, due to the manufacturing process, the charge injection and clock feedthrough at the chopper switch act on the operational amplifier of the integrator, so that the operational amplifier generates a larger residual offset, the residual offset is mixed with the signal amplified by the input signal, the total offset of the output signal of the integrator is increased, and the final conversion result of the sigma-delta analog-to-digital converter is deviated.
Disclosure of Invention
Based on this, it is necessary to provide an integrator circuit, a sigma-delta modulator and an analog-to-digital converter that can reduce the residual offset.
An integrator circuit, comprising:
the first chopping module is used for accessing an input signal and a first chopping signal, modulating the input signal according to the first chopping signal and obtaining a first modulation signal;
the second chopping module is connected with the output end of the first chopping module, is also used for accessing a second chopping signal, and modulates the first modulation signal according to the second chopping signal to obtain a second modulation signal; the frequency of the second chopping signal is a preset multiple of the frequency of the first chopping signal, and the preset multiple is an integer multiple of more than 1 time;
the amplifier is connected with the output end of the second chopper module and is used for amplifying the second modulation signal to obtain a modulation amplification signal;
the third chopping module is connected with the output end of the amplifier, is also used for accessing a third chopping signal, and modulates the modulated amplified signal according to the third chopping signal to obtain a third modulated signal; the frequency of the third chopping signal is the same as the frequency of the second chopping signal, and the same time and opposite time of the phase of the third chopping signal and the phase of the second chopping signal are equal;
the feedback module is connected between the output end of the third chopping module and the input end of the first chopping module and is used for feeding back the third modulation signal to the first chopping module so that the first chopping module, the second chopping module and the amplifier can conduct demodulation and amplification processing on the third modulation signal to obtain a demodulation and amplification signal;
the third chopping module is further configured to modulate the demodulated and amplified signal according to the third chopping signal to obtain an output signal, where the output signal includes a useful signal, and the useful signal is a signal obtained by modulating, demodulating, and amplifying the input signal.
In one embodiment, the third chopping module includes a first chopping unit and a second chopping unit; the input end of the first chopping unit and the input end of the second chopping unit are both connected with the output end of the amplifier, and the output end of the first chopping unit is connected with the feedback module;
the first chopping unit and the second chopping unit are also used for accessing the third chopping signal; the first chopping unit is used for modulating the modulation amplification signal according to the third chopping signal to obtain the third modulation signal; the second chopping unit is used for modulating the demodulation amplified signal according to the third chopping signal to obtain the output signal.
In one embodiment, the frequency of the first chopping signal is greater than the frequency of the input signal.
In one embodiment, the frequency of the second chopping signal is more than three times the frequency of the first chopping signal.
In one embodiment, the third chopping signal is the same phase as the second chopping signal when the first chopping signal is high; the third chopping signal is in opposite phase to the second chopping signal when the first chopping signal is low.
In one embodiment, the circuit further comprises a sampling circuit, wherein an input end of the sampling circuit is connected with an external signal, an output end of the sampling circuit is connected with an input end of the first chopping module, and the sampling circuit is used for sampling the external signal and outputting the input signal to the first chopping module.
In one embodiment, the input end of the first chopper module includes a positive electrode and a negative electrode, the output end of the first chopper unit includes a positive electrode and a negative electrode, and the feedback module includes: the first feedback unit is connected between the positive electrode of the output end of the first chopping unit and the positive electrode of the input end of the first chopping module; the second feedback unit is connected between the negative electrode of the output end of the first chopping unit and the negative electrode of the input end of the first chopping module.
In one embodiment, the first feedback unit includes a first capacitance, and the second feedback unit includes a second capacitance; the first capacitor is connected between the positive electrode of the output end of the first chopping unit and the positive electrode of the input end of the first chopping module, and the second capacitor is connected between the negative electrode of the output end of the first chopping unit and the negative electrode of the input end of the first chopping module.
A sigma-delta modulator, comprising: the low-pass filter circuit is connected with the integrator circuit, the low-pass filter circuit and the quantizer circuit in sequence, wherein the integrator circuit is the integrator circuit;
the low-pass filter circuit is used for carrying out low-pass filter processing on the output signal output by the integrator circuit so as to obtain a useful signal in the output signal;
the quantizer circuit is used for converting the useful signal into a multi-bit digital signal and outputting the multi-bit digital signal.
An analog to digital converter comprising a sigma-delta modulator as described above.
The integrator circuit, the sigma-delta modulator and the analog-to-digital converter comprise a first chopping module, a second chopping module, an amplifier, a third chopping module and a feedback module connected between the third chopping module and the first chopping module. The frequency of the third chopping signal and the frequency of the second chopping signal are the same value larger than that of the first chopping signal, and the phase is the same time and the opposite time, so that after the offset peaks (voltage signals) generated by the first chopping module and the second chopping module are amplified by an amplifier, the offset peaks are modulated by the third chopping module, fed back to the first chopping module and the second chopping module by a feedback module, subjected to phase modulation by the first chopping module, subjected to high-frequency modulation by the second chopping module, subjected to secondary modulation by the third chopping module, and subjected to secondary modulation, and at the moment, when the third chopping signal is the same as the second chopping signal, the pulse rising edge is the positive offset peak, so that the positive offset peak is obtained; the pulse falling edge and the negative offset peak are obtained as positive offset peak; under the condition that 180 degrees of phase shift exists between the third chopping signal and the second chopping signal, the rising edge of the pulse and the negative offset peak are obtained, and the negative offset peak is obtained; the pulse falling edge and the positive offset spike result in a negative offset spike such that the positive offset spike is equal to the total number of negative offset spikes and the average offset value is 0. Therefore, the total offset of the output signal of the integrator is reduced, and further, the total offset of the output signal of the integrator can be obviously reduced through subsequent low-pass filtering processing, so that the accuracy of the conversion result of the sigma-delta analog-to-digital converter is improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of an integrator in the prior art in one embodiment;
FIG. 2 is a schematic diagram of the timing and bias of the integrator in the embodiment of FIG. 1;
FIG. 3 is a block diagram of an integrator circuit in one embodiment;
FIG. 4 is a schematic diagram of the timing and biasing of an integrator circuit in one embodiment;
FIG. 5 is a block diagram of an integrator circuit in another embodiment;
FIG. 6 is a schematic diagram of an integrator circuit in one embodiment;
FIG. 7 is a schematic diagram of an integrator circuit in another embodiment;
fig. 8 is a schematic diagram of a sigma-delta modulator in one embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
As described in the background art, in the integrator of the sigma-delta analog-to-digital converter in the related art, the residual offset of the operational amplifier is larger, and the total offset of the output signal of the integrator is increased, so that the final conversion result of the sigma-delta analog-to-digital converter has the technical problem of low accuracy. As shown in fig. 1, an integrator of a mirror integrating structure in the related art includes a chopper CHO11, a sampling circuit 100, a chopper CHO12, a chopper CHO13, a chopper CHO14, an operational amplifier AMP0, a feedback capacitor C11, and a feedback capacitor C12. The input signal Vin is first modulated by a chopper CHO11 controlled by a clock signal CLK, the chopper signal CLK operating at fs/2 (fs being the sampling frequency), and finally demodulated back to baseband by a chopper CHO 14. The dc bias and 1/f noise (flicker noise) of the operational amplifier AMP0 are modulated to a chopping frequency by the chopper CHO14 to be eliminated by a low-pass filter.
The capacitor Cs1 and the capacitor Cs2 are parasitic capacitances of the chopper CHO11 between the clock path and the signal path, and the capacitor Cs3 and the capacitor Cs4 are parasitic capacitances corresponding to the chopper CHO 12. Ideally, the capacitance value of the capacitor Cs1 is the same as that of the capacitor Cs2, and the capacitance value of the capacitor Cs3 is the same as that of the capacitor Cs 4. Therefore, the output of the input signal after passing through the operational amplifier AMP0 does not show a differential mode peak (voltage) and will not have a residual offset (spike voltage). However, due to practical process factors, there is a deviation in the capacitance values of the capacitor Cs1 and the capacitor Cs2, and the capacitance values of the capacitor Cs3 and the capacitor Cs 4. When the clock of the chopper signal CLK is switched from on to off each time, the channel charges injected by the chopper CHO11 and CHO12 will be different due to the mismatch of the parasitic capacitances, resulting in asymmetry at both ends of the signal input to the operational amplifier AMP0, the asymmetry of the input signal results in an offset spike (voltage) of the output signal of the operational amplifier AMP0, and after demodulation by the chopper CHO14, the residual bias (spike voltage) which cannot be distinguished from the input signal appears at the output of the integrator.
As shown in fig. 2, fig. 2 is a schematic diagram of the timing and offset values of the integrator in fig. 1, and after the signal is chopped by the chopper CHO11 and CHO12 in fig. 1 at the frequency of fig. 2 (c), the generated offset peak is shown in fig. 2 (d); then, the pulse signal is demodulated in the same way as in the step (c) of fig. 2, and the positive offset peak is obtained by the pulse rising edge and the positive offset peak; the pulse falling edge and the negative offset spike result in a positive offset spike resulting in the offset spike plot of fig. 2 (e), where the offset value (i.e., average offset value/residual offset value) of the offset is shown in fig. 2 (e) as a dashed line. Therefore, in the integrator of the sigma-delta analog-to-digital converter in the related art, there is a phenomenon that the residual offset of the operational amplifier is large.
Based on the above technical problems, the inventors have found that by suppressing the offset caused by the parasitic capacitances Cs1 and Cs2, cs3 and Cs4 of the chopper CHO11 and the chopper CHO12 in fig. 1, the residual offset of the operational amplifier can be effectively suppressed, and the final conversion result of the sigma-delta analog-to-digital converter is more accurate. Based on the above, the inventors further studied the technical scheme of the embodiment of the present invention. Specifically, an embodiment of the present invention provides an integrator circuit including: the first chopping module is used for accessing an input signal and a first chopping signal, and modulating the input signal according to the first chopping signal to obtain a first modulation signal; the second chopping module is connected with the output end of the first chopping module, is also used for accessing a second chopping signal, and modulates the first modulation signal according to the second chopping signal to obtain a second modulation signal; the frequency of the second chopping signal is a preset multiple of the frequency of the first chopping signal, and the preset multiple is an integer multiple greater than 1 time; the amplifier is connected with the output end of the second chopper module and is used for amplifying the second modulation signal to obtain a modulation amplified signal; the third chopping module is connected with the output end of the amplifier, is also used for accessing a third chopping signal, and modulates the modulation amplification signal according to the third chopping signal to obtain a third modulation signal; the frequency of the third chopping signal is the same as that of the second chopping signal, and the same time and opposite time of the phase of the third chopping signal and the second chopping signal are equal; the feedback module is connected between the output end of the third chopper module and the input end of the first chopper module and is used for feeding back a third modulation signal to the first chopper module so that the first chopper module, the second chopper module and the amplifier can demodulate and amplify the third modulation signal to obtain a demodulated and amplified signal; the third chopper module is further used for modulating the demodulation and amplification signal according to a third chopper signal to obtain an output signal, wherein the output signal comprises a useful signal, and the useful signal is a signal obtained by modulating, demodulating and amplifying an input signal.
By adopting the technical scheme, the frequency of the third chopping signal and the frequency of the second chopping signal are the same value larger than the frequency of the first chopping signal, and the phase is the same time and the opposite time, so that after the offset peaks (voltage signals) generated by the first chopping module and the second chopping module are amplified by the amplifier, the offset peaks are fed back to the first chopping module and the second chopping module through the feedback module after being modulated by the third chopping module, the phase modulation is carried out by the first chopping module, the high-frequency modulation is carried out by the second chopping module, and the remodulation is carried out by the third chopping module, and at the moment, when the third chopping signal CLK2 is the same as the second chopping signal CLK1, the pulse rising edge is the positive offset peak, so that the positive offset peak is obtained; the pulse falling edge and the negative offset peak are obtained as positive offset peak; under the condition that 180 degrees of phase shift exists between the third chopping signal CLK2 and the second chopping signal CLK1, the rising edge of the pulse and the negative offset peak are obtained, and the negative offset peak is obtained; the pulse falling edge and the positive offset spike result in a negative offset spike such that the positive offset spike is equal to the total number of negative offset spikes and the average offset value is 0. Therefore, the total offset of the output signal of the integrator is reduced, and further, the total offset of the output signal of the integrator can be obviously reduced through subsequent low-pass filtering processing, so that the accuracy of the conversion result of the sigma-delta analog-to-digital converter is improved.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Fig. 3 is a schematic structural diagram of an integrator circuit according to an embodiment of the present invention, where, as shown in fig. 3, the integrator circuit provided in the embodiment of the present invention includes: a first chopper module 210, a second chopper module 220, an amplifier 230, a third chopper module 240, and a feedback module 250.
The first chopper module 210 is configured to receive the input signal Vin and the first chopper signal CLKP, and modulate the input signal Vin according to the first chopper signal CLKP to obtain a first modulated signal. The second chopper module 220 is connected to the output end of the first chopper module 210, and the second chopper module 220 is further configured to access a second chopper signal CLK1 and modulate the first modulation signal according to the second chopper signal CLK1 to obtain a second modulation signal; the frequency of the second chopping signal CLK1 is a preset multiple of the frequency of the first chopping signal CLKP, the preset multiple being an integer multiple greater than 1.
The amplifier 230 is connected to the output end of the second chopper module 220, and is configured to amplify the second modulated signal to obtain a modulated amplified signal. The third chopper module 240 is connected to the output end of the amplifier 230, and the third chopper module 240 is further configured to access the third chopper signal CLK2, and modulate the modulated amplified signal according to the third chopper signal CLK2 to obtain a third modulated signal. The frequency of the third chopping signal CLK2 is the same as the frequency of the second chopping signal CLK1, and the same time and opposite time of the third chopping signal CLK2 and the second chopping signal CLK1 are equal.
The feedback module 250 is connected between the output end of the third chopper module 240 and the input end of the first chopper module 210, and is configured to feed back the third modulated signal to the first chopper module 210, so that the first chopper module 210, the second chopper module 220 and the amplifier 230 perform demodulation and amplification processing on the third modulated signal to obtain a demodulated and amplified signal. The third chopper module 240 is further configured to re-modulate the demodulated and amplified signal according to the third chopper signal CLK2 to obtain an output signal Vout, where the output signal Vout includes a useful signal, and the useful signal is a signal obtained by modulating, demodulating and amplifying the input signal Vin.
The input signal Vin is an analog signal, and the specific signal type is not limited. In actual implementation, the first chopping signal CLKP, the second chopping signal CLK1 and the third chopping signal CLK2 may be pulse signals with alternating high and low levels, and the frequencies of the first chopping signal CLKP, the second chopping signal CLK1 and the third chopping signal CLK2 may be set according to actual situations.
Preferably, the first chopping module 210 employs low frequency modulation, the clock frequency of the first chopping signal CLKP may be much lower than the frequency of the chopping signal CLK in the embodiment shown in fig. 1, in one embodiment, the frequency of the first chopping signal CLKP is greater than the frequency of the input signal Vin, and when the frequency of the first chopping signal CLKP is set, it only needs to be greater than the highest frequency of the input signal Vin, and illustratively, the frequency of the first chopping signal CLKP is more than twice the frequency of the input signal Vin. It will be appreciated that the offset value of the first chopper module 210 itself may also be reduced by employing a first chopper signal CLKP having a lower clock frequency.
Further, the second chopper module 220 may employ high-frequency modulation, specifically, the frequency of the second chopper signal CLK1 is at least 1 times that of the first chopper signal CLKP, and in practical implementation, the higher the frequency of the second chopper signal CLK1 is within the allowable range of the amplifier 230, the better the useful signal is obtained because the final output signal Vout is subjected to low-pass filtering, the higher the frequency of the second chopper signal CLK1 is, the better the filtering effect in low-pass filtering is, and the narrower the cutoff frequency requirement is, and the easier the low-pass filter is to implement. In one embodiment, the frequency of the second chopping signal CLK1 is more than three times the frequency of the first chopping signal CLKP, such as three times the frequency of the second chopping signal CLK1, five times the frequency of the first chopping signal CLKP, etc.
The third chopper module 240 is also a high frequency modulation, which has the same frequency of the third chopper signal CLK2 as the second chopper signal CLK1, and the same phase of the third chopper signal CLK2 as the second chopper signal CLK1 is equal to the opposite phase, and in one embodiment, when the first chopper signal CLKP is at a high level, the third chopper signal CLK2 is opposite to the second chopper signal CLK 1; when the first chopping signal CLKP is at a low level, the third chopping signal CLK2 is in the same phase as the second chopping signal CLK 1. In another embodiment, the third chopping signal CLK2 and the second chopping signal CLK1 are in the same phase when the first chopping signal CLKP is at a high level; when the first chopping signal CLKP is low, the third chopping signal CLK2 is opposite in phase to the second chopping signal CLK 1. In practical implementation, those skilled in the art can flexibly set the time required for the third chopping signal CLK2 to be identical to the time required for the second chopping signal CLK1 to be opposite to the time required for the third chopping signal CLK1 to be identical to the time required for the second chopping signal CLK 1.
The principle of the present embodiment will be described with reference to fig. 3 to 4, taking the example that the frequency of the second chopping signal CLK1 is three times the frequency of the first chopping signal CLKP, it is assumed that the timing of the third chopping signal CLK2 is identical to the timing of the second chopping signal CLK1 when the first chopping signal CLKP is at a high level, and that there is a 180 degree phase shift between the third chopping signal CLK2 and the second chopping signal CLK1 when the first chopping signal CLKP is at a low level.
In this embodiment, the current input signal Vin is first subjected to low-frequency modulation by the first chopper module 210, so as to realize phase modulation of the signal, and obtain a low-frequency first modulated signal; the second chopper module 220 modulates the second modulated signal into a high-frequency second modulated signal, and then the second modulated signal is amplified by the amplifier 230, and the amplified modulated amplified signal is an operational amplifier, and the modulated amplified signal output by the operational amplifier comprises: the signal obtained by twice modulating the input signal Vin through the first chopper module 210 and the second chopper module 220 and amplifying the input signal through the amplifier 230 is assumed to be a "first process signal" for convenience of description.
The modulated amplified signal is then high frequency modulated by the third chopper module 240 to obtain a third modulated signal, which may be understood to include: the "first process signal" is a "second process signal" obtained by modulating the third chopper module 240 again (the second process signal is a signal obtained by modulating the input signal Vin twice by the first chopper module 210 and the second chopper module 220, amplifying the signal by the amplifier 230, and modulating the signal by the third chopper module 240).
The third modulation signal is fed back to the input end of the first chopper module 210 through the feedback module 250, so that the first chopper module 210 and the second chopper module 220 demodulate the second process signal, the amplifier 230 amplifies the second process signal for a second time to increase the amplitude of the second process signal, the third chopper module 240 demodulates the second process signal again to obtain an output signal Vout, and at the moment, the input signal Vin is a useful signal in the output signal Vout, namely, the useful signal is demodulated by the first chopper module 210 and the second chopper module 220 twice, amplified by the amplifier 230, modulated by the third chopper module 240, demodulated by the first chopper module 210 and the second chopper module 220 twice, amplified by the amplifier 230, and demodulated by the third chopper module 240, and the frequency of the useful signal is already demodulated to the original frequency of the input signal Vin, and the amplitude of the useful signal Vin is the amplitude of the input signal Vin after the two times of amplification.
In the above processing procedure, the second modulated signal input to the amplifier 230 includes the signal of the input signal Vin modulated at high frequency and the noise signal (including offset spike voltage) of the front-end chopper module, and the signals are amplified, but the input signal Vin is demodulated back to the original frequency after being processed, and only the amplitude is amplified, the average offset after the offset spike in the noise is processed is already 0, and other signals in the noise are modulated at high frequency, so that only the useful signal can be remained when the subsequent low-pass filtering is performed, and the final analog-digital conversion result is more accurate and reliable.
Regarding the offset peak, in the present embodiment, by making the frequency of the third chopping signal CLK2 the same as the frequency of the second chopping signal CLK1, the phase is set to be changed along with the voltage state of the first chopping signal CLKP, so that after the input signal Vin passes through the second chopping module 220, the offset peak generated by the second chopping module 220 is amplified and fed back to the first chopping module 210 and the second chopping module 220, and is modulated to a high frequency by the second chopping module 220, but is also modulated by the frequency of the first chopping signal CLKP with a lower frequency, so as to obtain the offset peak diagram of fig. 4 (d). Since the magnitude of the offset is proportional to the number of offset peaks, the same time and opposite time of the third chopping signal CLK2 and the second chopping signal CLK1 need to be identical to each other to enable the frequency of the offset peaks generated by the second chopping module 220 to be distinguished from the chopping signals with a 180 degree phase shift between the third chopping signal CLK2 and the second chopping signal CLK 1. At this time, the signal is demodulated again by the pulse signal in fig. 4 (b), and when the third chopping signal CLK2 is identical to the second chopping signal CLK1, the rising edge of the pulse is a positive offset peak, so as to obtain a positive offset peak; the pulse falling edge and the negative offset peak are obtained as positive offset peak; under the condition that 180 degrees of phase shift exists between the third chopping signal CLK2 and the second chopping signal CLK1, the rising edge of the pulse and the negative offset peak are obtained, and the negative offset peak is obtained; the pulse falling edge and the positive offset peak are used for obtaining a negative offset peak; thus, the offset spike diagram of fig. 4 (e) is obtained, and it can be seen that the offset average value at this time is 0. The high frequency peak offset generated by the chopper module is modulated onto the frequency of the lower CLKP, which is higher than the frequency of the input signal Vin, although lower than the frequencies of the third and second chopper signals CLK2 and CLK1, and the average residual offset at the output of the integrator circuit will be zero after subsequent passes through the low pass filter.
The integrator circuit includes a first chopper module 210, a second chopper module 220, an amplifier 230, a third chopper module 240, and a feedback module 250 connected between an output terminal of the third chopper module 240 and an input terminal of the first chopper module 210. By making the frequency of the third chopping signal CLK2 and the second chopping signal CLK1 be the same value larger than the frequency of the first chopping signal CLKP, and the same time and the opposite time of the phase, the offset peak (voltage signal) generated by the first chopping module 210 and the second chopping module 220 is amplified by the amplifier 230, then is fed back to the first chopping module 210 and the second chopping module 220 by the feedback module 250 through modulation of the third chopping module 240, is subjected to phase modulation by the first chopping module 210, is subjected to high-frequency modulation by the second chopping module 220, and is subjected to secondary modulation by the third chopping module 240, and at this time, when the third chopping signal CLK2 is the same as the second chopping signal CLK1, the pulse rising edge is the positive offset peak, so that the positive offset peak is obtained; the pulse falling edge and the negative offset spike result in a positive offset spike. Under the condition that 180 degrees of phase shift exists between the third chopping signal CLK2 and the second chopping signal CLK1, the rising edge of the pulse and the negative offset peak are obtained, and the negative offset peak is obtained; the pulse falling edge and the positive offset spike result in a negative offset spike such that the positive offset spike is equal to the total number of negative offset spikes and the average offset value is 0. Therefore, the total offset of the output signal of the integrator is reduced, and the accuracy of the conversion result of the sigma-delta analog-to-digital converter is further improved.
In one embodiment, as shown in fig. 5, the third chopping module 240 includes a first chopping unit 241 and a second chopping unit 242. The input end of the first chopping unit 241 and the input end of the second chopping unit 242 are both connected with the output end of the amplifier 230, and the output end of the first chopping unit 241 is connected with the feedback module 250.
The first chopping unit 241 and the second chopping unit 242 are also used for switching in the third chopping signal CLK2; the first chopper unit 241 is configured to modulate the modulated amplified signal according to a third chopper signal CLK2 to obtain a third modulated signal; the second chopper 242 is configured to modulate and demodulate the amplified signal according to the third chopper signal CLK2 to obtain an output signal Vout.
The structures of the first chopping unit 241, the second chopping unit 242, the first chopping module 210 and the second chopping module 220 may be set according to actual needs, for example, they are all choppers. Specifically, referring to fig. 6, the first chopper module 210 includes a first chopper CHO1, the second chopper module 220 includes a second chopper CHO2, the first chopper unit 241 includes a third chopper CHO3, the second chopper unit 242 includes a fourth chopper CHO4, the amplifier 230 includes an operational amplifier AMP, and the structures of the first chopper CHO1, the second chopper CHO2, the third chopper CHO3 and the fourth chopper CHO4 may be the same.
In practical implementation, the positive electrode of the input end and the negative electrode of the first chopper CHO1 are used for accessing an input signal Vin, the positive electrode of the output end of the first chopper CHO1 is connected with the positive electrode of the input end of the second chopper CHO2, the negative electrode of the output end of the first chopper CHO1 is connected with the negative electrode of the input end of the second chopper CHO2, and the control end of the first chopper CHO1 is accessed with a first chopping signal CLKP; the positive electrode of the output end of the second chopper CHO2 is connected with the non-inverting input end of the operational amplifier AMP, and the negative electrode of the output end of the second chopper CHO2 is connected with the inverting input end of the operational amplifier AMP; the inverting output end of the operational amplifier AMP is connected with the positive electrode of the input end of the third chopper CHO3 and the positive electrode of the input end of the fourth chopper CHO4, and the non-inverting output end of the operational amplifier AMP is connected with the negative electrode of the input end of the third chopper CHO3 and the negative electrode of the input end of the fourth chopper CHO 4. The positive electrode of the output end of the third chopper CHO3 and the negative electrode of the output end of the third chopper CHO3 are also connected to the feedback module 250.
Note that, although parasitic capacitance is also generated by the third chopper CHO3 and the fourth chopper CHO4, residual offset generated by the peak corresponding to the third chopper CHO3 returns to the front end of the operational amplifier AMP0 along with the feedback loop and is not directly transmitted to the output end, and the error caused by the third chopper CHO3 is suppressed by the gain before due to the open loop gain of the operational amplifier AMP, so that the charge injection error is significantly reduced; the peak generated by the unmatched parasitic capacitance of the fourth chopper CHO4 is in the frequency band of the third chopping signal CLK2, and the signal is chopped again and modulated back to the baseband, so that the peak of the fourth chopper CHO4 can be filtered out through subsequent low-pass filtering. Therefore, the residual offset caused by the third chopper CHO3 and the fourth chopper CHO4 is negligible.
In one embodiment, the input terminal of the first chopping module 210 includes a positive electrode and a negative electrode, the output terminal of the first chopping unit 241 includes a positive electrode and a negative electrode, the feedback module 250 includes a first feedback unit 251 and a second feedback unit 252, and the first feedback unit 251 is connected between the positive electrode of the output terminal of the first chopping unit 241 and the positive electrode of the input terminal of the first chopping module 210; the second feedback unit 252 is connected between the output terminal negative electrode of the first chopping unit 241 and the input terminal negative electrode of the first chopping module 210.
Specifically, the first feedback unit 251 may include a first capacitance C1, and the second feedback unit 252 may include a second capacitance C2; the first capacitor C1 is connected between the positive electrode of the output end of the first chopping unit 241 and the positive electrode of the input end of the first chopping module 210, and the second capacitor C2 is connected between the negative electrode of the output end of the first chopping unit 241 and the negative electrode of the input end of the first chopping module 210.
Still referring to the embodiment shown in fig. 6, the first capacitor C1 is connected between the positive electrode of the output terminal of the third chopper CHO3 and the positive electrode of the input terminal of the first chopper CHO1, and the second capacitor C2 is connected between the negative electrode of the output terminal of the third chopper CHO3 and the negative electrode of the input terminal of the first chopper CHO1, so that feedback is achieved through the first capacitor C1 and the second capacitor C2.
Further, in some embodiments, the integrator circuit further includes a sampling circuit 260, an input end of the sampling circuit 260 is connected to the external signal Vi, an output end of the sampling circuit 260 is connected to the input end of the first chopper module 210, and the sampling circuit 260 is configured to sample the external signal Vi and output the input signal Vin to the first chopper module 210.
The specific structure of the sampling circuit 260 may be set according to actual needs, for example, the sampling circuit includes two switch sampling units, the two switch sampling units are respectively disposed at the positive electrode of the input end of the first chopper CHO1 and the negative electrode of the input end of the first chopper CHO1, each switch sampling unit includes a switch Φ1, a switch Φ2, a switch Φ1d, a switch Φ2d and a capacitor C3, the first end of the switch Φ1d is used for accessing an external signal Vi, the second end of the switch Φ1d is connected with the first end of the switch Φ2 through the capacitor C3, and the second end of the switch Φ2 is connected with the input end of the first chopper CHO 1. The first end of the switch phi 2d is connected with one end of the capacitor C3, the first end of the switch phi 1 is connected with the other end of the capacitor C3, and the second end of the switch phi 2d and the second end of the switch phi 1 are used for accessing an externally input reference voltage signal Vref. The switches phi 1, phi 2, phi 1d and phi 2d are controlled by an external circuit, and the specific control mode is not limited, and can be set by referring to common technology in the art by a person skilled in the art.
According to the integrator circuit, the low-frequency 1/f noise and offset voltage can be removed through chopping, and meanwhile, the average residual bias caused by chopping at the output position can be further reduced through adjusting the circuit structure and the frequency and the phase of each chopping signal, so that the signal-to-noise ratio of the whole system is improved.
In one embodiment, as shown in fig. 8, there is provided a sigma-delta modulator comprising: an integrator circuit 300, a low-pass filter circuit 400, and a quantizer circuit 500 are connected in order. The integrator circuit 300 may be configured with reference to the integrator circuits of the above embodiments, and the low-pass filter circuit 400 is configured to perform low-pass filtering processing on the output signal output by the integrator circuit 300 to obtain a useful signal in the output signal; the quantizer circuit 500 is configured to convert the useful signal into a multi-bit digital signal and output the multi-bit digital signal.
In practical implementation, the structure of the sigma-delta modulator may be adjusted according to practical needs, for example, the sigma-delta modulator further includes a digital-to-analog converter, etc., and those skilled in the art may refer to the common technology in the art, which is not described in detail in this embodiment.
In an embodiment an analog to digital converter is provided comprising a Sigma-delta modulator, the structure of which can be arranged with reference to the Sigma-delta modulator of the above embodiment.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. An integrator circuit, comprising:
the first chopping module is used for accessing an input signal and a first chopping signal, modulating the input signal according to the first chopping signal and obtaining a first modulation signal;
the second chopping module is connected with the output end of the first chopping module, is also used for accessing a second chopping signal, and modulates the first modulation signal according to the second chopping signal to obtain a second modulation signal; the frequency of the second chopping signal is a preset multiple of the frequency of the first chopping signal, and the preset multiple is an integer multiple of more than 1 time;
the amplifier is connected with the output end of the second chopper module and is used for amplifying the second modulation signal to obtain a modulation amplification signal;
the third chopping module is connected with the output end of the amplifier, is also used for accessing a third chopping signal, and modulates the modulated amplified signal according to the third chopping signal to obtain a third modulated signal; the frequency of the third chopping signal is the same as the frequency of the second chopping signal, and the same time and opposite time of the phase of the third chopping signal and the phase of the second chopping signal are equal;
the feedback module is connected between the output end of the third chopping module and the input end of the first chopping module and is used for feeding back the third modulation signal to the first chopping module so that the first chopping module, the second chopping module and the amplifier can conduct demodulation and amplification processing on the third modulation signal to obtain a demodulation and amplification signal;
the third chopping module is further configured to modulate the demodulated and amplified signal according to the third chopping signal to obtain an output signal, where the output signal includes a useful signal, and the useful signal is a signal obtained by modulating, demodulating, and amplifying the input signal.
2. The integrator circuit of claim 1, wherein the third chopping module comprises a first chopping unit and a second chopping unit; the input end of the first chopping unit and the input end of the second chopping unit are both connected with the output end of the amplifier, and the output end of the first chopping unit is connected with the feedback module;
the first chopping unit and the second chopping unit are also used for accessing the third chopping signal; the first chopping unit is used for modulating the modulation amplification signal according to the third chopping signal to obtain the third modulation signal; the second chopping unit is used for modulating the demodulation amplified signal according to the third chopping signal to obtain the output signal.
3. The integrator circuit of claim 1 wherein the frequency of the first chopping signal is greater than the frequency of the input signal.
4. The integrator circuit of claim 1 wherein the frequency of the second chopping signal is more than three times the frequency of the first chopping signal.
5. The integrator circuit according to any one of claims 1 to 4, wherein the third chopping signal is the same phase as the second chopping signal when the first chopping signal is high level; the third chopping signal is in opposite phase to the second chopping signal when the first chopping signal is low.
6. The integrator circuit of claim 5 further comprising a sampling circuit, an input of the sampling circuit being coupled to an external signal, an output of the sampling circuit being coupled to an input of the first chopper module, the sampling circuit being configured to sample the external signal and output the input signal to the first chopper module.
7. The integrator circuit of claim 6 wherein the input of the first chopping module comprises a positive pole and a negative pole, the output of the first chopping unit comprises a positive pole and a negative pole, and the feedback module comprises: the first feedback unit is connected between the positive electrode of the output end of the first chopping unit and the positive electrode of the input end of the first chopping module; the second feedback unit is connected between the negative electrode of the output end of the first chopping unit and the negative electrode of the input end of the first chopping module.
8. The integrator circuit of claim 7, wherein the first feedback unit comprises a first capacitance and the second feedback unit comprises a second capacitance; the first capacitor is connected between the positive electrode of the output end of the first chopping unit and the positive electrode of the input end of the first chopping module, and the second capacitor is connected between the negative electrode of the output end of the first chopping unit and the negative electrode of the input end of the first chopping module.
9. A sigma-delta modulator, comprising: an integrator circuit, a low-pass filter circuit and a quantizer circuit connected in sequence, the integrator circuit being an integrator circuit as claimed in any one of claims 1 to 8;
the low-pass filter circuit is used for carrying out low-pass filter processing on the output signal output by the integrator circuit so as to obtain a useful signal in the output signal;
the quantizer circuit is used for converting the useful signal into a multi-bit digital signal and outputting the multi-bit digital signal.
10. An analog to digital converter comprising a sigma-delta modulator as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310732195.8A CN116488657A (en) | 2023-06-20 | 2023-06-20 | Integrator circuit, sigma-delta modulator and analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310732195.8A CN116488657A (en) | 2023-06-20 | 2023-06-20 | Integrator circuit, sigma-delta modulator and analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116488657A true CN116488657A (en) | 2023-07-25 |
Family
ID=87212206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310732195.8A Pending CN116488657A (en) | 2023-06-20 | 2023-06-20 | Integrator circuit, sigma-delta modulator and analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116488657A (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4896156A (en) * | 1988-10-03 | 1990-01-23 | General Electric Company | Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals |
| CN1549453A (en) * | 2003-05-19 | 2004-11-24 | 旺宏电子股份有限公司 | Nested chopper circuit and method for chopping analog inputting signal to supply samples |
| US20110063146A1 (en) * | 2009-09-15 | 2011-03-17 | Texas Instruments Incorporated | Multistage chopper stabilized delta-sigma adc with reduced offset |
| US8072262B1 (en) * | 2010-06-28 | 2011-12-06 | Texas Instruments Incorporated | Low input bias current chopping switch circuit and method |
| JP2015121487A (en) * | 2013-12-24 | 2015-07-02 | 旭化成エレクトロニクス株式会社 | Magnetic detection device |
| CN105306061A (en) * | 2014-05-15 | 2016-02-03 | 艾尔默斯半导体股份公司 | Fast reduced-current digitization, conditioning and filtering of analogue signals from a sensor or detector |
| JP2017153051A (en) * | 2016-02-26 | 2017-08-31 | 旭化成エレクトロニクス株式会社 | Incremental delta-sigma modulator and incremental delta-sigma a/d converter |
| US10615818B1 (en) * | 2019-06-02 | 2020-04-07 | Nxp Usa, Inc. | Mixed chopping and correlated double sampling two-step analog-to-digital converter |
| CN114157304A (en) * | 2021-12-10 | 2022-03-08 | 中国兵器工业集团第二一四研究所苏州研发中心 | Feedforward type multi-bit quantization sigma-delta modulator |
| WO2022049888A1 (en) * | 2020-09-01 | 2022-03-10 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor circuit |
| CN114614843A (en) * | 2022-03-04 | 2022-06-10 | 成都通量科技有限公司 | DCOC circuit for zero intermediate frequency receiver |
| US20220190789A1 (en) * | 2020-12-11 | 2022-06-16 | Cirrus Logic International Semiconductor Ltd. | Analog circuit differential pair element mismatch detection using spectral separation |
| CN114665832A (en) * | 2022-05-23 | 2022-06-24 | 杭州万高科技股份有限公司 | Capacitive coupling chopper modulation instrument amplifier |
| US20220239308A1 (en) * | 2021-01-28 | 2022-07-28 | Analog Devices International Unlimited Company | Switched-capacitor integrators with improved flicker noise rejection |
| WO2022173693A1 (en) * | 2021-02-12 | 2022-08-18 | Cirrus Logic International Semiconductor Ltd. | System-level chopping in coulomb counter circuit |
-
2023
- 2023-06-20 CN CN202310732195.8A patent/CN116488657A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4896156A (en) * | 1988-10-03 | 1990-01-23 | General Electric Company | Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals |
| CN1549453A (en) * | 2003-05-19 | 2004-11-24 | 旺宏电子股份有限公司 | Nested chopper circuit and method for chopping analog inputting signal to supply samples |
| US20110063146A1 (en) * | 2009-09-15 | 2011-03-17 | Texas Instruments Incorporated | Multistage chopper stabilized delta-sigma adc with reduced offset |
| US8072262B1 (en) * | 2010-06-28 | 2011-12-06 | Texas Instruments Incorporated | Low input bias current chopping switch circuit and method |
| JP2015121487A (en) * | 2013-12-24 | 2015-07-02 | 旭化成エレクトロニクス株式会社 | Magnetic detection device |
| CN105306061A (en) * | 2014-05-15 | 2016-02-03 | 艾尔默斯半导体股份公司 | Fast reduced-current digitization, conditioning and filtering of analogue signals from a sensor or detector |
| JP2017153051A (en) * | 2016-02-26 | 2017-08-31 | 旭化成エレクトロニクス株式会社 | Incremental delta-sigma modulator and incremental delta-sigma a/d converter |
| US10615818B1 (en) * | 2019-06-02 | 2020-04-07 | Nxp Usa, Inc. | Mixed chopping and correlated double sampling two-step analog-to-digital converter |
| WO2022049888A1 (en) * | 2020-09-01 | 2022-03-10 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor circuit |
| US20220190789A1 (en) * | 2020-12-11 | 2022-06-16 | Cirrus Logic International Semiconductor Ltd. | Analog circuit differential pair element mismatch detection using spectral separation |
| US20220239308A1 (en) * | 2021-01-28 | 2022-07-28 | Analog Devices International Unlimited Company | Switched-capacitor integrators with improved flicker noise rejection |
| WO2022173693A1 (en) * | 2021-02-12 | 2022-08-18 | Cirrus Logic International Semiconductor Ltd. | System-level chopping in coulomb counter circuit |
| CN114157304A (en) * | 2021-12-10 | 2022-03-08 | 中国兵器工业集团第二一四研究所苏州研发中心 | Feedforward type multi-bit quantization sigma-delta modulator |
| CN114614843A (en) * | 2022-03-04 | 2022-06-10 | 成都通量科技有限公司 | DCOC circuit for zero intermediate frequency receiver |
| CN114665832A (en) * | 2022-05-23 | 2022-06-24 | 杭州万高科技股份有限公司 | Capacitive coupling chopper modulation instrument amplifier |
Non-Patent Citations (2)
| Title |
|---|
| JIAYU WU, KAIDA ZHANG, HUA CHEN, ZHIYU WANG, FAXIN YU: "A sigma-delta modulator with residual offset suppression", IEICE ELECTRONICS EXPRESS, pages 1 - 5 * |
| 温丽媛: "高精度传感器模拟前端关键技术研究与设计", 知网 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6351506B1 (en) | Switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop | |
| JP2779267B2 (en) | Preamplifier circuit | |
| US5892473A (en) | Switched capacitor digital-analog converter with a decreased harmonic distortion | |
| CA2212146C (en) | A delta-sigma modulator having dynamically tunable continuous time gm-c architecture | |
| US7098827B2 (en) | Integrator circuit | |
| US8063629B2 (en) | Method for processing sensor signals subject to an offset and sensor arrangement designed to carry out the method | |
| US8305246B2 (en) | Amplifier with digital input and digital PWM control loop | |
| US6573785B1 (en) | Method, apparatus, and system for common mode feedback circuit using switched capacitors | |
| GB2256551A (en) | Switched-capacitor integrator with chopper stabilization performed at the sampling rate | |
| US5049831A (en) | Single-ended input to differential output amplifier with integral two-pole filter | |
| US5068660A (en) | Combining fully-differential and single-ended signal processing in a delta-sigma modulator | |
| US6259313B1 (en) | Chopper-stabilized telescopic differential amplifier | |
| US6191648B1 (en) | Switched-capacitor cosine filter circuit | |
| US10911004B2 (en) | Sampled moving average notch filter for ripple reduction in chopper stabilized operational amplifiers | |
| CA2069808A1 (en) | Analogue-to-digital converters | |
| US20190369168A1 (en) | Signal processing arrangement for a hall sensor and signal processing method for a hall sensor | |
| CN115632659A (en) | Chopper stabilization buffer suitable for Delta Sigma modulator | |
| US7898331B2 (en) | Increasing the common mode range of a circuit | |
| US10158335B2 (en) | Gated CDS integrator | |
| EP0415080A2 (en) | Device for converting unbalanced analog electric signals into fully-differential signals | |
| US7315268B1 (en) | Integrator current matching | |
| US6285311B1 (en) | Switched capacitor filter circuit having reduced offsets and allowing for offset compensation without a closed feedback loop | |
| CN116488657A (en) | Integrator circuit, sigma-delta modulator and analog-to-digital converter | |
| US20230188105A1 (en) | Analog signal processing circuit and method for eliminating dc offset voltage | |
| US20170085251A1 (en) | Preamplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |