JPS6327114A - Switch control circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate switched capacitor circuit not causing distortion or the like due to clock noise by controlling 4 kinds of switch circuits by 4 kinds of control signals so as to turn on/off the switch circuits in predcribed different timings. CONSTITUTION:A switch control circuit 16 controls the switch circuits 1-4 by using different control signals CLK1-CLK4 respectively to turn on/off them in different timings. In selecting the mode from the integration state into the charging state, the circuit 4 is turned off at first, then the circuit 3 is turned on, then the circuit 2 is turned off and the circuit 1 is turned on by controlling each switch circuit. Moreover, in switching the charging state into the integrating state, each switch circuit is controlled in such a way as by turning off the circuit 3 at first, then turning on the circuit 4, turning off the circuit 1 and turning on the circuit 2. Since the clock noise subject to integration is constant independently of the input signal, the integrated electric charge is proportional accurately to the input signal to realize the switched capacitor circuit with high accuracy.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a switched capacitor that uses a switch circuit and a capacitive element to function equivalently to a resistive element, and realizes a circuit such as an integrator or a filter. The present invention relates to a switch control circuit that controls on/off of a switch circuit in a circuit.

[Conventional technology]

A switched capacitor circuit is a switch circuit.

Various filters, analog/digital converters, etc. are realized by connecting capacitive elements and operational amplifiers.

The basic principle is to charge and discharge a signal voltage into a capacitive element by turning on and off a switch circuit, and by causing a current proportional to the signal voltage to flow, it achieves the equivalent function of a resistive element.

FIG. 6 is an example diagram of a conventional switched capacitor circuit, illustrating a switched capacitor integrator. This is a device that uses four switch circuits to avoid being affected by parasitic capacitance (for example, Ken Martin and Adel Escedra's "Stray Zoo Insensitive Switched Toe Capacitor Filters Bast on Bilinear Z-Transform"). Ken
Martin and Adal S 5edra
“Strsys-InsensitiveSwitch
ed-Capacitor Filters Ba
5ed on BBllllnearZ-trans
for” Electronics 1etters
21st June1979 Vol, 15 N
o, 13 pp. 365-366).

In FIG. 6, 1 to 4 are switch circuits, 15 is a switch control circuit, 21 and 22 are capacitive elements, 23 is an operational amplifier, 30 is a clock input terminal, 31 is a signal input terminal, 3
2 is a signal output terminal, and the above switch circuits 1 to 4,
The switch control circuit 15 and the capacitive element 21 constitute a sampling circuit, and the capacitive element 22 and the operational amplifier 23 constitute an integrating circuit.

Further, the switch control circuit 15 is constructed using logic gate circuits 50 and 51 and a delay circuit 52, for example, as shown in FIG. Then, input the clock signal CLK-〇 as shown in FIG. 8 to the clock input terminal 30, and
Two control signals CLK-A and CLK-B are output.

Switch circuits 1 to 4 in FIG.
”, and turns off when “Low”.Then, the control signal CLK-A controls switch circuits 1 and 3 simultaneously, and the control signal CLK-B controls switch circuits 2 and 4 simultaneously. are doing.

The operation of the above circuit is as follows.

That is, during period t in FIG. 8, switch circuits 1 and 3
is turned on, switch circuits 2 and 4 are turned off, and the capacitive element 21 is charged with the signal voltage applied to the signal input terminal 31.

Next, during period t, switch circuits 2 and 4 are turned on, switch circuits 1 and 3 are turned off, and the charge of capacitive element 21 is integrated into capacitive element 22 of the integrating circuit.

Note that all switch circuits are off during periods t2 and t4, but this is because switch circuits 1 and 2 or 3 and 4 are on at the same time in order to ensure that the charge in the capacitive element 21 is retained. This is to avoid this situation.

[Problem that the invention seeks to solve]

In the conventional switched capacitor circuit as described above, there is a problem in that clock noise when the switch circuits 1 to 4 are turned on and off causes an error in the integrated charge.

This will be explained in detail below.

FIG. 9 is an example of a switch circuit used as 1 to 4 in FIG.
, p-channel MOS transistor 42 and inverter 4
This is an example of a switch circuit using 3. In addition, 44 and 4
5 is a signal input/output terminal, and 46 is a control signal input terminal.

In the switch circuit like ρ mentioned above, since the MOS transistor has parasitic capacitance between the gate, source, and drain, voltage changes of the control signal leak through the parasitic capacitance to the source and drain terminals (signal input/output terminals 44 and 45). This causes clock noise.

FIG. 10 shows the voltage v7 at node 7.8 in FIG.
FIG. 3 is a diagram showing the relationship between changes in and V and clock noise.

In FIG. 10, V is the input signal voltage in the period t, and ■ is the input signal voltage in the period t of the next cycle, and these are voltages that change with time. Since the magnitude of the parasitic capacitance of a MOS transistor changes depending on the voltage at the source terminal and drain terminal, the magnitude of clock noise also changes as the input terminal voltage changes as described above.

Clock noise consists of T1, T2, and T where the clock waveform changes.
3, T, and (T,), but it is the clock noise that occurs at time T and T2 that is affected by the signal voltage.

At time T□, switch circuits 1 and 3 are turned off, but at this time, the input/output terminal voltage of switch circuit 3 is always constant at the ground voltage.

However, the input/output terminal voltage V of the switch circuit 1 changes with the input signal voltage. Clock noise is added to this voltage v1 and becomes v2, but during period t2, the capacitive element 21 is (V
2 vs), and this charge is integrated after one time point T2.

At time T2, switch circuits 2 and 4 are turned on, but since voltage v7 at node 7 quickly becomes ground voltage, operational amplifier 23 does not follow it, and immediately after time T2, voltage v9 transiently swings to voltage v6. .

Since this voltage 6 is almost proportional to the voltage v1, it affects the clock noise when the switch circuit 4 is turned on.

Also, the parasitic capacitance value of a MOS transistor varies non-linearly with respect to the source-drain voltage.

When clock noise is affected by input signal voltage, it also shows nonlinear dependence. As a result, the integrated charge is no longer completely proportional to the input signal voltage, causing distortion, making it impossible to realize a highly accurate switched capacitor circuit.

The present invention solves the problems of the prior art as described above.

The purpose is to provide a highly accurate switched capacitor circuit.

[Means to solve the problem]

In order to achieve the above object, in the present invention, in a switched capacitor circuit including the four switch circuits, a capacitive element, and an integrating circuit, when switching from an integrating state to a charging state, first controlling each switch circuit to turn off the fourth switch circuit, then turn on the third switch circuit, turn off the first and second switch circuit, and then turn on the first switch circuit, Also, when switching from charging state to integral state, first
means for controlling each switch circuit to turn off a switch circuit, then turn on a fourth switch circuit, turn off the first switch circuit, and then turn on the second switch circuit; It is configured to be prepared.

With the above configuration, the circuit of the present invention operates as follows.

That is, when switching from the integrating state to the charging state, first disconnect the integrating circuit side terminal of the capacitive element from the integrating circuit, first connect the integrating circuit side terminal to the first voltage terminal (for example, ground potential), and then Each switch circuit is controlled to disconnect the input side terminal of the capacitive element from the first voltage terminal and then connect the input side terminal to the input voltage terminal, and when switching from the charging state to the integrating state, First, disconnect the integrating circuit side terminal of the capacitive element from the first voltage terminal, then connect the integrating circuit side terminal to the integrating circuit, then connect the input side terminal of the capacitive element to the input voltage terminal, and then Each switch circuit is controlled to disconnect the input side terminal from the first voltage terminal.

As mentioned above, the four types of switch circuits are controlled by four types of control signals and turned on and off at different predetermined timings, creating a precision switched capacitor circuit that does not cause distortion due to clock noise. It becomes possible to realize this.

[Embodiments of the invention]

FIG. 1 is a diagram showing an embodiment of the present invention.

In FIG. 1, 1 to 4 are switch circuits, 16 is a switch control circuit, 21 and 22 are capacitive elements, 23 is an operational amplifier, 30 is a clock input terminal, 31 is a signal input terminal, and 32
is a signal output terminal, the switch circuits 1 to 4, the switch control circuit 16, and the capacitive element 21 constitute a sampling circuit, and the capacitive element 22 and the operational amplifier 23 constitute an integrating circuit.

In the device shown in FIG. 1, four types of switch circuits 1 to 4 are controlled by different control signals CLK-1-CLK-2, C
Controlled by LK-3 and CLK-4, they are turned on and off at different timings.

The switch control circuit 16 that outputs the four types of control signals described above can be composed of, for example, four logic gate elements 53 to 56 and three delay circuits 57 to 59, as shown in FIG.

Clock signal CL in the above switch control circuit 16
The relationship between K-0 and the four types of control signals CLK-1 to CLK-'4 has characteristics as shown in FIG. 2, for example.

Further, the switch circuits 1 to 4 are turned on when the control signal is "High" as in the case of FIG. 6, and 71 L
(In case of “IIJ”, it is turned off.

FIG. 3 is a diagram showing operating waveforms of the voltages 7 and V at nodes 7 and 8 in the circuit shown in FIG.

Hereinafter, the operation of the circuit shown in FIG. 1 will be explained based on FIGS. 2 and 3.

First, in the period t1, the switch circuits 1 and 3 are on, and the capacitive element 21 is charged with the voltage of the input signal.

In the charging state as described above, first, the switch circuit 3 is turned off at time T1.

At this time, the voltage at the input and output terminals of the switch circuit 3.

In other words, since the voltage vIl of the node 8 is always at the ground potential regardless of the input signal voltage, the switch circuit 3
The clock noise V generated from the clock signal is also always of a constant magnitude.

Next, when the switch circuit 4 is turned on at time T2, the node 8 is connected to the inverting input terminal (the input terminal of the integrator) of the operational amplifier 23, and the clock noise generated from the switch circuit 3 is integrated and the node 8 is The voltage 8 becomes the ground voltage again.

Next, when the switch circuit 1 is turned off at time T3, the voltage at the input/output terminal of the switch circuit 1 is the input signal voltage v1, so that the clock noise is affected by the input signal voltage.

However, since the switch circuit 4 is already turned on at that point, the amount of charge integrated into the capacitive element 22 of the integrating circuit is equal to the amount of change in the terminal voltage on the input terminal side of the capacitive element 21.
That is, it is determined by the voltage difference between the voltage v0 at time T and the voltage (ground voltage) at time T, which is the end of the integration period t5.

Therefore, the transient voltage change in the voltage V1, (2) during the period from t4 to 1s between time T and time T5 becomes irrelevant to the amount of integrated charge.

Therefore, even if voltage ■7 at node 7 becomes v2 due to clock noise generated in switch circuit 1, or voltage ■8 at node 8 becomes v6 when switch circuit 2 is turned on, the integrated charge Does not affect quantity.

If the switching from the charging period t□ to the integration period t is performed in the above-described order, the integrated charge will be accurately proportional to the input signal voltage.

On the other hand, when switching from the integral state to the charging state, the switch circuit 4 is first turned off at time T5.At this time, the input/output terminal voltage of the switch circuit 4 is the ground voltage, so the clock noise always has a constant magnitude. Occurs in

The subsequent switching order does not directly affect the integrated charge amount since the switch circuit 4 is already turned off. However, a small amount of voltage change at node 8 is transmitted through the parasitic capacitance of the switch circuit.

Therefore, at time T, the switch circuit 3 is turned on to fix the voltage vII of the node 8 to the ground voltage, and then,
Switch circuit 2 and switch circuit 1 at times T1 and Ts
If the switch circuit 1.2 is switched to a charging state, it will not be affected by the clock noise of the switch circuit 1.2 or the voltage change at the node 7.

The switch circuit is turned on and off in the order explained above.
By off-controlling, the integrated clock noise becomes constant regardless of the input signal voltage, so the integrated charge becomes a value exactly proportional to the input signal voltage, realizing a highly accurate switched capacitor circuit. Can be done.

Note that when sampling audio signals etc. using the circuit of the present invention, AC is used as an input signal, but analog/
When used as a digital converter, direct current may be used as the input signal6. In the switch control circuit shown in FIG. 4, the timing of control signals CLK-3 and CLK-4 (second
t2 and t6 in the figure) are determined. In addition, the delay circuit 58
The time t3 and t7 in FIG. 2 are determined by the delay time of , and the time t4 and 1s are determined by the delay time of the delay circuit 59.

Such a delay circuit can generally be easily realized by connecting an even number of inverter circuits.

Further, the length of the above delay time is set in consideration of the response speed of the switch circuits, etc. so that the operations of the respective switch circuits do not overlap. However, control signals CLK-1 and C
Since the time difference between t4 and tI, which is the time difference between I and -2, does not affect the accuracy of the integration operation, the switch circuit 1
If there is no problem even if circuits 1 and 2 are turned on at the same time and current flows, switch circuits 1 and 2 may operate in an overlapping manner. In that case, the times t4 and t can be set to timings close to 0.

Next, FIG. 5 is a diagram showing another embodiment of the present invention.
An example in which the present invention is applied to a switched capacitor circuit different from the illustrated embodiment is shown.

The circuit in Figure 5 is an oversampling type analog/
It is a digital conversion circuit.

In FIG. 5, 5 and 6 are switch circuits, Z4 is a voltage comparator, 25 is a delay circuit, 26 is a capacitive element, 27 is a polarity switching circuit, 33 is a reference voltage input terminal, 34 is an analog signal input terminal, and 35 is a This is a digital signal output terminal, and the same reference numerals as in FIG. 1 indicate the same components.

In the device shown in FIG.
4, the signal is converted into a digital signal, and this signal is used as a feedback signal for the next clock cycle.

Note that the polarity switching circuit 27 is connected to the switch circuits 5 and 6.
The reference voltage is integrated with either positive or negative polarity by switching the control signals input to the .

In addition, a control signal CLK for controlling the switch circuits 5 and 6
-1 and CLK-2 are the same as control signals for controlling switch circuits 1 and 2, and two sets of switch circuits 1 and 2 and the circuit of capacitor 21 in the switched capacitor integrator of FIG. By preparing two voltages and connecting them in parallel, it is possible to integrate two voltages at the same time.6 In the circuit shown in Fig. 5, two sets of switch circuits 3 and 4 are also used, and each switch circuit 4 is connected in parallel. Of course, it is also possible to configure the output to be connected to the input of the integrating circuit.

As described above, the switch control circuit of the present invention can be applied to various switched capacitor circuits.

〔Effect of the invention〕

As explained above, in the switch control circuit of the present invention, it is possible to eliminate the input signal voltage dependence of tallock noise generated from the switch circuit of a switched capacitor circuit.

Therefore, the integral operation, which is the basic operation of a switched capacitor circuit, can be performed with extremely high precision.
The effect of eliminating nonlinearity in the input/output characteristics of the switched capacitor circuit and suppressing the occurrence of distortion can be obtained.

Further, when the filter is configured with a switched capacitor circuit, since the output is an analog signal, the effect of lowering the distortion of the output signal can be directly obtained.

Further, when a switched capacitor circuit is applied to analog signal processing of an analog/digital converter, the effect of improving the conversion accuracy of digital output can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram of an embodiment of control signal waveforms in a switch control circuit of the present invention,
3 is an operating waveform diagram in the embodiment of FIG. 1, FIG. 4 is an embodiment diagram showing a specific configuration of the switch control circuit, and FIG.
6 is an example of a conventional device, FIG. 7 is an example of a switch control circuit in the conventional device, FIG. 8 is a control signal waveform diagram in the circuit of FIG. 6, 9th
The figure is a side view of a specific configuration of the switch circuit, and FIG. 10 is an operational waveform diagram of the device of FIG. 6. Explanation of symbols> 1 to 6... Switch circuit 15.16... Switch control circuit 21, 22.26... Capacitive element 23... Operational amplifier 24... Voltage comparator 25... Delay circuit 2
7...Polarity switching circuit 30...Clock input terminal 31...Signal input terminal 32...Signal output terminal 33...Reference voltage input terminal 34...Analog signal input terminal 35...Digital signal Output Terminal Patent Applicant Nippon Telegraph and Telephone Corporation Representative Patent Attorney Junnosuke Nakamura Figure 2 Off Figure 51 Page 8 Figure 9 Figure 10

Claims (2)

[Claims] (1) A first switch circuit connected between the input side terminal of the capacitive element and the input voltage terminal, and a second switch circuit connected between the input side terminal of the capacitive element and the first voltage terminal. a third switch circuit connected between the switch circuit, the integrating circuit side terminal of the capacitive element and the first voltage terminal, and the integrating circuit side terminal of the capacitive element and the input terminal of the integrating circuit; and a fourth switch circuit connected to the first to fourth switch circuits.
In the switched capacitor circuit, the capacitor is charged with the input voltage by turning on and off the switch circuit at a predetermined timing, and the charged charge is integrated by the integration circuit. When switching from an integration state in which the capacitive element is integrated to a charge state in which the capacitive element is charged, the fourth switch circuit is first turned off, then the third switch circuit is turned on, and then the second switch circuit is turned off. Each of the switch circuits is controlled to turn off the circuit and then turn on the first switch circuit, and when switching from the charging state to the integrating state, first the third switch circuit is turned on. , the fourth switch circuit is turned on, the first switch circuit is turned off, and the second switch circuit is turned on. A switch control circuit characterized by comprising means. (2) A plurality of each of the input voltage, the capacitor, the first switch circuit, and the second switch circuit are provided, and a plurality of input voltages are integrated simultaneously. Switch control circuit as described.