JPS61204572A - Frequency/voltage converter - Google Patents

Frequency/voltage converter

Info

Publication number
JPS61204572A
JPS61204572A JP4364685A JP4364685A JPS61204572A JP S61204572 A JPS61204572 A JP S61204572A JP 4364685 A JP4364685 A JP 4364685A JP 4364685 A JP4364685 A JP 4364685A JP S61204572 A JPS61204572 A JP S61204572A
Authority
JP
Japan
Prior art keywords
integrator
voltage
pulse
frequency
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4364685A
Other languages
Japanese (ja)
Inventor
Kenzo Watanabe
渡辺 健蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansho Co Ltd
Original Assignee
Sansho Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansho Co Ltd filed Critical Sansho Co Ltd
Priority to JP4364685A priority Critical patent/JPS61204572A/en
Publication of JPS61204572A publication Critical patent/JPS61204572A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute the monolithic integration and to select the polarity of the output voltage by constituting the reference voltage by a switched capacitor integrator, a pulse generating device and a switch control circuit. CONSTITUTION:A pulse is generated by a pulse generating device 2 each time an input signal voltage reaches a certain voltage value. A switch control circuit 3 forms a switch control signal by the pulse and the clock signal applied to a clock input terminal 32, charges the capacitor to constitute an integrator 1, to a reference voltage each time the pulse is outputted from the generating device 2 and the charging charge is integrated. The output voltage of the integrator 1 is in proportion to the integrated charge, and therefore, the voltage in proportion to the frequency of the input signal is obtained from an output terminal 12. Whether or not the integrator 1 is operated as a positive-phase integrator and operated as a reverse-phase integrator is executed by changing the switch sequence of the integrator 1 by the circuit 3. By the constitution, since the digital signal processing is main, integrating can be easily executed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はディジタル・アナログ変換器や計数器を用いず
に、実時間動作で人力信号の周波数に比例した電圧を得
る周波数・電圧変換器に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency-to-voltage converter that operates in real time and obtains a voltage proportional to the frequency of a human input signal without using a digital-to-analog converter or a counter.

従来の技術 実時間で作動する従来の周波数・電圧変換器は単安定回
路と積分器とで構成され、単安定回路で人力信号を一定
パルス信号に変換し、これを積分器で積分して周波数に
比例する電圧を得ている。積分器としては、抵抗とコン
デンサによる受動積分回路、演算増幅器と抵抗とコンデ
ンサによる能動積分回路、或いは、抵抗とコンデンサと
定電流源による積分回路が用いられている。
Conventional technology A conventional frequency/voltage converter that operates in real time consists of a monostable circuit and an integrator.The monostable circuit converts a human signal into a constant pulse signal, which is integrated by an integrator to calculate the frequency A voltage proportional to is obtained. As the integrator, a passive integrating circuit using a resistor and a capacitor, an active integrating circuit using an operational amplifier, a resistor, and a capacitor, or an integrating circuit using a resistor, a capacitor, and a constant current source is used.

発明が解決しようとする問題点 この従来の方式では、周波数を電圧に変換する感度が単
安定回路からのパルス信号のパルス幅に依存するため、
高安定な単安定回路を必要とする。又、出力電圧変動を
小さくするには積分時定数を大きくせざるを得す、この
ためには高抵抗と大きな容量・のコンデンサが必要とな
るのでモノリシック集積化しにくい、さらに、出力電圧
として正又は負のいずれかの極性の電圧しか得られない
等の問題があった。
Problems to be Solved by the Invention In this conventional method, the sensitivity of converting frequency to voltage depends on the pulse width of the pulse signal from the monostable circuit.
Requires a highly stable monostable circuit. Furthermore, in order to reduce output voltage fluctuations, it is necessary to increase the integration time constant, which requires a high resistance and large capacitance capacitor, which makes monolithic integration difficult. There were problems such as only being able to obtain a voltage of either negative polarity.

本発明はこれらの問題点を解決すべくなされたもので、
モノリシック集積可能で、入力信号周波数を正、負いず
れの電圧にも変換できる周波数・電圧変換器を提供する
ことを目的としている。
The present invention was made to solve these problems.
The object of the present invention is to provide a frequency/voltage converter that can be monolithically integrated and that can convert an input signal frequency to either positive or negative voltage.

問題点を解決するための手段 第1図は本発明の周波数・電圧変換器のブロック図であ
って、1はスインチド・キャパシタ積分器、2はパルス
発生器、3はスイッチ制御回路、4は基準電圧源である
。入力信号はパルス発生器20入力端子21に加えられ
、変換された電圧は前記積分器1の出力端子12から得
られる。スイッチ制御回路3は出力電圧の極性を選択す
るための信号が印加される出力電圧極性選択端子31を
有する。
Means for Solving the Problems FIG. 1 is a block diagram of the frequency/voltage converter of the present invention, in which 1 is a pinched capacitor integrator, 2 is a pulse generator, 3 is a switch control circuit, and 4 is a reference. It is a voltage source. An input signal is applied to the pulse generator 20 input terminal 21 and a converted voltage is obtained from the output terminal 12 of said integrator 1. The switch control circuit 3 has an output voltage polarity selection terminal 31 to which a signal for selecting the polarity of the output voltage is applied.

作  用 パルス発生器2は入力信号電圧がある電圧値に達する度
毎にパルスを発生する。スイッチ制御回路2はこのパル
スとクロ7り入力端子32に加えられるクロック信号と
からスイッチ制御信号を作り、スイッチド・キャパシタ
積分器に含まれているスイへチを制御して、パルス発生
器2からパルスが出力される度毎に該積分器1を構成し
ているキャパシタを基準電圧4に光電し、この充電電荷
を積分する。スイッチド・キャパシタ積分器1の出力電
圧は積分された電荷に比例するので、入力信号の周波数
に比例した電圧が出力端子12から得られる。スイッチ
ド・キャパシタ積分器lを正相積分器として動作させる
か、或いは逆相積分器として動作させるかは、出力電圧
極性選択端子31に加えられる信号を参照してスイッチ
制御回路3がスイ7チド・キャパシタ積分器lのスイッ
チ・シーケンスヲ変よることによって行う。当該積分器
1が正相積分器として作用する時は正極性の電圧に、逆
相積分器として作用する時は負極性の電圧に、入力信号
周波数は変換される。
Operation The pulse generator 2 generates a pulse every time the input signal voltage reaches a certain voltage value. The switch control circuit 2 generates a switch control signal from this pulse and the clock signal applied to the clock input terminal 32, controls the switch included in the switched capacitor integrator, and outputs the pulse generator 2. Every time a pulse is output from the integrator 1, the capacitor constituting the integrator 1 is photoelectrically charged to the reference voltage 4, and this charged charge is integrated. Since the output voltage of the switched capacitor integrator 1 is proportional to the integrated charge, a voltage proportional to the frequency of the input signal is obtained at the output terminal 12. Whether the switched capacitor integrator 1 is operated as a positive phase integrator or a negative phase integrator is determined by the switch control circuit 3 based on a signal applied to the output voltage polarity selection terminal 31. - By changing the switch sequence of the capacitor integrator l. When the integrator 1 acts as a positive phase integrator, the input signal frequency is converted into a voltage of positive polarity, and when it acts as a negative phase integrator, the input signal frequency is converted into a voltage of negative polarity.

実施例 第2図は本発明の実施例であって、デユーティ比50%
の対称方形波の周波数を電圧に変換する周波数・電圧変
換器の結線図で、対称方形波はパルス発生回路2の入力
端子21に加えられる。
Embodiment FIG. 2 shows an embodiment of the present invention, in which the duty ratio is 50%.
This is a wiring diagram of a frequency/voltage converter that converts the frequency of a symmetrical square wave into a voltage, and the symmetrical square wave is applied to the input terminal 21 of the pulse generation circuit 2.

この例ではパルス発生器2は二つのエフ・ジトリガ型D
フリップフロップ22.23と排他論理和ゲート24か
らなり、入力信号の立上りと立下りを出力電圧極性選択
端子31に印加される電圧が正の時はクロック信号入力
端子32に入力されるJクロック信号に同期して、出力
電圧極性選択端子31の電圧が負の時はクロック信号入
力端子33に入力されるφクロック信号に同期して検出
する。ここで、φクロック信号とφクロック信号は、入
力信号周波数よりもずっと高い周波数をもつ2相クロツ
クパルスでアル。
In this example, the pulse generator 2 has two F-di-trigger type D
It consists of flip-flops 22 and 23 and an exclusive OR gate 24, and when the voltage applied to the output voltage polarity selection terminal 31 is positive, the rising and falling edges of the input signal are J clock signals input to the clock signal input terminal 32. When the voltage at the output voltage polarity selection terminal 31 is negative, it is detected in synchronization with the φ clock signal input to the clock signal input terminal 33. Here, the φ clock signal and the φ clock signal are two-phase clock pulses with a frequency much higher than the input signal frequency.

スイッチド・キャパシタ積分器3は入力キャパシタ10
11積分キャパシタ102、ダンピング用キャパシタ1
03、ホールド用キャパシタ104ト、これらのキャパ
シタの充放電を制御するスイッチ105.106.10
7.108.109.110.111と演算増幅器10
0で構成されている。スイッチの横に書かれたクロック
信号の記号は、当該スイッチがオンとなるクロック信号
を示している。スイッチ105とスイッチ106の開閉
は、論理ゲートで構成されているスイッチ制御回路3に
よ−Jて制御されている。正の出力電圧極性が指定され
た時は入力信号の立上りと立下り時のiクロック信号で
スイッチ105が閉じてキャパシタ101が基準電圧4
に充電され、充電された電荷は次のφクロック信号でス
イッチ106が閉じるのでS分キャバシク102に転送
され、キャパシタ102を図示の極性に充電する。キャ
パシタ101の充電と転送は瞬時に行われるので、入力
信号及びクロック信号のパルス幅には依存しない。1秒
間にキャパシタ102が充電される回数は入力信号の周
波数に比例(この例では入力信号周波数の2倍)するの
で、積分器3の出力端子から人力周波数に比例した正の
電圧が得られる。
Switched capacitor integrator 3 has an input capacitor 10
11 Integral capacitor 102, damping capacitor 1
03, hold capacitor 104, switch 105.106.10 to control charging and discharging of these capacitors
7.108.109.110.111 and operational amplifier 10
Consists of 0. The clock signal symbol written next to a switch indicates the clock signal that turns on the switch. The opening and closing of the switches 105 and 106 are controlled by a switch control circuit 3 made up of logic gates. When a positive output voltage polarity is specified, the switch 105 is closed by the i clock signal at the rise and fall of the input signal, and the capacitor 101 is set to the reference voltage 4.
Since the switch 106 closes with the next φ clock signal, the charged charge is transferred to the S-minute cabassic 102, charging the capacitor 102 to the polarity shown. Charging and transfer of the capacitor 101 are instantaneous and therefore independent of the pulse widths of the input signal and clock signal. Since the number of times the capacitor 102 is charged per second is proportional to the frequency of the input signal (in this example twice the frequency of the input signal), a positive voltage proportional to the human frequency is obtained from the output terminal of the integrator 3.

負の出力電圧極性が指定された場合は、入力信号の立上
りと立下り時のφクロック信号でスイッチ105が閉じ
、キャパシタ101を図示の極性に充電する。この場合
には充電電流が同時にキャパシタ102を流れ、キャパ
シタ102を図示とは逆の極性に充電するので、出力端
子12には負の電圧が現われる。
When a negative output voltage polarity is specified, the switch 105 is closed by the φ clock signal at the rise and fall of the input signal, and the capacitor 101 is charged to the illustrated polarity. In this case, a charging current simultaneously flows through the capacitor 102 and charges the capacitor 102 to a polarity opposite to that shown, so that a negative voltage appears at the output terminal 12.

第3図は、65 k Hzの2相りロック信号φ、φを
使って第2図の実施例で得られた入力信号周波数対出力
電圧の関係であって、本発明の周波数変換器が広い周波
数範囲に亘って直線性良く、信号周波数を電圧に変換す
ることを示している。
FIG. 3 shows the relationship between the input signal frequency and the output voltage obtained in the embodiment of FIG. 2 using two-phase locking signals φ and φ of 65 kHz, and shows that the frequency converter of the present invention has a wide range. This shows that the signal frequency is converted into voltage with good linearity over the frequency range.

発明の効果 パルス発生器2とスイッチ制御回路3はディジクル信号
処理を主としているので、現状の集積技術で集積化でき
、スイッチド・キャパシタ積分器lもCMO5技術で集
積化できる回路である。従って、本発明の周波数・電圧
変換器はモノリシック集積が可能である。又、以上述べ
たように、変換感度がパルス幅には依存しないので高精
度の周波数・電圧変換が可能であり、出力電圧の極性も
選択できるので、本発明は応用上極めて有用である。
Effects of the Invention Since the pulse generator 2 and the switch control circuit 3 mainly perform digital signal processing, they can be integrated using the current integration technology, and the switched capacitor integrator 1 can also be integrated using the CMO5 technology. Therefore, the frequency-to-voltage converter of the present invention can be monolithically integrated. Furthermore, as described above, since the conversion sensitivity does not depend on the pulse width, highly accurate frequency/voltage conversion is possible, and the polarity of the output voltage can also be selected, making the present invention extremely useful in applications.

4、面の簡単な説明 第1図は本発明の周波数・電圧変換器のブロック図、第
2図は本発明の実施例を示す回路図、第3図は第2図の
実施例で得られた入力信号周波数対出力電圧の関係。
4. Brief explanation of aspects FIG. 1 is a block diagram of the frequency/voltage converter of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram obtained by the embodiment of FIG. 2. Relationship between input signal frequency and output voltage.

第1図、第2図において、1はスイ7チド・キャパシタ
積分器、2はパルス発生器、3はスイッチ制御回路。
In FIGS. 1 and 2, 1 is a switched capacitor integrator, 2 is a pulse generator, and 3 is a switch control circuit.

Claims (1)

【特許請求の範囲】[Claims] スイッチド・キャパシタ積分器(1)と、入力信号電圧
がある電圧値に達した時にパルスを発生するパルス発生
器(2)と、出力電圧極性選択端子(31)を有するス
イッチ制御回路(3)とから成り、前記積分器(1)の
入力端子(11)には基準電圧(4)が接続され、該積
分器(1)の出力端子(12)から出力を得る周波数・
電圧変換器。
A switch control circuit (3) having a switched capacitor integrator (1), a pulse generator (2) that generates a pulse when the input signal voltage reaches a certain voltage value, and an output voltage polarity selection terminal (31). A reference voltage (4) is connected to the input terminal (11) of the integrator (1), and a frequency
voltage converter.
JP4364685A 1985-03-07 1985-03-07 Frequency/voltage converter Pending JPS61204572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4364685A JPS61204572A (en) 1985-03-07 1985-03-07 Frequency/voltage converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4364685A JPS61204572A (en) 1985-03-07 1985-03-07 Frequency/voltage converter

Publications (1)

Publication Number Publication Date
JPS61204572A true JPS61204572A (en) 1986-09-10

Family

ID=12669625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4364685A Pending JPS61204572A (en) 1985-03-07 1985-03-07 Frequency/voltage converter

Country Status (1)

Country Link
JP (1) JPS61204572A (en)

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