SU1666967A1 - Analogue phase meter - Google Patents

Abstract

The invention can be used in devices for measuring phase shift. The goal is to improve the accuracy of phase shift measurements. The analog phase meter contains amplifiers 1 and 2, integrators 3 and 4, bit switches 5 and 6, comparators 7 and 8, upper limits 9 and 10, lower limit stops 11 and 12, and an output adder 13. The goal is achieved by using comparators 7 and 8 to control the bit switches, and limiters 9-12 to guarantee the voltage on some inputs of the comparators 7 and 8, which are higher than the voltage on their other inputs. 2 Il.

Description

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Yo

1

oh oh u

Os VI

limiters 11 and 12 of the lower level and output adder 13. The goal is achieved by using comparators 7 and 8 to control the bit keys

The invention relates to an electrical measurement technique, namely to measuring a phase shift angle between two harmonic signals.

The purpose of the invention is to increase the accuracy of measuring the phase shift of the input signals.

Fig. 1 is shown from the rumurpa of the phase meter in Fig. 2 — time diagrams.

The phase meter contains the first I and Itoron 2 limit amplifiers, the first 3 and second 4 integrators, bit switches 5 and 6 in the integrator feedback circuits of the first 7 and second 8 comparators, the first 9 and second 10 upper limiters of the first 11 and second 12 low limiters 4 output sum of a torus P Inputs of limit amplifiers 1 and 2 are connected to input buses The output of amplifier limiter 1 is connected to the first offenses of integrators 5 and 6 and limiters 11 and 10 The output of amplifier limiter 2 is connected to the second inputs of integrators 5 and 6 and entrances the boundaries 9 and 1 of the limiters 9 and 10 are connected respectively to the direct inputs of the comparators 7 and 8, and the outputs of the limiters 11 and 12 to the inverse inputs of the comparators 7 and 8; the outputs of the comparators 7 and 8 are connected (correspondingly to the control inputs of the keys 5 and B. The output of the integrator 3 is connected to the inverted input of the adder 13. The output of the integrator 4 is with the direct input of the adder 13 The output of the adder 13 is the output of the device.

The phase meter works as follows.

The sinusoidal input voltages Ui and U2 are fed to the inputs of limiting amplifiers 1 and 2, which form two-pole square pulses Uz and 1) 4 at their outputs (Fig. 2a, b). The amplitudes of the voltage pulses are the same and are determined by the value of pr. the voltage drop across the diodes of the limiting amplifiers 1 and 2, since the diodes manufactured in a single technological cycle on a single substrate (for example, 2С223В) are used;

9 12 - to guarantee voltage at some inputs of comparators 7 and 8. exceeding the voltage at their other inputs 2 or more

ww

are fed to the inputs of integrators 3 and 4 and to the inputs of limiters 9-12. Limiters 9 and 10 produce a limitation on the upper level, and the voltages U4 and Uz are formed at their outputs (Fig. 2g, and). Limiters 11 and 12 produce a limitation on the lower level, and on their dyes, the voltages Uz and ( Fig. 2e, k). The voltages Uz and W are fed to the inverse and direct inputs of the comparator 7 Voltages Uz and are fed to the direct inverse inputs of the comparator 8 The presence of limit switches 9-12 ensures the accuracy of the operation of the comparators 7 and 8 when the sum of the voltages Ib-tLM is equal to zero the account of guaranteed overvoltage of 1Uz over ILUl, which is achieved by adjusting the resistor of the limiter 11. and I Uz I over I U4 I, achieved by adjusting the resistor of the limiter 12 At the output of the comparator 7, rectangular pulses of voltage Y, appear. and at the output of the comparator 8, rectangular pulses with voltage Ua (fig. 2h, l), arriving at the control inputs of the keys 5 and b.

The integrators 3 and 4 simultaneously integrate the sum of the voltages Uz and U4 (Fig. 2c).

In the time interval from ti to t4, bit switch 5 is open, and the output voltage of integrator 3 is described by the expression

14

Ur, Ki / (Uz + U4) dt and

In the time interval from the moment 1h to te, the discharge switch 6 is open. And the integrator output voltage 4 is described by the expression

 Ki / (Uz + U4) dt,

13

where Ki is the transfer coefficients of the integrators 3 and 4. are chosen the same for both inputs of each integrator 3. 4.

Each of the integrators 3 and 4 in one open-loop cycle of their bit switches integrates two adjacent opposite-polar impulses of the sum Uz + U4, and due to the shift of the integration cycles by half the period, the trapezoidal pulses Ue and U are formed at the half of the period forms, but of different polarity (Fig. 2d). The difference of the instantaneous amplitudes of these pulses in time is proportional to the difference of 180 ° and the phase shift angle of the input signals.

Isolation of the difference Uy-Ue is performed by the output adder 13, the operation of which is described by the expression

Up K :().

With this interlaced i4H, the coefficient K.2 ü K | bi) is the same for the inverting and non-inverting current adder 13

BI-: the total voltage of the adder 13 is pr / sh,. but in fig. 2d

Since the speed of the comparator1 is much higher than that of the operational amplifiers and is limited to a few 5-7) nanoseconds, the accuracy of the phase meter operation is much higher than this, while maintaining accuracy, the frequency range of the input signals is expanded to higher frequencies. In addition, with this device there is no need to use an additional two-pole power supply for biasing the control signals, which simplifies the design of the device.

Claims (1)

Claims of the invention Analog phase meter comprising first and second limiter amplifiers, first and second integrators with two input resistors each and each with its own discharge keys in reverse circuits, the first and second bit control units, and the output adder, and the conclusions of the first The integrator input resistors are connected to the output of the first amplifier limiter, the terminals of the second integrator input resistors are connected to the output of the second amplifier limiter, and the outputs of the first and second integrators connect respectively, with inverting and non-inverting inputs of the output adder, characterized in that, in order to improve accuracy, two upper limiters and two lower limiters are introduced into it. and control units for bit switches are made in the form of comparators, while the direct inputs of the first and second comparators are connected to the outputs of the corresponding upper level stops, the inverse inputs of the first and second comparators are connected to the outputs of the corresponding lower level stops, and the inputs of the first low level limiter and the second limiter the upper level is connected to the output of the first amplifier limiter, and the inputs of the first limiter of the upper level and the second limiter of the lower level are below during the second limiting amplifier FIG. 2