SU1185251A1 - Apparatus for automatic selection of measuring limits - Google Patents

Description

The invention relates to electrical engineering and is intended for use in the construction of multi-range analog measuring devices. five

The purpose of the invention is to provide applicability at voltages with wide frequency and dynamic ranges.

Figure 1 shows the functional diagram of the device for. automatic selection of measurement limits "in figure 2 a, b - approximate zone of operation of the comparators; on fig.Z - timing diagram of signals illustrating the operation of the device.

The device consists of a DC amplifier 1 (Fig. 1), with a block of 2 reference resonators in the feedback circuit ^ d, connected in parallel to each other through the corresponding keys of the measurement range switch 3, a reversible counter of 4 pulses, a decoder 5, comparators & 6 and 7 with zero-level symmetric non-interrupting zones of operation, single vibrators 8 and 9, · integrating KS-chain 10, block 11 for setting the counter to zero state, peak detector 12, block 13 sampling-storage, synchronous detector 14, block 15 pack ION.

Position 16 on the diagram indicates the input of the device, and positions 17 and 18 measuring outputs, respectively, 35 alternating and direct currents. The outputs of the reversible counter 4 through the decoder 5 are connected to the control inputs of the unit 3 switching the measurement limits. The comparator 6, having a zone of operation covering the zero level (Fig. 2a), is connected by an output via a single vibrator 8 to a summing input of a reversible counter 4. Comparator 7, having a zone of operation, not covering a zero level (Fig. 2b) is connected by an output through a single vibrator 9 to his subtractive input. The reset input of the reversible counter 4 is connected to the output of the counter installation unit 11 to the zero state. Peak detector 12 and sampling-storage unit 13 are connected in series. The signal input of the peak detector 12 is connected to the input of a DC gain of $ 1. Integrating the KS chain 10 is connected between the output of block 13 sample-storage and signal-ί

input of the synchronous detector 14. The output of the synchronous detector 14 is connected to the inputs of Comparators 6 and 7 .. The input of control unit 15 is connected to the input of DC amplifier 1, and the outputs are connected to the control inputs of peak detector 12, sampling-hokey 13 and synchronous detector 14.

The device works as follows.

After turning on the power unit 11 generates a pulse that sets the reversible counter 4 to the zero state. In this case, the limit switching unit 3 connects to the amplifier 1 a resistor from block 2, which corresponds to the coarsest limit of measurement of the input AC voltage υ _χ (FIG. 3 a). AC voltage from the output of the amplifier 1 is fed to the input of the peak detector 12.

At the time of transition of voltage b through the zero level upwards, the control unit 15 generates a short impulse ϋ _UP p.

(Fig.36), resetting the peak detector 12 to the zero state. During the next time interval (6 _ή , 6 „), equal to a quarter of the voltage period and _in , peak detector 12 monitors the maximum value of this voltage. During the time interval (6 ^, 6 ^) the peak detector 12 stores the recorded amplitude value (Fig. 3g). At time b ^ voltage transition and _6x through the zero level in the direction of decreasing the control unit 15 generates a short pulse and ^ pr. ₁₅ (fig.Zv), allowing the recording of voltage from the output of the peak detector

12 in block 13 sample storage.

♦

If during the next voltage period ϋ _βχ its amplitude value changes, for example, decreases, the described cycle of operation of the peak detector 12 and sample-storage unit 13 will repeat with the only difference that the output of unit 13 will abruptly decrease during the next overwrite pulse. Thus, at the output of the sampling-storage unit 13 there will be a step voltage of positive polarity with an amplitude equal to the voltage amplitude and _6x in the previous period (FIG. 3D). Integrating

3 - * 1185251 4

The EC-chain 10 smoothes the output voltage. The parameters of this chain are chosen so that its characteristic frequency is higher than the highest frequency of the measured signals.

Step signal having an amplitude equal to the amplitude voltage υ _Βχ, is fed to the input of the synchronous detector 14. The transmission ratio w syn- hronnsgo detector 14 is equal to 1, the EC • the phases and the voltage _VC and _the reference pulses at the control input are the same, and -1 if these phases are opposite. Consequently, the polarity of the output voltage depends on the phase relationships of the signal and the reference pulses. This property of the proposed device is convenient for the implementation of measurements according to the scheme "modulation, amplification, demodulation". If this is not necessary, the control input of the synchronous detector 14 is connected, as shown in the diagram, to the corresponding output of the control unit 15 25.

If the voltage at the output of the synchronous detector 14 becomes less in absolute value of the threshold of the comparator 6, then at the output of the last ^ 0 the signal "1" will appear, triggering the one-shot 8, the pulse from the output of which goes to the summing input of the reversible counter 4. state to 35 units, so that the amplifier 1 unit 3 switching the measurement limits connects a resistor from unit 2, corresponding to a more sensitive limit, the measurement. This process will be repeated until the voltage amplitude at the output of the device becomes in absolute value.

more than the trigger threshold of the comparator 6, but less than the threshold срабат _ρ7 triggering of the comparator 7.

When the amplitude of the voltage increases at the output of the device is higher than the threshold and the _{pickup of} the comparator 7 is triggered, a “1” signal appears at its output, triggering the one-shot 9, the pulse from the output goes to the subtracting input of the reversing counter 4. The state of the latter decreases by one, resulting in connects a resistor corresponding to a coarser measurement limit. Since the trigger thresholds of comparators 6 and 7 are symmetrical about zero, the above process proceeds equally for both positive and negative polarities of the output voltage.

The frequency range of the proposed device is limited by the speed of the applied amplifier 1, the peak detector 12 and the block 13 of the sample-storage. The dynamic range of the device depends on the number of measurement limits and the accuracy of the amplifier 1.

Thus, the proposed device automatically selects the limit for measuring alternating voltages in a wide frequency and dynamic ranges. The device implements the fastest (within one period) conversion of an alternating voltage into a constant one. At the same time, the choice of measurement limits does not exceed the value

^{from the} left ^ ^Ν ' ^Τ *

where N is the number of switchable limits;

T - period of stress υ _6χ .

Φι / ί 1

1185251

Claims (2)

DEVICE FOR AUTOMATIC SELECTION OF MEASUREMENT LIMITS,. <> Holding a constant eye amplifier with a block of reference resistors in the feedback circuit, connected in parallel through the corresponding keys of the measuring limits switching unit, reversible pulse counter, the outputs of which through the decoder are connected to the control inputs of the specified switching unit , two comparators with non-overlapping trigger zones symmetric with respect to the zero level, the first of which, having a trigger zone, covers This zero level is connected by an output through one of the single-oscillators to a summing input of a reversible pulse counter, and the second one, which has a response zone that does not cover the zero level, is connected to an output of an one-off vibrator through its other subtractor input, which is different in that enabling applications at voltages with wide frequency and dynamic ranges, a control unit, a peak detector and a sample-storage unit, a synchronous detector, n And the signal input of the peak detector is connected to the output of the DC amplifier, the integrating QC-chain is connected between the output of the sampling-storage unit and the signal input of the synchronous device, whose output is connected to the inputs of both comparators, the input of the control unit is connected to the input of the DC amplifier, and the outputs with control inputs: peak detector, sampling-storage unit and synchronous detector. $ Ц 118525 one 1185251 2