JPS6011492B2 - Analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed, high resolution analog-to-digital converter.

Conventionally, successive approximation type analog-to-digital converters use high-speed elements to reduce conversion processing time to lowS.
The following models with a disassembly of 14 bits or more have been designed, but they are extremely expensive.

On the other hand, with the development of microcomputers in recent years, control circuits that perform fairly sophisticated processing can now be obtained in a small size and at low cost. An object of the present invention is to provide a high-speed, high-resolution analog-to-digital converter at low cost.

In other words, the present invention provides an advanced analog-to-digital converter at a lower cost than conventional products even if a microcomputer-based control circuit as described above or an equivalent logic circuit is used to control the analog-to-digital converter. It focuses on the fact that

The present invention connects an input signal, a reference voltage, and circuit elements such as capacitors and resistors to an operational amplifier by switching between them to create modes such as sampling, comparison, double voltage generation, and feedback, thereby creating an analog signal. It is characterized by converting it into a digital signal.

This will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The terminal 8x is an analog signal input, and the terminal 0d is a digital signal output. The non-inverting input of the differential operational amplifier U is configured to be supplied with the reference voltage Es via the switch So, the potential of the input terminal Ex via the switch S, and the common potential via the switch S7. There is. Further, the inverting input of the operational amplifier U is coupled to the output voltage of the amplifier U via a switch S2. Further, one end of a capacitor C is connected to this inverting input, and the other end is connected to a common potential point via a switch S3. The output of the operational amplifier U is coupled to the digital output terminal ○d via a switch S9 and a resistor R3, and a switch S6 and two equal-value series resistors R.
, and connected to a common potential via R2. The potential at the connection point between these resistors R and R2 is determined by the switch S3 mentioned above.
is combined with The switch S6 is connected to the ground potential via the switch S3, and is connected to the capacitor C2.
The other end is connected to the non-inverting input of the amplifier U via the switch S4, and to the ground potential via the switch S5. Digital output terminal 0
A Zener diode D is connected between d and the common potential, and is led to the control circuit CONT. This control circuit CONT is for controlling the opening and closing of the above-mentioned switches So to S8, and is constituted by a microcomputer or a logic circuit. In addition, switch So~
Ss is constituted by a semiconductor switch. The operation of the circuit configured in this way will be explained.

FIG. 2 is a control flowchart of the control circuit CONT. In FIG. 2, ■ to ■ indicate the first to fifth modes, respectively, and the states of the switches So to S9 in each mode are as shown in Table 1. The equivalent circuit diagram of the first mode is shown in FIG.

In this state, a voltage equal to the analog input voltage Ex is sampled as the potential V, across the capacitor C. The equivalent circuit of the second mode is as shown in FIG.

Table 1 In this state, the potential V, across the sampled capacitor C, is compared with the reference voltage Es.

If the zener voltage of the zener diode D, is set to 5V, which is the TTL level, the voltage of the output terminal ○d will be V, kuE.
When s OVV. >Es, it becomes 5V.

This is done by controlling the control circuit CON as shown in the flowchart of FIG.
It is determined by T. Now, if V,<Es, then
A third mode is set.

The equivalent circuit at this time is shown in FIG. That is, since the values of resistors R and R2 are equal, the capacitors C,
A voltage 12 times the voltage V, across the voltage V, appears at the output of the amplifier U and charges the capacitor C2. In the comparison of the second mode described above, if V,>ES, the fourth mode is set as shown in the flowchart of FIG.

This equivalent circuit is as shown in FIG. That is,
A reference voltage Es is coupled to the non-inverting input of the operational amplifier U;
-2 (V'-Es) appears at its output, which is charged to capacitor C2.

Since the voltage obtained across the capacitor C2 in the third or fourth mode is a negative voltage, its polarity is reversed and fed back in the fifth mode to charge the capacitor C again.
The equivalent circuit of the fifth mode is shown in FIG. This provides a new voltage V2 and cycles back to the second mode. When the modes are cycled in this way, each time the voltage Vi across the capacitor C and the reference voltage Es are compared in the second mode, the voltage of OV or 5V obtained at the output 0d is equal to the initial input voltage Bx becomes a digitized binary signal.

Next, the reason why the signal obtained at this output 0d is a binary signal obtained by digitizing the input voltage Ex will be explained.

Generally, in the (i11)th step, the capacitor C.
The voltage V... across the board is V, 10, = 2 (V, - aiEs)...
[11]

Here a' is the value of the output ○d at that time, "1" or "
0". Transforming the '1} formula, VFa/ES Juura V...
‐‐‐‐‐‐{2, is obtained.

This is achieved by substituting i=0, 1, 2, 3, . . . n into this equation '21.

Here, Vo is equal to the voltage Ex of the first analog input terminal, so EX: must be ES+Ge(a・EbeV2)=
MoE3mo・ES+Shadow: False, E3 Juuraku a2ES+Za3
): is S + (mugi. juura) Esu v3 = false ten (mugi, sua20...juugo an) ES + ticket vM≠舷ju (mugi, sua
It becomes ES.

Here, n is the value when sampling the terminal voltage Ex for the first time, and it becomes 0, so EXi wide i≧. Enjoy... ■.

This [Formula 41] is nothing but a digital binary output. In this way, an analog-to-digital converter can be obtained by controlling the switches So to S9 with a control circuit using a simple circuit configuration.

In recent years, control circuits from outside the microcomputer have become available at fairly low cost, so the circuit of the present invention is sufficiently economical compared to conventional devices. Further, the circuit of the present invention has an excellent feature that it essentially has an automatic zero function and does not require zero adjustment of an operational amplifier.

That is, when the capacitor C is charged with a voltage in the first mode or the fifth mode, an offset voltage V is generated between both differential inputs of the operational amplifier U. When s occurs, Vi=
VI-, 1V.

s……[It becomes 51.

Also, when obtaining twice the voltage in the third or fourth mode, the fin level V^ at the connection point of resistors R and R2 is V^i-(
V'+VOS).

Substituting formula 51 into this, it becomes V=-VI-, and the offset voltage V is automatically canceled out.

This is an extremely excellent feature that can increase the precision of analog-to-digital converters. Furthermore, since the output signals are transferred in time series, only one signal line is required.

Furthermore, by sequentially repeating the same steps, there is no element that limits the resolution, and in principle an infinitely large resolution library can be obtained. Furthermore, the conversion speed is determined by the response speed of the semiconductor element used as the switch and the processing speed of the control circuit, and a conversion speed of about 1 millisecond can be extremely practically constructed. In addition, in the above explanation, it was stated that this analog-to-digital converter is provided with its own control circuit, but this control circuit is not necessarily used exclusively for this analog-to-digital converter. For example, it is also possible to configure other peripheral circuits to be controlled simultaneously.

In this case, other control circuits control this angle. The same holds true if we consider that the digital converter is also controlled.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a control flow diagram of the control circuit. FIG. 3 is an equivalent circuit diagram of the first mode. FIG. 4 is an equivalent circuit diagram of the second mode. FIG. 5 is an equivalent circuit diagram of the third mode. FIG. 6 is an equivalent circuit diagram of the fourth mode. FIG. 7 is an equivalent circuit diagram of the fifth mode. Rare 1st figure, 7th figure, 2nd figure, 3rd figure, 4th figure, 5th figure, 6th figure

Claims (1)

[Claims] 1 An analog input terminal is connected to one input of the differential operational amplifier, and a first capacitor C_1 is connected to the other input, and sufficient negative feedback is provided to the differential operational amplifier to increase the voltage of the analog input terminal to the above level. First capacitor C_1
A first mode in which the reference voltage E_s is applied to one input of the differential operational amplifier, the first capacitor C_1 is connected to the other input, and the voltage V_i across the capacitor and the reference voltage E_s are and a second mode in which the first capacitor C_1 is connected to the other input of the differential operational amplifier and the second capacitor C_2 is connected to the output.
The voltage across the first capacitor C_1 is V_
a third mode in which a voltage (2×V_i) twice that of i is obtained at the output of the differential operational amplifier and the second capacitor C_2 is charged with that twice the voltage (2×V_i); A reference voltage E_s is applied to one input of the operational amplifier, the first capacitor C_1 is connected to the other input, and a voltage (2(V_i - E_s) twice the difference between the voltage V_i across the capacitor and the reference voltage E_s is applied. )) at the output of the differential operational amplifier to charge the second capacitor C_2, and a fourth mode to feed back the voltage charged in the second capacitor C_2 to the input of the differential operational amplifier. The first mode is followed by the second mode, and the first capacitor C is set in the second mode.
If the voltage V_i across _1 is lower than the reference voltage E_s, the second mode is followed by the third mode; if it is higher, the second mode is followed by the fourth mode; the third mode or the fourth mode is followed by the fifth mode. a control circuit for controlling the plurality of switches so that the mode returns to the second mode after the fifth mode, and the comparison output of the differential operational amplifier for each of the second modes is made into a digital output. An analog-to-digital converter characterized by being configured as follows.