JPS62245724A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To assure, the monotonousity even when capacitors of a capacitor array have an error by supplying a control signal selecting (2<n>-1) capacitors from a decoder outputting (2<n>-1) control signals and inputting an m-bit digital input signal. CONSTITUTION:The capacitor array has capacitors whose unit capacitance is 1C and consists of (2<n>-1) capacitors C1-Cm whose one electrodes are connected in common. Further, (2<n>-1) switches S1-Sm connecting selectively the other electrodes of the (2<n>-1) capacitors to a ground potential or a reference voltage VR in response to a control signal, a decoder 1 inputting an n-bit binary code and outputting outputs Q1-Qm as (2<n>-1) control signals, and a capacitor C0 whose capacitance is 1C and connected between the common connecting point of the capacitor array and the ground potential are provided. Even when the capacitors constituting the capacitor array have an error, the analog output voltage is increased/decreased according to the increase/decrease in the binary number as the digital input signal and its monotonousity is assured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital-to-analog converter, and in particular,
In a digital-to-analog converter using a capacitive string,
If the binary code you enter increases or decreases by 1,
The present invention relates to a digital-to-analog converter that guarantees monotonicity in which the analog output voltage increases or decreases accordingly.

〔overview〕

The present invention provides a digital-to-analog converter using a capacitance string, in which the capacitance string is configured with (2n-1) unit capacitances having the same capacitance value, and control for selecting the (2n-1) capacitances is provided. The signal is input by inputting an m-bit digital input signal (2n-
1) Monotonicity is guaranteed even if there is an error in the capacitance of the capacitor array by supplying the predetermined control signals by a decoder that outputs them.

[Conventional technology]

There is a circuit system for digital-to-analog converters that uses a capacitor array in which multiple unit capacitances are arranged.
It has the advantage of being suitable for integrated circuits. This circuit system is shown in the literature (11) and is shown in FIG.

In Fig. 2, capacitors 01 to C7 constitute a capacitor string with one electrode commonly connected, and the capacitance values are C+=2°・C, C2
=2n-C,, C3=2n・c, -...-1C,,
Binary weighting is performed as =2n-'·C.

Here, C is the value of the unit capacitance, and the capacitors C2 to C6 are made by connecting a plurality of unit capacitors to improve the relative accuracy of the capacitance.

One electrode of each of the capacitors C3 to C0 is connected to a switch 8.
1 to Sfi to the ground potential or reference potential. Switches S1-S.

is controlled by an n-bit input digital signal and operates as an n-bit digital-to-analog converter. capacity lc
, are connected between the common connection point of the capacitor string and the ground potential, and C,
= has the value of IC.

The output voltage v0 of the capacitor string in FIG. 2 is calculated using the law of conservation of charge and is expressed as follows.

Here, is 0 depending on the n-bit input digital signal.
or a coefficient that takes the value of 1, where ``e'' is the voltage of the reference potential. (Equation 11 shows that an output voltage V0 proportional to the binary number represented by the sign of n bits of the input digital signal is obtained, and the circuit in FIG. 2 operates as an n-bit digital-to-analog converter.

Reference 11) Jie, L., McCleary et al. (J.
L.

MaCreary et al), [Total-MO3 charge redistribution A/D conversion technology - Part 1 (Δ11-MOS Char
ge redistribution analog-to
-Digital conversion tech
hniques-1” artl)” IEEE Journal, Solid State Electronic Circuits (I E E E J, 5ol
id-State C1rcits) Volume 5C-10, pages 371-379. December 1975.

[Problem that the invention seeks to solve]

The conventional digital-to-analog converter described above has the disadvantage that monotonicity cannot be ensured when the capacitance has an error. "Monotonic" means that when the binary code input to the digital-to-analog converter increases or decreases by 1, the output analog voltage necessarily increases or decreases.

In FIG. 2, digital input signals S, ~b,.

(binary code) increases, the digital-to-analog converter output takes on a quantized analog value, and the output increases stepwise, making the output voltage at the i-th step
. When set to 1, C0+Σbm'ct.

V, i = V*
-(21C0+C, 4------...-+C.

becomes. Here, V8>0, and the relationship between i and the binary code is as follows.

i=Σbk, 2 is -1, . . . - Song (3) When there is an error in the capacitance, the probability that the absolute value of the error will become larger increases as the capacitance value increases. For example, in the example shown in Figure 2,
. tends to have the largest error, C,=2n-'・C
+ΔC, the output voltage V at the i-th step. ic, from formula (2), 1−−−−+41, and in a step-up where b and l change from “0” to “1”, the amount of change Δ■1 in the output voltage Vat becomes, but ΔC
Since is an error of the capacity 12fi-'·C, it is possible that ΔC<-t C .

When ΔC<-IC, the value in parentheses in equation (5) is negative, so Δv
, <0, and a phenomenon occurs in which the output decreases as the input binary code increases.

That is, the circuit shown in FIG. 2 may lose monotonicity if there is a certain amount of error in the capacitance.

An object of the present invention is to provide a digital-to-analog converter that guarantees monotonicity even when there is an error in capacitance by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a digital-to-analog converter using a capacitor string, wherein the capacitor string is composed of (2n-1) (n is a natural number) unit capacitors having equal capacitance values and having one electrode commonly connected. , (2n-1) switches that selectively connect the other electrodes of the (2''-1) unit capacitors to the first reference potential or the second reference potential according to the control signal, and n bits. a decoder that manually outputs the 2n-1) binary code of the control signal, and one unit capacitor connected between the common connection point of the capacitor string and the first reference potential. It is characterized by

[For production]

The decoder decodes an n-bit digital input signal (binary code), and when it takes a breather to i=Σ b,...2, outputs Q1 to Q are rlJ and the rest are "0".
A control signal is output to switch the switch 81 to the button to the second reference potential side. Therefore, an analog voltage corresponding to the digital input signal is output from the output.

In this case, the difference in output voltage between the i-th step and the (i-1)th step is Δ■. , is given by Δ■, where the voltage of the second reference potential is ■8. is always a positive value.

Therefore, even if there is an error in the capacitors forming the capacitor string, for example, the analog output voltage increases or decreases in accordance with the increase or decrease in the binary number as the digital input signal, and its monotonicity is guaranteed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In this embodiment, the capacitor array has a capacitance value of a unit capacitance IC, and is composed of (2″=1) (n is a natural number) capacitance values CI, cz, −1C1 with one electrode commonly connected. , select the other electrode of each of the (2″-1) capacitors CI, C2, −.-1C1 to the ground potential, which is the first reference potential, or the reference voltage VR, which is the second reference potential, according to the control signal. (2n-1) switches S, ,S,
,...-1S.

and a decoder 1 which inputs an n-bit binary code and outputs outputs Q1, C2, . It includes one capacitor itco connected between the common connection point of the capacitor array and the ground potential.

The feature of the present invention is that (2n-1) capacitors c1, C2, -1 having a capacitance value of unit volume ff1lc are
C1 and (2n-1) switches! S+, Sz, -・
, S, and a decoder l are provided.

Next, the operation of this embodiment will be explained. switch S,
~S1 is controlled by the outputs Q1~Q of the decoder 1. When the decoder 1 decodes the digital input signals S, ~b, (binary code), it operates to set the outputs Q, ~Qi to "1" and the rest to "0", and as a result, switches 81 to Switch the SM to the reference voltage vR side. At this time, I≦i≦2n-1 and m = 211 1 is selected.

Output voltage at the i-th step■. Five is (CI+
C2+-・-・10C,) −・−(6), so when there is no error in the capacitance, Co =C+=Ct−−−−−−−=C4−−−・・−
By substituting =C, =C into equation (6), we get: Since there is a relationship of m=2n-1, equation (7) becomes the same equation as equation (11), and this example is different from the conventional one shown in Fig. 2. As in the example, it operates as an analog-to-digital converter.

Next, monotony when there is an error in capacitance will be explained. First, use (6) 2 to calculate the output voltage ■ at the i-th step. , and the output voltage Vo (i-H) at the (i-1)th step is calculated, and the following is obtained.

Equation (8) is a general equation that shows the increase in output voltage when the input binary code increases by 1. C0, CI,・
Since C1 and Cz are capacitance values, they always take positive values, and since v<Q, the right side of equation (8) is always positive regardless of the presence or absence of an error. That is, in this embodiment, since the output voltage always increases when the input binary number increases, monotonicity is guaranteed even if there is an error in the capacitance.

〔Effect of the invention〕

As explained above, the present invention provides a digital-to-analog converter using a capacitor string, in which the capacitor string is (2n-
1) consists of unit capacitances with the same capacitance value, and the above (2n-
1) A control signal for selecting each of the capacitances is given as the output of a decoder that manually inputs an n-bit digital input signal and outputs (2n-1) predetermined (2n-1) control signals. This has the effect of guaranteeing monotonicity even if there is an error in the capacitance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing a conventional example. 1...Decoder, b1-b7...Digital input signal, Co"'C-, C6-C, l"'capacitance, Sl
""5lll %81~SR...Switch, Vo...
・Output, vlI...Reference voltage.

Claims (1)

[Claims] (1) In a digital-to-analog converter using a capacitive string, one electrode of the capacitive string is commonly connected (2^n-
1) Consisting of (n is a natural number) unit capacitors with equal capacitance values, the other electrode of each of the (2^n-1) unit capacitors is connected to a first reference potential or a second reference potential according to a control signal. (2^n-1) switches that are selectively connected to the potential, a decoder that inputs an n-bit binary code and outputs (2^n-1) control signals, and the capacitance string. A digital-to-analog converter comprising one unit capacitor connected between a common connection point and the first reference potential.