JPS59112223A - Capacity type converter - Google Patents

Abstract

PURPOSE:To compensate the nonlinearity of a sensor part by using a pulse width signal which has a duty ratio corresponding to the capacities of a couple of capacitors and a pulse width signal which has a constant duty ratio. CONSTITUTION:A capacity and pulse width converting circuit C/P detects the capacities of a couple of variable capacitors C1 and C2 and a reference capacitor C3 and outputs pulse width signals PW1-PW3 having corresponding duty ratios. The circuit which includes an inverting amplifier IA1 and switches SW1 and SW2 generates an output regarding the product of the difference in duty ratio between the pulse width signals PW1 and PW2 and a set voltage Vr and the circuit which includes an inverting amplifier IA2 and switches SW2 and SW4 generates an output regarding the product of the difference in duty ratio between the pulse width signals PW2 and PW3 and the set voltage Vr. The set voltage Vr is controlled on the basis of those voltages. An output is obtained from a filter circuit FC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive transducer using a pair of capacitors in which a movable electrode is displaced in accordance with a measured quantity such as pressure or differential pressure, and the capacitance of at least one of the capacitors is changed.

In general, capacitive converters have the disadvantage of poor linearity due to the influence of stray capacitance that exists in parallel with a pair of capacitors. Furthermore, in the case of metal diaphragms such as differential pressure transducers and pressure transducers in which the movable electrode is displaced according to the amount to be measured, the relationship between the amount to be measured and the change in capacitance can often be expressed as a hyperbola, and the sensor section There was also nonlinearity. .

The present invention uses a pair of capacitors in which the volume of one of the capacitors changes depending on the quantity to be measured, and provides a first pulse width signal with a duty ratio corresponding to the capacitance of one of the pair of capacitors and a duty ratio corresponding to the capacitance of the other capacitor. obtain a second pulse width signal and a fifth pulse width signal with a constant duty ratio, and obtain an output voltage related to the product of the difference in duty ratio of the first pulse width signal and the second pulse width signal and the set voltage. In addition to obtaining the first. The sum of the current related to the product of the duty ratio difference between one of the second sills width signals and the fifth pulse width signal and the set voltage, the current related to the output voltage, and the reference current becomes zero. By controlling the set voltage as described above, a capacitive converter is realized which can effectively compensate for the above-mentioned nonlinearity.

FIG. 1 is a connection diagram showing an embodiment of the first embodiment of the present invention converter.

In the figure, C1 and C2 are a pair of variable capacitors, including a movable electrode 10 that is displaced according to a measured quantity such as differential pressure, and a fixed electrode 11.1 that is disposed opposite to this movable electrode 10.
2 and 6, C3 is a reference capacitor with a constant capacitance. C/P is a capacitive pulse width conversion circuit that detects the capacitances of a pair of variable capacitors CC and a reference 1' 2 capacitor C3, and generates a pulse width signal pw with a duty ratio corresponding to the capacitances of C1, C2, and C3, respectively.
1. pw2. It outputs pw3.

An example of a specific configuration of the C/P is shown in FIGS. In Figure 3, 5w11, 5W12, and 5W13 are switches such as field effect transistors connected in parallel to the first capacitors C1, C2, and C3, and pG is the period T.
and a pulse generator that outputs a pulse Pc with a constant time width t8, BAl, BA2. BA3 is a buffer amplifier, cpl, cp2. cps is a comparator, G1. G2. Each G3 is a Noah gate. , 5W
11.8W12 and 5W13 are simultaneously driven by a pulse Pc from the PG with a constant period T and a constant pulse width t as shown in FIG.

S turns on 3, Oylc turns C
□, when the charge charged in C2-Ca is discharged and turned off, the resistor R11' R1□.

C1, C2, with the current from the DC power supply Va via R13.
C3 is full 1) 1. be done. As a result, the charging voltage vc1 of C1, C2, and C3. vc2. vc3 becomes as shown in FIG. 4(b)K. Comparator Cp1. Cp2. B at Cp3
Al, BA2. vCl given via BA3,
vC2, vc3 are monitored, vc11vc2. When vc3 reaches a certain value 'VbK, the outputs of Cpl, C20 and cps are inverted as shown in FIG. vc
l, vc2. The time until vc3 reaches vb, that is, the time during which C1, C2, and C3 are charged, is tx, t2
If y ts, then t1* t2* t
s is the resistance R□1. The values of R1□ and R□3 are R1□-R12
=R13=R, then t1= kC□
(1) t2=kC2(2) ts-hc3(3) However, k=-R11'n (1-Vb/Va)
Since pwl, pw2. The duty ratio of pw3 corresponds to the capacities of C□, C2, and C3, respectively.

The capacitive pulse width conversion circuit c1p in FIG.
By driving the switch sw1□ with the output Q of FF1 and driving the switch sw1□ with the output 4 of FF□, the pair of capacitors C□ and C2 are charged and discharged as shown in Figure 6 (A), ←). It is made to repeat and cause self-excited oscillation. Period of self-excited vibration Tl-1: O D between time t1 when cl is charged and time t2 when C2 is charged (=t1
+t2), υ, the output Q of FF□ generates a pulse width signal P'l11 of duty resolution 1 according to the capacitance of CL as shown in Figure 6 (c), and the output Q of FF1 generates a pulse width signal P'l11 as shown in Figure 5. ) A pulse width signal Pw with a duty ratio S is generated depending on the capacitance of C2 as shown by K. -Flip 70-tub FF that is reset by the output of the two-way comparator CP2 and reset by the output of the comparator Cp3
The output ζ of 2 drives the switch sw□3, and the capacitor C
3 is charged and discharged as shown in Figure 6), and the output Q of FF2 is
As shown in FIG. 6(f), pressure is applied to obtain a duty register pulse width signal PW3 corresponding to the capacitance of the capacitor c3.

Oite again in Figure 1, swl, 8w2.8w3.5w
41' are switches, SW is the pulse width signal pw1
8w2 and 5W4U pulse width signal pw2, 8w3 is driven by pulse width signal pW3, respectively, 8w2 and 8w
4 turns on and off the set voltage Vr, swl and 8w
3 are inverting amplifiers IA1 . It turns on and off the voltage -Vr inverted by IA2. Note that electronic switches such as field effect transistors are also suitable as the switches sw to SW4. FC is operational amplifier Op
This is a filter circuit using a filter circuit that smoothes the voltage turned on and off by swl and the voltage turned on and off by SW2 to obtain an output voltage 0 corresponding to the sum thereof. The IC is an integrating circuit using an operational amplifier Op2, which adds and integrates the currents applied to the input (-) to obtain the set voltage Vr. Then, the voltage turned on and off by the set voltage Vrt switch SW4 is applied to the input (-) via the resistor R4, and the voltage -V obtained by inverting the set voltage Vr by IA2 is applied via the variable resistor R5.
A voltage that turns r on and off with switch SW3 is applied, an output voltage Vo is applied via variable resistor R6, and resistor R7
A reference voltage Vs is applied via.

In the converter of the present invention configured as above, the period T of the pulse width signal is equal to the time constant ClR4°CXR5 of the integrating circuit IC.
If Vr is the DC component of the output voltage of the integrating circuit IC when it is sufficiently short compared to , and reaches a steady state, the average input current of the integrating circuit IC is zero, so the filter circuit F
When the DC component of the output voltage of C is vO, the following relationship holds true.

Similarly, if the period T of the pulse width signal is sufficiently short compared to the time constant CFR3 of the filter circuit FC, then the DC component v of the output voltage of the filter circuit FC when the steady state is reached is
O becomes (+ From equations (4) and (5), vO becomes 4 5 and is not affected by changes in the period T of the pulse width signal. Equation (6) and equation (1) , (2) and (3)
By substituting/substituting the formula, Vo can be expressed by the following formula.

On the other hand, the capacitance of the variable capacitors C1 and C2 is determined by setting the initial capacitance to Co and the movable electrode 10 and the fixed electrode 11 (12
) is the reference interval between d (when y=0) and the stray capacitance is C5, the output voltage vO changes as follows. Here, if the variable resistor R5 is adjusted and α is selected, the output voltage V
l) is 9, the influence of the stray capacitance Cs can be removed3. Therefore, if the resistance value of the variable resistor R6 is adjusted to satisfy the following,
The output voltage vO is as follows, and since R7 and RA l dr Vs are constant values, the output voltage Vo is determined by the displacement Jt as shown in Figure 2 (A).
If x is set accurately, if the output voltage is adjusted to be 0 as shown in Figure 2 (B), then Figure 2 (C)
As shown in the figure, the increase rate decreases as the displacement amount x increases, making the input-output relationship non-linear. Moreover, the magnitude of the nonlinearity can be set by changing the value of the resistance value R61. Therefore, when converting differential pressure or pressure into displacement using a metal diaphragm, for example, the amount to be measured and the movable electrode 1 3, that is, the nonlinearity of the sensor section can be corrected.

Note that in the above, the pulse width signal PW2 causes the switch SW4 to
, the case where the switch SW3 is driven by the pulse width signal PW3 has been exemplified, but as shown in FIG.
is applied to one input terminal of the NOR gate G via the inverter V, and the pulse width signal pw is applied to the other input terminal of G4.
is added to the output terminal of G, and a pulse width signal pw4 (
4) and drive the switch SW with this pulse width signal PW4, the inverting amplifier A2
and switch SW3 can be omitted. In this case, the influence of the stray capacitance tcs can be removed by selecting the capacitance of the reference capacitor 5 as C3t''Cs, and the nonlinearity can be corrected by adjusting the value of the variable resistor R6. The case where the non-linearity is corrected by adjusting is illustrated as an example, but if the output voltage vO is amplified by the amplifier A and then applied to the integrating circuit IC via the resistor R6 17 as shown in FIG. For the output type, the pressure Vo is as follows, where the gain of the good amplifier is β and C3-CB.The nonlinearity can be corrected by adjusting the gain β of amplifier A.In addition, in Fig. 8, amplifier A is used as the amplifier A, and the calculation A non-inverting version consisting of an amplifier OP3 and a voltage dividing resistor R8 is shown, the gain β of which is given by the voltage dividing ratio of the voltage dividing resistor R8 and can be adjusted by the position of the brush of the voltage dividing resistor R8. .

Furthermore, in the above description, the case where the switch SW is driven by the pulse width signal pW2 or pw has been exemplified, but if the amplification driver is inverted as shown in FIG. 9, it can be driven by the pulse width signal pw. Output voltage V in this case.

Assuming α-value C6/C3, it becomes as follows, and can be linearized by adjusting the resistor R6 or the gain β of the amplifier A. In this case as well, if the switch SW4 is driven by the pulse width signal pW with a duty ratio tl-3 (see Figure 4a)) corresponding to the difference between the capacitance a of the capacitor C1 and the capacitance of the reference capacitor C3, the inverting amplifier IA2 Switch SW can be omitted. Furthermore, in the above description, the switches swl and sw2 are connected to the pulse width signals pw1. Needless to say, it is difficult to drive with pw2. In addition, in FIGS. 8 and 9, switch SW
1~Resistor R1 connected between one end of SW4 and the reference point
1 (21, R41, R51 are for eliminating the influence of stray capacitance of elements and wiring of sw, ~sw4. In addition, instead of resistors R1° R2+, R41, R51, SW,
A switch that turns on and off in the opposite phase to SW4 may be used, or 8W1 to SW4 may be used as transfer switches.

In addition, in the above description, using the reference capacitor C3, the 6 rus width t
3 to obtain a constant pulse width signal pW3, as shown by the dotted line in FIGS. 3 and 5, a monomulti, etc., which is driven by the output of the pulse generator PG and the comparator Cp2 and is turned on for a certain period of time, is illustrated. One circuit, circuit MM
If the reference capacitor C3 is obtained by using the reference capacitor C3, the reference capacitor C3 can be omitted. In this case, αt3yokC1,l″
α or t3 is selected so that l or t3 becomes kCs.

Furthermore, in the above description, the capacitance of the capacitor C1 changes according to the relationship shown in equation (8) with respect to zero displacement of the pair of capacitors C□ and C2, and the capacitance of the capacitor C2 becomes C2I! ICO+C8
may be fixed. In this case, the output voltage vO is RA
x However, since C3=C8, if you adjust the resistance value of variable resistor R6 to satisfy
The output voltage vO can correct the nonlinearity of the sensor section. In the case of 2, as shown in FIG. 11, the pulse width signal PW2 is applied to one input terminal of the NOR gate G5 through the input terminal IV, and the pulse width signal PW is applied to the other input terminal of G5, A pulse width signal PW1. Obtain a pulse width signal pw6 (see O0 in FIG. 4) corresponding to the difference in duty ratio between PW2 and PW2,
If the switch SW2 is driven by this pulse width signal PW, the inverting amplifier IA1 and the switches and switches SWi can be omitted. Note that when capacitor C1 is fixed to Cx "Co + Cs and the capacitance of capacitor C2 is changed according to the relationship in equation (9), the output voltage vO may be applied to the integrating circuit IC via an inverting amplifier. .

As explained above, the present invention provides a capacitive converter that can effectively correct nonlinearity with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a connection diagram showing an embodiment of the converter of the present invention, Fig. 2 is an explanatory diagram of its operation, and Fig. 3 is an example of a specific configuration of a capacitive pulse width conversion circuit used in the converter of the present invention. Connection diagram,
FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 is a connection diagram showing another example of a specific configuration of the capacitive pulse width conversion circuit.
Figure 6 is a waveform diagram for explaining its operation, Figures 7 to 11
The figure is a connection diagram showing another embodiment of the converter of the present invention. C1, C2...pair of capacitors, C3...reference capacitor, C/P...capacitance pulse width conversion circuit, SW,
SW4...Switch, IC...Integrator circuit, FC...
・Filter circuit, op1 to OPa... operational amplifier, I
A□, IA2...Inverting amplifier, A...Amplifier, V
s...Reference voltage.

Claims (1)

[Claims] A pair of capacitors, the capacitance of at least one of which changes depending on the measured quantity, a first pulse width signal with a duty ratio corresponding to the capacitance of one of the pair of capacitors, and a second pulse width signal with a duty ratio corresponding to the capacitance of the other capacitor. a circuit for generating a pulse width signal and a third pulse width signal with a constant duty ratio, and an output voltage related to the product of the difference in duty ratio of the first pulse width signal and the second pulse width signal and a set voltage. a circuit for obtaining the first. The sum of the current related to the product of the duty ratio difference between one of the second pulse width signals and the third pulse width signal and the set voltage, the current related to the output voltage, and the reference current is A capacitive converter comprising a circuit for controlling the set voltage so that it becomes zero.