JPH0448280B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive differential pressure transmitter that converts displacement based on a change in a physical quantity such as pressure into an electrical signal via capacitance, and is particularly applicable to a sensor. The present invention relates to a capacitive differential pressure transmitter that eliminates the influence of distributed capacitance formed around the.

<Prior Art> Such a capacitive differential pressure transmitter detects the flow rate or pressure of various processes as a change in capacitance, converts it into an electrical signal, and transmits it to a distant receiving section, etc. It is used in

An example of such a conventional capacitive differential pressure transmitter is shown in the fourth example.
It is shown in the figure and will be explained.

Fixed electrodes 11 and 12 are arranged facing the moving electrode 10, and have a capacitance that functions as a sensor capacitance.
C ₁ and C ₂ are formed. In addition, the moving electrode 10
A distributed capacitance C _s is formed between and the case.

The connection point between the capacitances C ₁ and C ₂ is connected to the input end of the inverter G ₁ , and a constant value current limiting circuit CC ₁ is connected in negative feedback between the output end and the input end of the inverter G 1 .
The output end of inverter _G1 is an n-bit counter.
It is connected to the input terminal CL of CT ₁ , and its output terminal Q _o is connected via a NAND gate G ₂ to a fixed electrode 11 forming the first electrode of capacitance C ₁ , and at the same time connects an inverter G ₃ and a NAND gate G ₄ . It is connected via a fixed electrode 12 forming a second electrode of capacitance C ₂ . Furthermore, the other input ends of the NAND gates G ₂ and G ₄ are connected to the output end of the inverter G ₁ .

With this configuration, the first positive feedback loop to the inverter _G1 is formed by the NAND gate _G2 and the capacitance _C1 ,
Inverter G ₁ with NAND gate G ₄ and capacitance C ₂
The output of the counter _CT1 forms a second positive feedback loop to the NAND gate _G2 ,
The oscillation is continued by switching alternately through _G4 . The output of the counter _CT1 is smoothed by a filter circuit _FC1 .

Now, as shown in Figure 5A, the output A of NAND gate _G2 is set to high level "H", and the voltage +E is applied here.
When this occurs, the capacitance increases due to its rise.
The composite capacitance C _t of C ₁ , distributed capacitance C _s , and electrostatic capacitance C ₂ is charged in series, and the input terminal of inverter G ₁ suddenly reaches a constant voltage and rises almost vertically as shown in Figure 5B. . Therefore, the change e ₁₀ in the terminal voltage of the distributed capacitance C _s with respect to the threshold level V _TH of the inverter G ₁ is expressed by the following equation.

e ₁₀ = C ₁ / C ₁ + C _t E (1) At this time, the output C of the inverter G ₁ is at the low level “L”, but the constant value current limiting circuit CC ₁ is connected between the input and output terminals of the inverter G ₁ . Since they are connected, the charges in the distributed capacitance C _s and the capacitance C ₂ immediately start discharging via the constant value current limiting circuit CC ₁ and the output impedance of the inverter G ₁ .
However, since the discharge current i caused by this discharge is regulated to a constant current value by the constant value current limiting circuit _CC1 , the voltage at the input terminal of the inverter _G1 decreases linearly as shown in FIG. 5B. Discharge time required to decrease to threshold level V _{TH 10}
is obtained from the following equation.

it ₁₀ = e ₁₀ (C ₁ + C _t ) (2) From equations (1) and (2), t ₁₀ = C ₁ E/i (3).

When the voltage drops to the threshold level _VTH of inverter _G1 , the output C of inverter _G1 is inverted and becomes the "H" level (Fig. 5C). As a result, the output A of the NAND gate _G2 becomes "L". level,
The voltage at the input terminal of inverter G ₁ has the same value as equation (1) and has the opposite polarity e′ ₁₀ . After this, constant value current limit circuit
CC ₁ causes a discharge of opposite polarity to occur linearly.
As a result, when the threshold level V _TH of inverter G ₁ is reached, the output C of inverter G ₁ becomes the fifth
Invert as shown in Figure C. Since this reverse polarity discharge is also carried out with a constant value of current i, the discharge time t′ ₁₀
is also equal to t ₁₀ , so t ₁₀ = t′ ₁₀ (4).

These relationships are the same even if the output of the counter CT ₁ is switched to the capacitance C ₂ side after the counter CT ₁ has counted a predetermined value.
The following formula holds true.

t ₂₀ = C ₂ E/i (5) Therefore, during the “H” period of the pulse signal obtained from the output Q _o of the counter CT ₁ , the capacitance C ₁ is “L”
The period corresponds to the capacitance C ₂ , and if this is averaged by the filter circuit FC ₁ , the calculation result of C ₁ /(C ₁ +C ₂ ) related to the duty ratio of the pulse signal is obtained. This calculation result provides a value proportional to the displacement of the moving electrode 10, that is, the differential pressure (P _H - P _L ).
Furthermore, the distributed capacitance C _s has been removed.

<Problems to be Solved by the Invention> However, although the distributed capacitance C _{s distributed between the moving electrode 10 and the case can be removed by conventional techniques, the distributed capacitance C s} distributed between the moving electrode 10 and the conversion circuit can be removed. If a distributed capacitance such as, for example, a distributed capacitance C _s0 is formed at both ends of the constant value current limiting circuit CC ₁ as shown in FIG. 4, an error will occur. When the distributed capacitance C _s0 is formed across the constant value current limiting circuit CC ₁ , considering equation (1), there are two cases: switching to the capacitance C ₁ side and switching to the capacitance C ₂ side. Since the voltage changes e _{10 and e 20} at the input end _{of inverter} G ₁ that occur in This has the disadvantage of being different and creating an error factor.

<Means for Solving the Problems> The present invention solves the above problems, and furthermore, the present invention solves the above-mentioned problems, and furthermore, it solves the problems that occur when analog voltages corresponding to differential pressure are digitally processed by a microcomputer and transmitted as analog quantities to a load. In order to eliminate conversion errors caused by the analog-to-digital conversion means, the input end is connected to a common connection point to which the first and second sensor capacitances that change according to the differential pressure and one end of each of the sensor capacitances are connected. detection gate means for changing an output level in response to a change in input voltage exceeding a predetermined threshold; and negative feedback means for supplying a negative feedback current to a common connection point in response to a change in the output level of the detection gate means. , a counting means that changes the output level every predetermined number of times of the change period of the output level of the detection gate means, and one of the first and second sensor capacitors is selected and detected based on the change in the output level of the counting means. a first transmitting a change in the output level of the gating means to excite each other end of the first and second sensor capacitors;
and a second excitation gate, and operating means for changing the excitation amplitude to the first and second sensor capacitors by gradually decreasing and increasing the excitation voltage of the first and second excitation gates in accordance with the output level of the counting means. , a microcomputer equipped with an analog-to-digital conversion means and a signal transmission means for transmitting an analog signal to a load; a return means controlled by the microcomputer for converting an output value of the signal transmission means into a voltage signal and returning the voltage signal; Each output of the return means and the operating means is read into a microcomputer via an analog-to-digital conversion means, and these outputs are controlled in a predetermined relationship to provide an output value of the signal transmission means. be.

<Example> Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is an overall block diagram showing one embodiment of the present invention. The moving electrode 10 is connected to the input end of a buffer gate _G5 serving as a detection gate means, and its output end is connected in negative feedback to the input end of the buffer gate _G5 via an inverter _G6 and a constant current limiting circuit _CC1 . There is.

Further, the output terminal of the buffer gate _G5 is connected to the input terminal CL of a counter _CT2 as a counting means. The arbitrary bit output terminal Q _o of the counter CT ₂ and its inverted output terminal _o are connected to one end of the input of AND gates G ₇ and G ₈ which function as excitation gates, respectively. Note that the counter _CT2 can have any arbitrary structure such as binary or decimal.

The other input ends of AND gates G ₇ and G ₈ are respectively connected to the output end of buffer gate G ₅ .
The output terminals of AND gates G ₇ and G ₈ are connected to fixed electrodes 11 and 12, respectively, and a first positive feedback loop (buffer gate G ₅ -AND gate G ₇ -capacitance
C ₁ − buffer gate G ₅ ) and the second positive feedback loop (buffer gate G ₅ − AND gate G ₈ − capacitance
C ₂ − buffer gate G ₅ ) is formed.
These positive feedback loops are connected to the output of counter CT ₂ .
Q _o and the loop switching signal which is the output of the inverted output terminal _o
It can be switched to either one by LS1 and LS2.

The inverted output terminal _o of the counter CT ₂ is applied to the input terminal of the integrating circuit Q ₁ , and the integrating circuit Q ₁ is connected to the counter CT ₂
When the high level period of the output terminal Q _o is longer than the high level period of the inverting output terminal _o , the potential at the output terminal of the integrating circuit Q ₁ gradually increases, and in the opposite case, a variable voltage V is generated that gradually decreases. Activate AND gates G ₇ and G ₈ .

For example, C-MOS devices are used for the AND gates G ₇ and G ₈ , and the logic output level thereof is provided by the energizing voltage values +E and V, or V and -E. The variable voltage V is a value within the range of the energized fixed voltage +E.

Distributed capacitances C _s1 and C _s2 inserted between the moving electrode 10 and the output end of the buffer gate G ₅ and between the moving electrode 10 and the output end of the inverter G ₆ are connected to the inside of the electronic component coupled to the moving electrode 10. Alternatively, it is a representative representation of the so-called inter-electrode distributed capacitance of the component distributed in the lead wire of the component.

Buffer gate G ₅ , inverter G ₆ , counter
CT ₂ and the integrating circuit Q ₁ are composed of C-MOS devices and are energized with a fixed voltage of ±E.

X ₁ and X ₂ are multiplexers, and variable voltage V
is input to the microcomputer μCOM via multiplexer _X1 and analog-to-digital converter ADC. Multiplexer x ₁ ,
_X2 is selected by a selection signal MSS provided by the microcomputer μCOM. The microcomputer μCOM executes the calculations described below and outputs it to the analog signal transmission circuit ASC, where it is converted to a unified current of, for example, 4 to 20 mA, and the line
Transmitted via L ₁ and L ₂ .

The current flowing through lines L ₁ and L ₂ is converted into a corresponding voltage by the return circuit ARC and sent to the multiplexer.
X ₂ and is read into the microcomputer via the analog-to-digital converter ADC.

Note that the DSR is an arbitrary setting device that sets coefficients and constants necessary for measurement calculations of the microcomputer μCOM.

Next, the operation of the embodiment shown in FIG. 1 constructed as above will be explained using the waveform diagram shown in FIG. 2.

The AND gate G7 or _G8 is opened and closed in a complementary manner by the loop switching signals LS1 _and LS2 (Fig. 2 A and _B ) from the output terminals Qo and _o of the counter _CT2 ,
Either the positive feedback loop on the capacitance C ₁ side or the C ₂ side is selected, and voltages as shown in FIG. 2 E and F are output to the output terminals of AND gates G ₇ and G ₈ .

With one of these positive feedback loops selected, when the output level of buffer gate _G5 changes as shown in Figure 2 D, AND gate _G7 or _G8
As shown in FIG. 3C, positive or negative voltage changes e ₁ (=e' ₁ ) and e ₂ (=e' ₂ ) are generated at the input terminal of the buffer gate G ₅ via the buffer gate G 5 . The voltage changes e ₁ and e ₂ that occur in this case are as shown in the following equation, taking into account the charge transfer to the input terminal of the buffer gate G ₅ via each capacitor.

e ₁ = C ₁ (EV) + C _s1・2E−C _s2・2E/C ₁ +C ₂ +C _s
+C _s1 +C _s2 (6) e ₂ =C ₂ (E+V) +C _s1・2E−C _s2・2E/C ₁ +C ₂ +C _s
+C _s1 +C _s2 (7) These voltage changes e ₁ and e ₂ are kept constant by a constant current i at the input terminal of buffer gate G ₅ via inverter G ₆ and constant value current limiting circuit CC ₁ as shown in Fig. 2 (c). It takes time t ₁ (=t' ₁ ) and t ₂ (=t' ₂ ) at the slope of , to be negatively fed back and pulled back to the threshold level of buffer gate G ₅ . From the above explanation, the times t ₁ and t ₂ in this case are as shown in the following equations.

t ₁ = e ₁ (C ₁ + C ₂ + C _s + C _s1 + C _s2 )/i (8) t ₂ = e ₂ (C ₁ + C ₂ + C _s + C _s1 + C _s2 )/i (9) Here, the return circuit ARC If the conversion constant is K ₁ , the output current I ₀ , and the return voltage is V _f , then I ₀ =V _f /K ₁ (10).

Also, if the conversion constant in the analog-to-digital converter ADC is K ₂ and the conversion constant determining the V _f /V ratio given from the setting device DSR is K ₃ , then K ₂ V _f = K ₂ VK ₃ (11) Become. This expression is an arithmetic expression for the microcomputer μCOM to execute control calculations.

An increase or decrease in the variable voltage V of the integrating circuit Q ₁ appears as a difference in the generation time of the loop switching signals LS ₁ and LS ₂ , and when the time widths of the loop switching signals LS 1 and LS 2 are equal, the variable voltage V maintains a constant value. Stabilize. Balance of loop switching signals LS1 and LS2 is not changed.
This is nothing but the coincidence of t ₁ and t ₂ in equations (8) and (9). accordingly
From the condition t ₁ = t ₂ and equations (6) to (9), we obtain V=EC ₁ −C ₂ /C ₁ +C ₂ (12).

Here, the capacitances C ₁ and C ₂ are expressed by the following equation, where C ₀ is the capacitance when the differential pressure ΔP is zero, and K ₄ is a constant.

C ₁ = C ₀ 1/1 - K ₄ ΔP (13) C ₂ = C ₀ 1/1 + K ₄ ΔP (14) Substituting these equations into equation (12), V = K ₄ E・ΔP (15 ) becomes.

Substituting equations (10) and (16) into equation (15) yields I ₀ =K ₃ K ₄ /K ₁ E·ΔP (16), and output current I ₀ is proportional to differential pressure ΔP. Moreover, this equation (16) does not include the distributed capacitances C _s1 and C _s2 between the moving voltage 10 and the electronic components, and the influence of these distributed capacitances is removed.
It also does not include the conversion constant K ₂ of the analog-to-digital converter ADC.

Note that FIG. 2 shows the output waveform of the inverter _G6 .

FIG. 3 shows the specific configuration of the signal transmission circuit and return circuit.

For the external power supply E _b , a three-terminal regulator is connected to a series circuit of the output transistor Q ₂ and the current limiting resistor R ₁ .
A circuit in which Q ₃ is connected in parallel, a feedback resistor R ₅ and a load resistor R _L are connected in series. A stabilized output voltage is obtained at the output terminal of the 3-terminal regulator _Q3 , and this output voltage is divided by resistors _R2 and _R3 , and is divided into three levels of circuit common voltages COM, +E, and -E. be done. Bypass capacitors are installed between resistors R ₂ and R ₃ and between resistor R ₃ and the case.
C _b1 , C _b2 , and C _b3 are connected.

The operational amplifier Q ₄ , the resistor R ₄ , and the capacitor C _i constitute an integrator circuit. The operational amplifier Q ₄ is energized with a voltage ±E, and its non-inverting input terminal (+) is connected to the resistors R ₂ and R ₃ . It is connected to the circuit common COM as well as to the circuit common COM. Microcomputer μCOM
The control output USD is applied to the inverting input terminal (-) of the operational amplifier _Q4 via the resistor _R4 , and is integrated by the capacitor C _i connected between this and the output terminal. The output end of operational amplifier Q ₄ is connected to the gate of output transistor Q ₂ , and the control output USD
The impedance of the output transistor Q ₂ is changed correspondingly to control the output current I ₀ .

In the return circuit _ARC , the output current is
I ₀ is converted to a return voltage V _f . This return voltage V _f is transferred to the microcomputer μCOM via the multiplexer X ₂ and the analog-to-digital converter ADC.
is loaded into.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, the distributed capacitance formed between the moving electrode and the electronic component coupled to it is removed, and the analog voltage corresponding to the differential pressure is reduced. A highly accurate capacitive differential pressure transmitter can be realized by eliminating conversion errors caused by the analog-to-digital conversion means that occur when the signal is digitally processed by a microcomputer and transmitted to a load as an analog quantity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a waveform diagram showing the waveforms of each part of the embodiment in FIG. 1, FIG. 3 is a block diagram showing the specific configuration of the signal transmission circuit and return circuit in FIG. 1, and FIG.
The figure is a block diagram showing the configuration of a conventional capacitive differential pressure transmitter, and FIG. 5 is a waveform diagram showing waveforms of various parts in FIG. 4. 10... moving electrode, 11, 12... fixed electrode,
G ₅ ... Buffer gate, G ₆ ... Inverter, G ₇ ,
G ₈ ...AND gate, CC ₁ ... Constant value current limit circuit, C ₁ , C ₂ ... Capacitance, C _s , C _s1 , C _s2 ... Distributed capacitance, μCOM ... Microcomputer, ADC
...Analog-to-digital converter, ASC...signal transmission circuit, ARC...return circuit, DSR...setting device,
CT ₁ , CT ₂ ... Counter, LS1, LS2... Loop switching signal, MSS... Selection signal, V... Variable voltage.

Claims (1)

[Claims] 1. First and second sensor capacitors that change according to the differential pressure, and an input end connected to a common connection point to which each end of the sensor capacitors are connected, and in response to a change in input voltage that exceeds a predetermined threshold. detection gate means for changing an output level; negative feedback means for supplying a negative feedback current to the common connection point in response to a change in the output level of the detection gate means; and a predetermined period of change in the output level of the detection gate means. A counting means that changes the output level every time, and a change in the output level of the detection gate means is transmitted by selecting one of the first and second sensor capacitors depending on the change in the output level of the counting means. first and second excitation gates that excite the other ends of the first and second sensor capacitors, and energizing voltages of the first and second excitation gates are gradually decreased and increased in accordance with the output level of the counting means; a microcomputer comprising an operating means for changing the excitation amplitude to the first and second sensor capacitors, an analog-to-digital conversion means, and a signal transmission means for transmitting an analog signal to a load;
a return means that is controlled by the microcomputer and converts the output value of the signal transmission means into a voltage signal and sends it back; and a return means that converts the output value of the signal transmission means into a voltage signal and sends it back; A capacitive differential pressure transmitter that provides an output value of the signal transmission means by reading the signals into the signal transmission means and controlling each of these outputs in a predetermined relationship.